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git01.mediatek.com / filogic / uboot / b8da47bd76bafad96c41cf285accbffd6e467324 / . / arch / powerpc / cpu / mpc83xx / hrcw / Kconfig
blob: 44f66cd5287731313d5f93533ad361c708d995fc [file] [log] [blame]
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]1menu "Reset Configuration Word"
2
3choice
4 prompt "Local bus memory controller clock mode"
5
6config LBMC_CLOCK_MODE_1_1
7 bool "1 : 1"
8
9config LBMC_CLOCK_MODE_1_2
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]10 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]11 bool "1 : 2"
12
13endchoice
14
15choice
16 prompt "DDR SDRAM memory controller clock mode"
17
18config DDR_MC_CLOCK_MODE_1_2
19 bool "1 : 2"
20
21config DDR_MC_CLOCK_MODE_1_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]22 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]23 bool "1 : 1"
24
25endchoice
26
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]27if !ARCH_MPC8313 && !ARCH_MPC832X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]28
29choice
30 prompt "System PLL VCO division"
31
32config SYSTEM_PLL_VCO_DIV_1
33 depends on !ARCH_MPC837X
34 bool "1"
35
36config SYSTEM_PLL_VCO_DIV_2
37 bool "2"
38
39config SYSTEM_PLL_VCO_DIV_4
40 depends on !ARCH_MPC831X
41 bool "4"
42
43config SYSTEM_PLL_VCO_DIV_8
44 depends on !ARCH_MPC831X
45 bool "8"
46
47endchoice
48
49endif
50
51choice
52 prompt "System PLL multiplication factor"
53
54config SYSTEM_PLL_FACTOR_2_1
55 bool "2 : 1"
56
57config SYSTEM_PLL_FACTOR_3_1
58 bool "3 : 1"
59
60config SYSTEM_PLL_FACTOR_4_1
61 bool "4 : 1"
62
63config SYSTEM_PLL_FACTOR_5_1
64 bool "5 : 1"
65
66config SYSTEM_PLL_FACTOR_6_1
67 bool "6 : 1"
68
69config SYSTEM_PLL_FACTOR_7_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]70 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]71 bool "7 : 1"
72
73config SYSTEM_PLL_FACTOR_8_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]74 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]75 bool "8 : 1"
76
77config SYSTEM_PLL_FACTOR_9_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]78 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]79 bool "9 : 1"
80
81config SYSTEM_PLL_FACTOR_10_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]82 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]83 bool "10 : 1"
84
85config SYSTEM_PLL_FACTOR_11_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]86 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]87 bool "11 : 1"
88
89config SYSTEM_PLL_FACTOR_12_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]90 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]91 bool "12 : 1"
92
93config SYSTEM_PLL_FACTOR_13_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]94 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]95 bool "13 : 1"
96
97config SYSTEM_PLL_FACTOR_14_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]98 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]99 bool "14 : 1"
100
101config SYSTEM_PLL_FACTOR_15_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]102 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]103 bool "15 : 1"
104
105config SYSTEM_PLL_FACTOR_16_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]106 depends on ARCH_MPV8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]107 bool "16 : 1"
108
109endchoice
110
111config CORE_PLL_BYPASS
112 bool "Core PLL bypassed"
113
114if !CORE_PLL_BYPASS
115
116choice
117 prompt "Core PLL Ratio"
118
119config CORE_PLL_RATIO_1_1
120 bool "1 : 1"
121
122config CORE_PLL_RATIO_15_1
123 bool "1.5 : 1"
124
125config CORE_PLL_RATIO_2_1
126 bool "2 : 1"
127
128config CORE_PLL_RATIO_25_1
129 bool "2.5 : 1"
130
131config CORE_PLL_RATIO_3_1
132 bool "3 : 1"
133
134endchoice
135
136choice
137 prompt "Core PLL VCO Divider"
138
139config CORE_PLL_VCO_DIVIDER_2
140 bool "2"
141
142config CORE_PLL_VCO_DIVIDER_4
143 bool "4"
144
145config CORE_PLL_VCO_DIVIDER_8
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]146 bool "8"
147
148endchoice
149
150endif
151
152if MPC83XX_QUICC_ENGINE
153
154choice
155 prompt "QUICC Engine PLL VCO Divider"
156
157config QUICC_VCO_DIVIDER_2
158 bool "2"
159
160config QUICC_VCO_DIVIDER_4
161 bool "4"
162
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]163endchoice
164
165choice
166 prompt "QUICC Engine PLL division factor"
167
168config QUICC_DIV_FACTOR_1
169 bool "1"
170
171config QUICC_DIV_FACTOR_2
172 bool "2"
173
174endchoice
175
176choice
177 prompt "QUICC Engine PLL multiplication factor"
178
179config QUICC_MULT_FACTOR_2
180 bool "2"
181
182config QUICC_MULT_FACTOR_3
183 bool "3"
184
185config QUICC_MULT_FACTOR_4
186 bool "4"
187
188config QUICC_MULT_FACTOR_5
189 bool "5"
190
191config QUICC_MULT_FACTOR_6
192 bool "6"
193
194config QUICC_MULT_FACTOR_7
195 bool "7"
196
197config QUICC_MULT_FACTOR_8
198 bool "8"
199
200config QUICC_MULT_FACTOR_9
201 depends on ARCH_MPC8360
202 bool "9"
203
204config QUICC_MULT_FACTOR_10
205 depends on ARCH_MPC8360
206 bool "10"
207
208config QUICC_MULT_FACTOR_11
209 depends on ARCH_MPC8360
210 bool "11"
211
212config QUICC_MULT_FACTOR_12
213 depends on ARCH_MPC8360
214 bool "12"
215
216config QUICC_MULT_FACTOR_13
217 depends on ARCH_MPC8360
218 bool "13"
219
220config QUICC_MULT_FACTOR_14
221 depends on ARCH_MPC8360
222 bool "14"
223
224config QUICC_MULT_FACTOR_15
225 depends on ARCH_MPC8360
226 bool "15"
227
228config QUICC_MULT_FACTOR_16
229 depends on ARCH_MPC8360
230 bool "16"
231
232config QUICC_MULT_FACTOR_17
233 depends on ARCH_MPC8360
234 bool "17"
235
236config QUICC_MULT_FACTOR_18
237 depends on ARCH_MPC8360
238 bool "18"
239
240config QUICC_MULT_FACTOR_19
241 depends on ARCH_MPC8360
242 bool "19"
243
244config QUICC_MULT_FACTOR_20
245 depends on ARCH_MPC8360
246 bool "20"
247
248config QUICC_MULT_FACTOR_21
249 depends on ARCH_MPC8360
250 bool "21"
251
252config QUICC_MULT_FACTOR_22
253 depends on ARCH_MPC8360
254 bool "22"
255
256config QUICC_MULT_FACTOR_23
257 depends on ARCH_MPC8360
258 bool "23"
259
260config QUICC_MULT_FACTOR_24
261 depends on ARCH_MPC8360
262 bool "24"
263
264config QUICC_MULT_FACTOR_25
265 depends on ARCH_MPC8360
266 bool "25"
267
268config QUICC_MULT_FACTOR_26
269 depends on ARCH_MPC8360
270 bool "26"
271
272config QUICC_MULT_FACTOR_27
273 depends on ARCH_MPC8360
274 bool "27"
275
276config QUICC_MULT_FACTOR_28
277 depends on ARCH_MPC8360
278 bool "28"
279
280config QUICC_MULT_FACTOR_29
281 depends on ARCH_MPC8360
282 bool "29"
283
284config QUICC_MULT_FACTOR_30
285 depends on ARCH_MPC8360
286 bool "30"
287
288config QUICC_MULT_FACTOR_31
289 depends on ARCH_MPC8360
290 bool "31"
291
292endchoice
293
294endif
295
296if MPC83XX_PCI_SUPPORT
297
298choice
299 prompt "PCI host mode"
300
301config PCI_HOST_MODE_DISABLE
302 bool "Disabled"
303
304config PCI_HOST_MODE_ENABLE
305 bool "Enabled"
306
307endchoice
308
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]309choice
310 prompt "PCI internal arbiter 1 mode"
311
312config PCI_INT_ARBITER1_DISABLE
313 bool "Disabled"
314
315config PCI_INT_ARBITER1_ENABLE
316 bool "Enabled"
317
318endchoice
319
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]320if ARCH_MPC8360
321
322choice
323 prompt "PCI clock output drive"
324
325config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
326 bool "Disabled"
327
328config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
329 bool "Enabled"
330
331endchoice
332
333endif
334
335endif
336
337choice
338 prompt "Core disable mode"
339
340config CORE_DISABLE_MODE_OFF
341 bool "Off"
342
343config CORE_DISABLE_MODE_ON
344 bool "On"
345
346endchoice
347
348choice
349 prompt "Boot Memory Space"
350
351config BOOT_MEMORY_SPACE_HIGH
352 bool "High"
353
354config BOOT_MEMORY_SPACE_LOW
355 bool "Low"
356
357endchoice
358
359choice
360 prompt "Boot Sequencer Configuration"
361
362config BOOT_SEQUENCER_DISABLED
363 bool "Disabled"
364
365config BOOT_SEQUENCER_NORMAL_I2C
366 bool "Normal I2C"
367
368config BOOT_SEQUENCER_EXTENDED_I2C
369 bool "Extended I2C"
370
371endchoice
372
373choice
374 prompt "Software Watchdog"
375
376config SOFTWARE_WATCHDOG_DISABLED
377 bool "Disabled"
378
379config SOFTWARE_WATCHDOG_ENABLED
380 bool "Enabled"
381
382endchoice
383
384choice
385 prompt "Boot ROM interface location"
386
387config BOOT_ROM_INTERFACE_DDR_SDRAM
388 bool "DDR_SDRAM"
389
390config BOOT_ROM_INTERFACE_PCI1
391 depends on MPC83XX_PCI_SUPPORT
392 bool "PCI1"
393
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]394config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
395 depends on ARCH_MPC837X
396 bool "PCI2"
397
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]398config BOOT_ROM_INTERFACE_GPCM_8BIT
399 bool "Local bus GPCM - 8-bit ROM"
400
401config BOOT_ROM_INTERFACE_GPCM_16BIT
402 bool "Local bus GPCM - 16-bit ROM"
403
404config BOOT_ROM_INTERFACE_GPCM_32BIT
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]405 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]406 bool "Local bus GPCM - 32-bit ROM"
407
408config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]409 depends on !ARCH_MPC832X && !ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]410 bool "Local bus NAND Flash- 8-bit small page ROM"
411
412config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]413 depends on !ARCH_MPC832X && !ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]414 bool "Local bus NAND Flash- 8-bit large page ROM"
415
416endchoice
417
418if MPC83XX_TSEC1_SUPPORT
419
420choice
421 prompt "TSEC1 mode"
422
423config TSEC1_MODE_MII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]424 bool "MII"
425
426config TSEC1_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]427 depends on ARCH_MPC831X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]428 bool "RMII"
429
430config TSEC1_MODE_RGMII
431 bool "RGMII"
432
433config TSEC1_MODE_RTBI
434 depends on ARCH_MPC831X || ARCH_MPC837X
435 bool "RTBI"
436
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]437config TSEC1_MODE_SGMII
438 depends on ARCH_MPC831X || ARCH_MPC837X
439 bool "SGMII"
440
441endchoice
442
443endif
444
445if MPC83XX_TSEC2_SUPPORT
446
447choice
448 prompt "TSEC2 mode"
449
450config TSEC2_MODE_MII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]451 bool "MII"
452
453config TSEC2_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]454 depends on ARCH_MPC831X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]455 bool "RMII"
456
457config TSEC2_MODE_RGMII
458 bool "RGMII"
459
460config TSEC2_MODE_RTBI
461 depends on ARCH_MPC831X || ARCH_MPC837X
462 bool "RTBI"
463
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]464config TSEC2_MODE_SGMII
465 depends on ARCH_MPC831X || ARCH_MPC837X
466 bool "SGMII"
467
468endchoice
469
470endif
471
472choice
473 prompt "True litle-endian mode"
474
475config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
476 bool "Big-endian"
477
478config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
479 bool "Little-endian"
480
481endchoice
482
483if ARCH_MPC8360
484
485choice
486 prompt "Secondary DDR IO"
487
488config SECONDARY_DDR_IO_DISABLE
489 bool "Disable"
490
491config SECONDARY_DDR_IO_ENABLE
492 bool "Enable"
493
494endchoice
495
496endif
497
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]498if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]499
500choice
501 prompt "LALE timing"
502
503config LALE_TIMING_NORMAL
504 bool "Normal"
505
506config LALE_TIMING_EARLIER
507 bool "Earlier"
508
509endchoice
510
511endif
512
513if MPC83XX_LDP_PIN
514
515choice
516 prompt "LDP pin mux state"
517
518config LDP_PIN_MUX_STATE_1
519 bool "Inital value 1"
520
521config LDP_PIN_MUX_STATE_0
522 bool "Inital value 0"
523
524endchoice
525
526endif
527
528endmenu
529
530config LBMC_CLOCK_MODE
531 int
532 default 0 if LBMC_CLOCK_MODE_1_1
533 default 1 if LBMC_CLOCK_MODE_1_2
534
535config DDR_MC_CLOCK_MODE
536 int
537 default 1 if DDR_MC_CLOCK_MODE_1_2
538 default 0 if DDR_MC_CLOCK_MODE_1_1
539
540config SYSTEM_PLL_VCO_DIV
541 int
Christophe Leroy60326812023-03-02 10:48:58 +0100[diff] [blame]542 default 2 if ARCH_MPC8313 || ARCH_MPC832X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]543 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
544 default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
545 default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
546 default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
547 default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
548 default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
549 default 3 if SYSTEM_PLL_VCO_DIV_1
550
551config SYSTEM_PLL_FACTOR
552 int
553 default 2 if SYSTEM_PLL_FACTOR_2_1
554 default 3 if SYSTEM_PLL_FACTOR_3_1
555 default 4 if SYSTEM_PLL_FACTOR_4_1
556 default 5 if SYSTEM_PLL_FACTOR_5_1
557 default 6 if SYSTEM_PLL_FACTOR_6_1
558 default 7 if SYSTEM_PLL_FACTOR_7_1
559 default 8 if SYSTEM_PLL_FACTOR_8_1
560 default 9 if SYSTEM_PLL_FACTOR_9_1
561 default 10 if SYSTEM_PLL_FACTOR_10_1
562 default 11 if SYSTEM_PLL_FACTOR_11_1
563 default 12 if SYSTEM_PLL_FACTOR_12_1
564 default 13 if SYSTEM_PLL_FACTOR_13_1
565 default 14 if SYSTEM_PLL_FACTOR_14_1
566 default 15 if SYSTEM_PLL_FACTOR_15_1
567 default 0 if SYSTEM_PLL_FACTOR_16_1
568
569config CORE_PLL_RATIO
570 hex
571 default 0x0 if CORE_PLL_BYPASS
572 default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
573 default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
574 default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
575 default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
576 default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
577 default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
578 default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
579 default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
580 default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
581 default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
582 default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
583 default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
584 default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
585 default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
586 default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
587
588config CORE_DISABLE_MODE
589 int
590 default 0 if CORE_DISABLE_MODE_OFF
591 default 1 if CORE_DISABLE_MODE_ON
592
593config BOOT_MEMORY_SPACE
594 int
595 default 0 if BOOT_MEMORY_SPACE_LOW
596 default 1 if BOOT_MEMORY_SPACE_HIGH
597
598config BOOT_SEQUENCER
599 int
600 default 0 if BOOT_SEQUENCER_DISABLED
601 default 1 if BOOT_SEQUENCER_NORMAL_I2C
602 default 2 if BOOT_SEQUENCER_EXTENDED_I2C
603
604config SOFTWARE_WATCHDOG
605 int
606 default 0 if SOFTWARE_WATCHDOG_DISABLED
607 default 1 if SOFTWARE_WATCHDOG_ENABLED
608
609config BOOT_ROM_INTERFACE
610 hex
611 default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
612 default 0x4 if BOOT_ROM_INTERFACE_PCI1
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]613 default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
614 default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
615 default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
616 default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
617 default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
618 default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
619
620config TSEC1_MODE
621 hex
622 default 0x0 if !MPC83XX_TSEC1_SUPPORT
623 default 0x0 if TSEC1_MODE_MII
624 default 0x1 if TSEC1_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]625 default 0x3 if TSEC1_MODE_RGMII
626 default 0x5 if TSEC1_MODE_RTBI
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]627 default 0x6 if TSEC1_MODE_SGMII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]628
629config TSEC2_MODE
630 hex
631 default 0x0 if !MPC83XX_TSEC2_SUPPORT
632 default 0x0 if TSEC2_MODE_MII
633 default 0x1 if TSEC2_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]634 default 0x3 if TSEC2_MODE_RGMII
635 default 0x5 if TSEC2_MODE_RTBI
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]636 default 0x6 if TSEC2_MODE_SGMII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]637
638config SECONDARY_DDR_IO
639 int
640 default 0 if !ARCH_MPC8360
641 default 0 if SECONDARY_DDR_IO_DISABLE
642 default 1 if SECONDARY_DDR_IO_ENABLE
643
644config TRUE_LITTLE_ENDIAN
645 int
646 default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
647 default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
648
649config LALE_TIMING
650 int
651 default 0 if ARCH_MPC830X || ARCH_MPC837X
652 default 0 if LALE_TIMING_NORMAL
653 default 1 if LALE_TIMING_EARLIER
654
655config LDP_PIN_MUX_STATE
656 int
657 default 0 if !MPC83XX_LDP_PIN
658 default 0 if LDP_PIN_MUX_STATE_1
659 default 1 if LDP_PIN_MUX_STATE_0
660
661config QUICC_VCO_DIVIDER
662 int
663 default 0 if !MPC83XX_QUICC_ENGINE
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]664 default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
665 default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]666
667config QUICC_DIV_FACTOR
668 int
669 default 0 if !MPC83XX_QUICC_ENGINE
670 default 0 if QUICC_DIV_FACTOR_1
671 default 1 if QUICC_DIV_FACTOR_2
672
673config QUICC_MULT_FACTOR
674 int
675 default 0 if !MPC83XX_QUICC_ENGINE
676 default 2 if QUICC_MULT_FACTOR_2
677 default 3 if QUICC_MULT_FACTOR_3
678 default 4 if QUICC_MULT_FACTOR_4
679 default 5 if QUICC_MULT_FACTOR_5
680 default 6 if QUICC_MULT_FACTOR_6
681 default 7 if QUICC_MULT_FACTOR_7
682 default 8 if QUICC_MULT_FACTOR_8
683 default 9 if QUICC_MULT_FACTOR_9
684 default 10 if QUICC_MULT_FACTOR_10
685 default 11 if QUICC_MULT_FACTOR_11
686 default 12 if QUICC_MULT_FACTOR_12
687 default 13 if QUICC_MULT_FACTOR_13
688 default 14 if QUICC_MULT_FACTOR_14
689 default 15 if QUICC_MULT_FACTOR_15
690 default 16 if QUICC_MULT_FACTOR_16
691 default 17 if QUICC_MULT_FACTOR_17
692 default 18 if QUICC_MULT_FACTOR_18
693 default 19 if QUICC_MULT_FACTOR_19
694 default 20 if QUICC_MULT_FACTOR_20
695 default 21 if QUICC_MULT_FACTOR_21
696 default 22 if QUICC_MULT_FACTOR_22
697 default 23 if QUICC_MULT_FACTOR_23
698 default 24 if QUICC_MULT_FACTOR_24
699 default 25 if QUICC_MULT_FACTOR_25
700 default 26 if QUICC_MULT_FACTOR_26
701 default 27 if QUICC_MULT_FACTOR_27
702 default 28 if QUICC_MULT_FACTOR_28
703 default 29 if QUICC_MULT_FACTOR_29
704 default 30 if QUICC_MULT_FACTOR_30
705 default 31 if QUICC_MULT_FACTOR_31
706
707config PCI_HOST_MODE
708 int
709 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
710 default 0 if PCI_HOST_MODE_DISABLE
711 default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
712
713config PCI_64BIT_MODE
714 int
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]715 default 0
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]716
717config PCI_INT_ARBITER1
718 int
719 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
720 default 0 if PCI_INT_ARBITER1_DISABLE
721 default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
722
723config PCI_INT_ARBITER2
724 int
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame]725 default 0
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]726
727config PCI_CLOCK_OUTPUT_DRIVE
728 int
729 default 0 if !ARCH_MPC8360
730 default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
731 default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE