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git01.mediatek.com / filogic / uboot / 291ab5604c2173b0638cc4446be5ba19e02027c3 / . / arch / powerpc / cpu / mpc83xx / hrcw / Kconfig
blob: 71fa73801ae19c86c5816b2b4965274574963cf7 [file] [log] [blame]
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]1menu "Reset Configuration Word"
2
3choice
4 prompt "Local bus memory controller clock mode"
5
6config LBMC_CLOCK_MODE_1_1
7 bool "1 : 1"
8
9config LBMC_CLOCK_MODE_1_2
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]10 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]11 bool "1 : 2"
12
13endchoice
14
15choice
16 prompt "DDR SDRAM memory controller clock mode"
17
18config DDR_MC_CLOCK_MODE_1_2
19 bool "1 : 2"
20
21config DDR_MC_CLOCK_MODE_1_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]22 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]23 bool "1 : 1"
24
25endchoice
26
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]27if !ARCH_MPC8313 && !ARCH_MPC832X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]28
29choice
30 prompt "System PLL VCO division"
31
32config SYSTEM_PLL_VCO_DIV_1
33 depends on !ARCH_MPC837X
34 bool "1"
35
36config SYSTEM_PLL_VCO_DIV_2
37 bool "2"
38
39config SYSTEM_PLL_VCO_DIV_4
40 depends on !ARCH_MPC831X
41 bool "4"
42
43config SYSTEM_PLL_VCO_DIV_8
44 depends on !ARCH_MPC831X
45 bool "8"
46
47endchoice
48
49endif
50
51choice
52 prompt "System PLL multiplication factor"
53
54config SYSTEM_PLL_FACTOR_2_1
55 bool "2 : 1"
56
57config SYSTEM_PLL_FACTOR_3_1
58 bool "3 : 1"
59
60config SYSTEM_PLL_FACTOR_4_1
61 bool "4 : 1"
62
63config SYSTEM_PLL_FACTOR_5_1
64 bool "5 : 1"
65
66config SYSTEM_PLL_FACTOR_6_1
67 bool "6 : 1"
68
69config SYSTEM_PLL_FACTOR_7_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]70 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]71 bool "7 : 1"
72
73config SYSTEM_PLL_FACTOR_8_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]74 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]75 bool "8 : 1"
76
77config SYSTEM_PLL_FACTOR_9_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]78 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]79 bool "9 : 1"
80
81config SYSTEM_PLL_FACTOR_10_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]82 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]83 bool "10 : 1"
84
85config SYSTEM_PLL_FACTOR_11_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]86 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]87 bool "11 : 1"
88
89config SYSTEM_PLL_FACTOR_12_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]90 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]91 bool "12 : 1"
92
93config SYSTEM_PLL_FACTOR_13_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]94 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]95 bool "13 : 1"
96
97config SYSTEM_PLL_FACTOR_14_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]98 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]99 bool "14 : 1"
100
101config SYSTEM_PLL_FACTOR_15_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]102 depends on ARCH_MPV8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]103 bool "15 : 1"
104
105config SYSTEM_PLL_FACTOR_16_1
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]106 depends on ARCH_MPV8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]107 bool "16 : 1"
108
109endchoice
110
111config CORE_PLL_BYPASS
112 bool "Core PLL bypassed"
113
114if !CORE_PLL_BYPASS
115
116choice
117 prompt "Core PLL Ratio"
118
119config CORE_PLL_RATIO_1_1
120 bool "1 : 1"
121
122config CORE_PLL_RATIO_15_1
123 bool "1.5 : 1"
124
125config CORE_PLL_RATIO_2_1
126 bool "2 : 1"
127
128config CORE_PLL_RATIO_25_1
129 bool "2.5 : 1"
130
131config CORE_PLL_RATIO_3_1
132 bool "3 : 1"
133
134endchoice
135
136choice
137 prompt "Core PLL VCO Divider"
138
139config CORE_PLL_VCO_DIVIDER_2
140 bool "2"
141
142config CORE_PLL_VCO_DIVIDER_4
143 bool "4"
144
145config CORE_PLL_VCO_DIVIDER_8
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]146 bool "8"
147
148endchoice
149
150endif
151
152if MPC83XX_QUICC_ENGINE
153
154choice
155 prompt "QUICC Engine PLL VCO Divider"
156
157config QUICC_VCO_DIVIDER_2
158 bool "2"
159
160config QUICC_VCO_DIVIDER_4
161 bool "4"
162
163config QUICC_VCO_DIVIDER_8
164 depends on ARCH_MPC8309
165 bool "8"
166
167endchoice
168
169choice
170 prompt "QUICC Engine PLL division factor"
171
172config QUICC_DIV_FACTOR_1
173 bool "1"
174
175config QUICC_DIV_FACTOR_2
176 bool "2"
177
178endchoice
179
180choice
181 prompt "QUICC Engine PLL multiplication factor"
182
183config QUICC_MULT_FACTOR_2
184 bool "2"
185
186config QUICC_MULT_FACTOR_3
187 bool "3"
188
189config QUICC_MULT_FACTOR_4
190 bool "4"
191
192config QUICC_MULT_FACTOR_5
193 bool "5"
194
195config QUICC_MULT_FACTOR_6
196 bool "6"
197
198config QUICC_MULT_FACTOR_7
199 bool "7"
200
201config QUICC_MULT_FACTOR_8
202 bool "8"
203
204config QUICC_MULT_FACTOR_9
205 depends on ARCH_MPC8360
206 bool "9"
207
208config QUICC_MULT_FACTOR_10
209 depends on ARCH_MPC8360
210 bool "10"
211
212config QUICC_MULT_FACTOR_11
213 depends on ARCH_MPC8360
214 bool "11"
215
216config QUICC_MULT_FACTOR_12
217 depends on ARCH_MPC8360
218 bool "12"
219
220config QUICC_MULT_FACTOR_13
221 depends on ARCH_MPC8360
222 bool "13"
223
224config QUICC_MULT_FACTOR_14
225 depends on ARCH_MPC8360
226 bool "14"
227
228config QUICC_MULT_FACTOR_15
229 depends on ARCH_MPC8360
230 bool "15"
231
232config QUICC_MULT_FACTOR_16
233 depends on ARCH_MPC8360
234 bool "16"
235
236config QUICC_MULT_FACTOR_17
237 depends on ARCH_MPC8360
238 bool "17"
239
240config QUICC_MULT_FACTOR_18
241 depends on ARCH_MPC8360
242 bool "18"
243
244config QUICC_MULT_FACTOR_19
245 depends on ARCH_MPC8360
246 bool "19"
247
248config QUICC_MULT_FACTOR_20
249 depends on ARCH_MPC8360
250 bool "20"
251
252config QUICC_MULT_FACTOR_21
253 depends on ARCH_MPC8360
254 bool "21"
255
256config QUICC_MULT_FACTOR_22
257 depends on ARCH_MPC8360
258 bool "22"
259
260config QUICC_MULT_FACTOR_23
261 depends on ARCH_MPC8360
262 bool "23"
263
264config QUICC_MULT_FACTOR_24
265 depends on ARCH_MPC8360
266 bool "24"
267
268config QUICC_MULT_FACTOR_25
269 depends on ARCH_MPC8360
270 bool "25"
271
272config QUICC_MULT_FACTOR_26
273 depends on ARCH_MPC8360
274 bool "26"
275
276config QUICC_MULT_FACTOR_27
277 depends on ARCH_MPC8360
278 bool "27"
279
280config QUICC_MULT_FACTOR_28
281 depends on ARCH_MPC8360
282 bool "28"
283
284config QUICC_MULT_FACTOR_29
285 depends on ARCH_MPC8360
286 bool "29"
287
288config QUICC_MULT_FACTOR_30
289 depends on ARCH_MPC8360
290 bool "30"
291
292config QUICC_MULT_FACTOR_31
293 depends on ARCH_MPC8360
294 bool "31"
295
296endchoice
297
298endif
299
300if MPC83XX_PCI_SUPPORT
301
302choice
303 prompt "PCI host mode"
304
305config PCI_HOST_MODE_DISABLE
306 bool "Disabled"
307
308config PCI_HOST_MODE_ENABLE
309 bool "Enabled"
310
311endchoice
312
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]313choice
314 prompt "PCI internal arbiter 1 mode"
315
316config PCI_INT_ARBITER1_DISABLE
317 bool "Disabled"
318
319config PCI_INT_ARBITER1_ENABLE
320 bool "Enabled"
321
322endchoice
323
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]324if ARCH_MPC8360
325
326choice
327 prompt "PCI clock output drive"
328
329config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
330 bool "Disabled"
331
332config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
333 bool "Enabled"
334
335endchoice
336
337endif
338
339endif
340
341choice
342 prompt "Core disable mode"
343
344config CORE_DISABLE_MODE_OFF
345 bool "Off"
346
347config CORE_DISABLE_MODE_ON
348 bool "On"
349
350endchoice
351
352choice
353 prompt "Boot Memory Space"
354
355config BOOT_MEMORY_SPACE_HIGH
356 bool "High"
357
358config BOOT_MEMORY_SPACE_LOW
359 bool "Low"
360
361endchoice
362
363choice
364 prompt "Boot Sequencer Configuration"
365
366config BOOT_SEQUENCER_DISABLED
367 bool "Disabled"
368
369config BOOT_SEQUENCER_NORMAL_I2C
370 bool "Normal I2C"
371
372config BOOT_SEQUENCER_EXTENDED_I2C
373 bool "Extended I2C"
374
375endchoice
376
377choice
378 prompt "Software Watchdog"
379
380config SOFTWARE_WATCHDOG_DISABLED
381 bool "Disabled"
382
383config SOFTWARE_WATCHDOG_ENABLED
384 bool "Enabled"
385
386endchoice
387
388choice
389 prompt "Boot ROM interface location"
390
391config BOOT_ROM_INTERFACE_DDR_SDRAM
392 bool "DDR_SDRAM"
393
394config BOOT_ROM_INTERFACE_PCI1
395 depends on MPC83XX_PCI_SUPPORT
396 bool "PCI1"
397
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]398config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
399 depends on ARCH_MPC837X
400 bool "PCI2"
401
402config BOOT_ROM_INTERFACE_ESDHC
403 depends on ARCH_MPC8309
404 bool "eSDHC"
405
406config BOOT_ROM_INTERFACE_SPI
407 depends on ARCH_MPC8309
408 bool "SPI"
409
410config BOOT_ROM_INTERFACE_GPCM_8BIT
411 bool "Local bus GPCM - 8-bit ROM"
412
413config BOOT_ROM_INTERFACE_GPCM_16BIT
414 bool "Local bus GPCM - 16-bit ROM"
415
416config BOOT_ROM_INTERFACE_GPCM_32BIT
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]417 depends on ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]418 bool "Local bus GPCM - 32-bit ROM"
419
420config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]421 depends on !ARCH_MPC832X && !ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]422 bool "Local bus NAND Flash- 8-bit small page ROM"
423
424config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]425 depends on !ARCH_MPC832X && !ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]426 bool "Local bus NAND Flash- 8-bit large page ROM"
427
428endchoice
429
430if MPC83XX_TSEC1_SUPPORT
431
432choice
433 prompt "TSEC1 mode"
434
435config TSEC1_MODE_MII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]436 bool "MII"
437
438config TSEC1_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]439 depends on ARCH_MPC831X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]440 bool "RMII"
441
442config TSEC1_MODE_RGMII
443 bool "RGMII"
444
445config TSEC1_MODE_RTBI
446 depends on ARCH_MPC831X || ARCH_MPC837X
447 bool "RTBI"
448
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]449config TSEC1_MODE_SGMII
450 depends on ARCH_MPC831X || ARCH_MPC837X
451 bool "SGMII"
452
453endchoice
454
455endif
456
457if MPC83XX_TSEC2_SUPPORT
458
459choice
460 prompt "TSEC2 mode"
461
462config TSEC2_MODE_MII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]463 bool "MII"
464
465config TSEC2_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]466 depends on ARCH_MPC831X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]467 bool "RMII"
468
469config TSEC2_MODE_RGMII
470 bool "RGMII"
471
472config TSEC2_MODE_RTBI
473 depends on ARCH_MPC831X || ARCH_MPC837X
474 bool "RTBI"
475
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]476config TSEC2_MODE_SGMII
477 depends on ARCH_MPC831X || ARCH_MPC837X
478 bool "SGMII"
479
480endchoice
481
482endif
483
484choice
485 prompt "True litle-endian mode"
486
487config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
488 bool "Big-endian"
489
490config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
491 bool "Little-endian"
492
493endchoice
494
495if ARCH_MPC8360
496
497choice
498 prompt "Secondary DDR IO"
499
500config SECONDARY_DDR_IO_DISABLE
501 bool "Disable"
502
503config SECONDARY_DDR_IO_ENABLE
504 bool "Enable"
505
506endchoice
507
508endif
509
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]510if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]511
512choice
513 prompt "LALE timing"
514
515config LALE_TIMING_NORMAL
516 bool "Normal"
517
518config LALE_TIMING_EARLIER
519 bool "Earlier"
520
521endchoice
522
523endif
524
525if MPC83XX_LDP_PIN
526
527choice
528 prompt "LDP pin mux state"
529
530config LDP_PIN_MUX_STATE_1
531 bool "Inital value 1"
532
533config LDP_PIN_MUX_STATE_0
534 bool "Inital value 0"
535
536endchoice
537
538endif
539
540endmenu
541
542config LBMC_CLOCK_MODE
543 int
544 default 0 if LBMC_CLOCK_MODE_1_1
545 default 1 if LBMC_CLOCK_MODE_1_2
546
547config DDR_MC_CLOCK_MODE
548 int
549 default 1 if DDR_MC_CLOCK_MODE_1_2
550 default 0 if DDR_MC_CLOCK_MODE_1_1
551
552config SYSTEM_PLL_VCO_DIV
553 int
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]554 default 0 if ARCH_MPC832X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]555 default 2 if ARCH_MPC8313
556 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
557 default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
558 default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
559 default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
560 default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
561 default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
562 default 3 if SYSTEM_PLL_VCO_DIV_1
563
564config SYSTEM_PLL_FACTOR
565 int
566 default 2 if SYSTEM_PLL_FACTOR_2_1
567 default 3 if SYSTEM_PLL_FACTOR_3_1
568 default 4 if SYSTEM_PLL_FACTOR_4_1
569 default 5 if SYSTEM_PLL_FACTOR_5_1
570 default 6 if SYSTEM_PLL_FACTOR_6_1
571 default 7 if SYSTEM_PLL_FACTOR_7_1
572 default 8 if SYSTEM_PLL_FACTOR_8_1
573 default 9 if SYSTEM_PLL_FACTOR_9_1
574 default 10 if SYSTEM_PLL_FACTOR_10_1
575 default 11 if SYSTEM_PLL_FACTOR_11_1
576 default 12 if SYSTEM_PLL_FACTOR_12_1
577 default 13 if SYSTEM_PLL_FACTOR_13_1
578 default 14 if SYSTEM_PLL_FACTOR_14_1
579 default 15 if SYSTEM_PLL_FACTOR_15_1
580 default 0 if SYSTEM_PLL_FACTOR_16_1
581
582config CORE_PLL_RATIO
583 hex
584 default 0x0 if CORE_PLL_BYPASS
585 default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
586 default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
587 default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
588 default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
589 default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
590 default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
591 default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
592 default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
593 default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
594 default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
595 default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
596 default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
597 default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
598 default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
599 default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
600
601config CORE_DISABLE_MODE
602 int
603 default 0 if CORE_DISABLE_MODE_OFF
604 default 1 if CORE_DISABLE_MODE_ON
605
606config BOOT_MEMORY_SPACE
607 int
608 default 0 if BOOT_MEMORY_SPACE_LOW
609 default 1 if BOOT_MEMORY_SPACE_HIGH
610
611config BOOT_SEQUENCER
612 int
613 default 0 if BOOT_SEQUENCER_DISABLED
614 default 1 if BOOT_SEQUENCER_NORMAL_I2C
615 default 2 if BOOT_SEQUENCER_EXTENDED_I2C
616
617config SOFTWARE_WATCHDOG
618 int
619 default 0 if SOFTWARE_WATCHDOG_DISABLED
620 default 1 if SOFTWARE_WATCHDOG_ENABLED
621
622config BOOT_ROM_INTERFACE
623 hex
624 default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
625 default 0x4 if BOOT_ROM_INTERFACE_PCI1
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]626 default 0x8 if BOOT_ROM_INTERFACE_ESDHC
627 default 0xc if BOOT_ROM_INTERFACE_SPI
628 default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
629 default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
630 default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
631 default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
632 default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
633 default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
634
635config TSEC1_MODE
636 hex
637 default 0x0 if !MPC83XX_TSEC1_SUPPORT
638 default 0x0 if TSEC1_MODE_MII
639 default 0x1 if TSEC1_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]640 default 0x3 if TSEC1_MODE_RGMII
641 default 0x5 if TSEC1_MODE_RTBI
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]642 default 0x6 if TSEC1_MODE_SGMII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]643
644config TSEC2_MODE
645 hex
646 default 0x0 if !MPC83XX_TSEC2_SUPPORT
647 default 0x0 if TSEC2_MODE_MII
648 default 0x1 if TSEC2_MODE_RMII
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]649 default 0x3 if TSEC2_MODE_RGMII
650 default 0x5 if TSEC2_MODE_RTBI
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]651 default 0x6 if TSEC2_MODE_SGMII
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]652
653config SECONDARY_DDR_IO
654 int
655 default 0 if !ARCH_MPC8360
656 default 0 if SECONDARY_DDR_IO_DISABLE
657 default 1 if SECONDARY_DDR_IO_ENABLE
658
659config TRUE_LITTLE_ENDIAN
660 int
661 default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
662 default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
663
664config LALE_TIMING
665 int
666 default 0 if ARCH_MPC830X || ARCH_MPC837X
667 default 0 if LALE_TIMING_NORMAL
668 default 1 if LALE_TIMING_EARLIER
669
670config LDP_PIN_MUX_STATE
671 int
672 default 0 if !MPC83XX_LDP_PIN
673 default 0 if LDP_PIN_MUX_STATE_1
674 default 1 if LDP_PIN_MUX_STATE_0
675
676config QUICC_VCO_DIVIDER
677 int
678 default 0 if !MPC83XX_QUICC_ENGINE
679 default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
680 default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
681 default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
682 default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
683 default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
684 default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
685
686config QUICC_DIV_FACTOR
687 int
688 default 0 if !MPC83XX_QUICC_ENGINE
689 default 0 if QUICC_DIV_FACTOR_1
690 default 1 if QUICC_DIV_FACTOR_2
691
692config QUICC_MULT_FACTOR
693 int
694 default 0 if !MPC83XX_QUICC_ENGINE
695 default 2 if QUICC_MULT_FACTOR_2
696 default 3 if QUICC_MULT_FACTOR_3
697 default 4 if QUICC_MULT_FACTOR_4
698 default 5 if QUICC_MULT_FACTOR_5
699 default 6 if QUICC_MULT_FACTOR_6
700 default 7 if QUICC_MULT_FACTOR_7
701 default 8 if QUICC_MULT_FACTOR_8
702 default 9 if QUICC_MULT_FACTOR_9
703 default 10 if QUICC_MULT_FACTOR_10
704 default 11 if QUICC_MULT_FACTOR_11
705 default 12 if QUICC_MULT_FACTOR_12
706 default 13 if QUICC_MULT_FACTOR_13
707 default 14 if QUICC_MULT_FACTOR_14
708 default 15 if QUICC_MULT_FACTOR_15
709 default 16 if QUICC_MULT_FACTOR_16
710 default 17 if QUICC_MULT_FACTOR_17
711 default 18 if QUICC_MULT_FACTOR_18
712 default 19 if QUICC_MULT_FACTOR_19
713 default 20 if QUICC_MULT_FACTOR_20
714 default 21 if QUICC_MULT_FACTOR_21
715 default 22 if QUICC_MULT_FACTOR_22
716 default 23 if QUICC_MULT_FACTOR_23
717 default 24 if QUICC_MULT_FACTOR_24
718 default 25 if QUICC_MULT_FACTOR_25
719 default 26 if QUICC_MULT_FACTOR_26
720 default 27 if QUICC_MULT_FACTOR_27
721 default 28 if QUICC_MULT_FACTOR_28
722 default 29 if QUICC_MULT_FACTOR_29
723 default 30 if QUICC_MULT_FACTOR_30
724 default 31 if QUICC_MULT_FACTOR_31
725
726config PCI_HOST_MODE
727 int
728 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
729 default 0 if PCI_HOST_MODE_DISABLE
730 default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
731
732config PCI_64BIT_MODE
733 int
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]734 default 0
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]735
736config PCI_INT_ARBITER1
737 int
738 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
739 default 0 if PCI_INT_ARBITER1_DISABLE
740 default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
741
742config PCI_INT_ARBITER2
743 int
Tom Rini291ab562021-09-09 07:54:53 -0400[diff] [blame^]744 default 0
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]745
746config PCI_CLOCK_OUTPUT_DRIVE
747 int
748 default 0 if !ARCH_MPC8360
749 default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
750 default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE