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git01.mediatek.com / filogic / uboot / 7578319e36b7e002eac6bfc65b09546663aa0816 / . / arch / powerpc / cpu / mpc83xx / hrcw / Kconfig
blob: 75ec9c9a3464ba13dcb1a128c23bdbf654bebd5e [file] [log] [blame]
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]1menu "Reset Configuration Word"
2
3choice
4 prompt "Local bus memory controller clock mode"
5
6config LBMC_CLOCK_MODE_1_1
7 bool "1 : 1"
8
9config LBMC_CLOCK_MODE_1_2
10 depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
11 bool "1 : 2"
12
13endchoice
14
15choice
16 prompt "DDR SDRAM memory controller clock mode"
17
18config DDR_MC_CLOCK_MODE_1_2
19 bool "1 : 2"
20
21config DDR_MC_CLOCK_MODE_1_1
Tom Rinid9e6ef52021-05-14 21:34:27 -0400[diff] [blame]22 depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]23 bool "1 : 1"
24
25endchoice
26
27if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
28
29choice
30 prompt "System PLL VCO division"
31
32config SYSTEM_PLL_VCO_DIV_1
33 depends on !ARCH_MPC837X
34 bool "1"
35
36config SYSTEM_PLL_VCO_DIV_2
37 bool "2"
38
39config SYSTEM_PLL_VCO_DIV_4
40 depends on !ARCH_MPC831X
41 bool "4"
42
43config SYSTEM_PLL_VCO_DIV_8
44 depends on !ARCH_MPC831X
45 bool "8"
46
47endchoice
48
49endif
50
51choice
52 prompt "System PLL multiplication factor"
53
54config SYSTEM_PLL_FACTOR_2_1
55 bool "2 : 1"
56
57config SYSTEM_PLL_FACTOR_3_1
58 bool "3 : 1"
59
60config SYSTEM_PLL_FACTOR_4_1
61 bool "4 : 1"
62
63config SYSTEM_PLL_FACTOR_5_1
64 bool "5 : 1"
65
66config SYSTEM_PLL_FACTOR_6_1
67 bool "6 : 1"
68
69config SYSTEM_PLL_FACTOR_7_1
70 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
71 bool "7 : 1"
72
73config SYSTEM_PLL_FACTOR_8_1
74 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
75 bool "8 : 1"
76
77config SYSTEM_PLL_FACTOR_9_1
78 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
79 bool "9 : 1"
80
81config SYSTEM_PLL_FACTOR_10_1
82 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
83 bool "10 : 1"
84
85config SYSTEM_PLL_FACTOR_11_1
86 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
87 bool "11 : 1"
88
89config SYSTEM_PLL_FACTOR_12_1
90 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
91 bool "12 : 1"
92
93config SYSTEM_PLL_FACTOR_13_1
94 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
95 bool "13 : 1"
96
97config SYSTEM_PLL_FACTOR_14_1
98 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
99 bool "14 : 1"
100
101config SYSTEM_PLL_FACTOR_15_1
102 depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
103 bool "15 : 1"
104
105config SYSTEM_PLL_FACTOR_16_1
106 depends on ARCH_MPC8349 || ARCH_MPV8360
107 bool "16 : 1"
108
109endchoice
110
111config CORE_PLL_BYPASS
112 bool "Core PLL bypassed"
113
114if !CORE_PLL_BYPASS
115
116choice
117 prompt "Core PLL Ratio"
118
119config CORE_PLL_RATIO_1_1
120 bool "1 : 1"
121
122config CORE_PLL_RATIO_15_1
123 bool "1.5 : 1"
124
125config CORE_PLL_RATIO_2_1
126 bool "2 : 1"
127
128config CORE_PLL_RATIO_25_1
129 bool "2.5 : 1"
130
131config CORE_PLL_RATIO_3_1
132 bool "3 : 1"
133
134endchoice
135
136choice
137 prompt "Core PLL VCO Divider"
138
139config CORE_PLL_VCO_DIVIDER_2
140 bool "2"
141
142config CORE_PLL_VCO_DIVIDER_4
143 bool "4"
144
145config CORE_PLL_VCO_DIVIDER_8
Mario Six94867102019-01-21 09:17:54 +0100[diff] [blame]146 bool "8"
147
148endchoice
149
150endif
151
152if MPC83XX_QUICC_ENGINE
153
154choice
155 prompt "QUICC Engine PLL VCO Divider"
156
157config QUICC_VCO_DIVIDER_2
158 bool "2"
159
160config QUICC_VCO_DIVIDER_4
161 bool "4"
162
163config QUICC_VCO_DIVIDER_8
164 depends on ARCH_MPC8309
165 bool "8"
166
167endchoice
168
169choice
170 prompt "QUICC Engine PLL division factor"
171
172config QUICC_DIV_FACTOR_1
173 bool "1"
174
175config QUICC_DIV_FACTOR_2
176 bool "2"
177
178endchoice
179
180choice
181 prompt "QUICC Engine PLL multiplication factor"
182
183config QUICC_MULT_FACTOR_2
184 bool "2"
185
186config QUICC_MULT_FACTOR_3
187 bool "3"
188
189config QUICC_MULT_FACTOR_4
190 bool "4"
191
192config QUICC_MULT_FACTOR_5
193 bool "5"
194
195config QUICC_MULT_FACTOR_6
196 bool "6"
197
198config QUICC_MULT_FACTOR_7
199 bool "7"
200
201config QUICC_MULT_FACTOR_8
202 bool "8"
203
204config QUICC_MULT_FACTOR_9
205 depends on ARCH_MPC8360
206 bool "9"
207
208config QUICC_MULT_FACTOR_10
209 depends on ARCH_MPC8360
210 bool "10"
211
212config QUICC_MULT_FACTOR_11
213 depends on ARCH_MPC8360
214 bool "11"
215
216config QUICC_MULT_FACTOR_12
217 depends on ARCH_MPC8360
218 bool "12"
219
220config QUICC_MULT_FACTOR_13
221 depends on ARCH_MPC8360
222 bool "13"
223
224config QUICC_MULT_FACTOR_14
225 depends on ARCH_MPC8360
226 bool "14"
227
228config QUICC_MULT_FACTOR_15
229 depends on ARCH_MPC8360
230 bool "15"
231
232config QUICC_MULT_FACTOR_16
233 depends on ARCH_MPC8360
234 bool "16"
235
236config QUICC_MULT_FACTOR_17
237 depends on ARCH_MPC8360
238 bool "17"
239
240config QUICC_MULT_FACTOR_18
241 depends on ARCH_MPC8360
242 bool "18"
243
244config QUICC_MULT_FACTOR_19
245 depends on ARCH_MPC8360
246 bool "19"
247
248config QUICC_MULT_FACTOR_20
249 depends on ARCH_MPC8360
250 bool "20"
251
252config QUICC_MULT_FACTOR_21
253 depends on ARCH_MPC8360
254 bool "21"
255
256config QUICC_MULT_FACTOR_22
257 depends on ARCH_MPC8360
258 bool "22"
259
260config QUICC_MULT_FACTOR_23
261 depends on ARCH_MPC8360
262 bool "23"
263
264config QUICC_MULT_FACTOR_24
265 depends on ARCH_MPC8360
266 bool "24"
267
268config QUICC_MULT_FACTOR_25
269 depends on ARCH_MPC8360
270 bool "25"
271
272config QUICC_MULT_FACTOR_26
273 depends on ARCH_MPC8360
274 bool "26"
275
276config QUICC_MULT_FACTOR_27
277 depends on ARCH_MPC8360
278 bool "27"
279
280config QUICC_MULT_FACTOR_28
281 depends on ARCH_MPC8360
282 bool "28"
283
284config QUICC_MULT_FACTOR_29
285 depends on ARCH_MPC8360
286 bool "29"
287
288config QUICC_MULT_FACTOR_30
289 depends on ARCH_MPC8360
290 bool "30"
291
292config QUICC_MULT_FACTOR_31
293 depends on ARCH_MPC8360
294 bool "31"
295
296endchoice
297
298endif
299
300if MPC83XX_PCI_SUPPORT
301
302choice
303 prompt "PCI host mode"
304
305config PCI_HOST_MODE_DISABLE
306 bool "Disabled"
307
308config PCI_HOST_MODE_ENABLE
309 bool "Enabled"
310
311endchoice
312
313if ARCH_MPC8349
314
315choice
316 prompt "PCI 64-bit mode"
317
318config PCI_64BIT_MODE_DISABLE
319 bool "Disabled"
320
321config PCI_64BIT_MODE_ENABLE
322 bool "Enabled"
323
324endchoice
325
326endif
327
328choice
329 prompt "PCI internal arbiter 1 mode"
330
331config PCI_INT_ARBITER1_DISABLE
332 bool "Disabled"
333
334config PCI_INT_ARBITER1_ENABLE
335 bool "Enabled"
336
337endchoice
338
339if ARCH_MPC8349
340
341choice
342 prompt "PCI internal arbiter 2 mode"
343
344config PCI_INT_ARBITER2_DISABLE
345 bool "Disabled"
346
347config PCI_INT_ARBITER2_ENABLE
348 bool "Enabled"
349
350endchoice
351
352endif
353
354if ARCH_MPC8360
355
356choice
357 prompt "PCI clock output drive"
358
359config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
360 bool "Disabled"
361
362config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
363 bool "Enabled"
364
365endchoice
366
367endif
368
369endif
370
371choice
372 prompt "Core disable mode"
373
374config CORE_DISABLE_MODE_OFF
375 bool "Off"
376
377config CORE_DISABLE_MODE_ON
378 bool "On"
379
380endchoice
381
382choice
383 prompt "Boot Memory Space"
384
385config BOOT_MEMORY_SPACE_HIGH
386 bool "High"
387
388config BOOT_MEMORY_SPACE_LOW
389 bool "Low"
390
391endchoice
392
393choice
394 prompt "Boot Sequencer Configuration"
395
396config BOOT_SEQUENCER_DISABLED
397 bool "Disabled"
398
399config BOOT_SEQUENCER_NORMAL_I2C
400 bool "Normal I2C"
401
402config BOOT_SEQUENCER_EXTENDED_I2C
403 bool "Extended I2C"
404
405endchoice
406
407choice
408 prompt "Software Watchdog"
409
410config SOFTWARE_WATCHDOG_DISABLED
411 bool "Disabled"
412
413config SOFTWARE_WATCHDOG_ENABLED
414 bool "Enabled"
415
416endchoice
417
418choice
419 prompt "Boot ROM interface location"
420
421config BOOT_ROM_INTERFACE_DDR_SDRAM
422 bool "DDR_SDRAM"
423
424config BOOT_ROM_INTERFACE_PCI1
425 depends on MPC83XX_PCI_SUPPORT
426 bool "PCI1"
427
428config BOOT_ROM_INTERFACE_PCI2
429 depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
430 bool "PCI2"
431
432config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
433 depends on ARCH_MPC837X
434 bool "PCI2"
435
436config BOOT_ROM_INTERFACE_ESDHC
437 depends on ARCH_MPC8309
438 bool "eSDHC"
439
440config BOOT_ROM_INTERFACE_SPI
441 depends on ARCH_MPC8309
442 bool "SPI"
443
444config BOOT_ROM_INTERFACE_GPCM_8BIT
445 bool "Local bus GPCM - 8-bit ROM"
446
447config BOOT_ROM_INTERFACE_GPCM_16BIT
448 bool "Local bus GPCM - 16-bit ROM"
449
450config BOOT_ROM_INTERFACE_GPCM_32BIT
451 depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
452 bool "Local bus GPCM - 32-bit ROM"
453
454config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
455 depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
456 bool "Local bus NAND Flash- 8-bit small page ROM"
457
458config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
459 depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
460 bool "Local bus NAND Flash- 8-bit large page ROM"
461
462endchoice
463
464if MPC83XX_TSEC1_SUPPORT
465
466choice
467 prompt "TSEC1 mode"
468
469config TSEC1_MODE_MII
470 depends on !ARCH_MPC8349
471 bool "MII"
472
473config TSEC1_MODE_RMII
474 depends on ARCH_MPC831X && !ARCH_MPC8349
475 bool "RMII"
476
477config TSEC1_MODE_RGMII
478 bool "RGMII"
479
480config TSEC1_MODE_RTBI
481 depends on ARCH_MPC831X || ARCH_MPC837X
482 bool "RTBI"
483
484config TSEC1_MODE_GMII
485 depends on ARCH_MPC8349
486 bool "GMII"
487
488config TSEC1_MODE_TBI
489 depends on ARCH_MPC8349
490 bool "TBI"
491
492config TSEC1_MODE_SGMII
493 depends on ARCH_MPC831X || ARCH_MPC837X
494 bool "SGMII"
495
496endchoice
497
498endif
499
500if MPC83XX_TSEC2_SUPPORT
501
502choice
503 prompt "TSEC2 mode"
504
505config TSEC2_MODE_MII
506 depends on !ARCH_MPC8349
507 bool "MII"
508
509config TSEC2_MODE_RMII
510 depends on ARCH_MPC831X && !ARCH_MPC8349
511 bool "RMII"
512
513config TSEC2_MODE_RGMII
514 bool "RGMII"
515
516config TSEC2_MODE_RTBI
517 depends on ARCH_MPC831X || ARCH_MPC837X
518 bool "RTBI"
519
520config TSEC2_MODE_GMII
521 depends on ARCH_MPC8349
522 bool "GMII"
523
524config TSEC2_MODE_TBI
525 depends on ARCH_MPC8349
526 bool "TBI"
527
528config TSEC2_MODE_SGMII
529 depends on ARCH_MPC831X || ARCH_MPC837X
530 bool "SGMII"
531
532endchoice
533
534endif
535
536choice
537 prompt "True litle-endian mode"
538
539config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
540 bool "Big-endian"
541
542config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
543 bool "Little-endian"
544
545endchoice
546
547if ARCH_MPC8360
548
549choice
550 prompt "Secondary DDR IO"
551
552config SECONDARY_DDR_IO_DISABLE
553 bool "Disable"
554
555config SECONDARY_DDR_IO_ENABLE
556 bool "Enable"
557
558endchoice
559
560endif
561
562if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
563
564choice
565 prompt "LALE timing"
566
567config LALE_TIMING_NORMAL
568 bool "Normal"
569
570config LALE_TIMING_EARLIER
571 bool "Earlier"
572
573endchoice
574
575endif
576
577if MPC83XX_LDP_PIN
578
579choice
580 prompt "LDP pin mux state"
581
582config LDP_PIN_MUX_STATE_1
583 bool "Inital value 1"
584
585config LDP_PIN_MUX_STATE_0
586 bool "Inital value 0"
587
588endchoice
589
590endif
591
592endmenu
593
594config LBMC_CLOCK_MODE
595 int
596 default 0 if LBMC_CLOCK_MODE_1_1
597 default 1 if LBMC_CLOCK_MODE_1_2
598
599config DDR_MC_CLOCK_MODE
600 int
601 default 1 if DDR_MC_CLOCK_MODE_1_2
602 default 0 if DDR_MC_CLOCK_MODE_1_1
603
604config SYSTEM_PLL_VCO_DIV
605 int
606 default 0 if ARCH_MPC8349 || ARCH_MPC832X
607 default 2 if ARCH_MPC8313
608 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
609 default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
610 default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
611 default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
612 default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
613 default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
614 default 3 if SYSTEM_PLL_VCO_DIV_1
615
616config SYSTEM_PLL_FACTOR
617 int
618 default 2 if SYSTEM_PLL_FACTOR_2_1
619 default 3 if SYSTEM_PLL_FACTOR_3_1
620 default 4 if SYSTEM_PLL_FACTOR_4_1
621 default 5 if SYSTEM_PLL_FACTOR_5_1
622 default 6 if SYSTEM_PLL_FACTOR_6_1
623 default 7 if SYSTEM_PLL_FACTOR_7_1
624 default 8 if SYSTEM_PLL_FACTOR_8_1
625 default 9 if SYSTEM_PLL_FACTOR_9_1
626 default 10 if SYSTEM_PLL_FACTOR_10_1
627 default 11 if SYSTEM_PLL_FACTOR_11_1
628 default 12 if SYSTEM_PLL_FACTOR_12_1
629 default 13 if SYSTEM_PLL_FACTOR_13_1
630 default 14 if SYSTEM_PLL_FACTOR_14_1
631 default 15 if SYSTEM_PLL_FACTOR_15_1
632 default 0 if SYSTEM_PLL_FACTOR_16_1
633
634config CORE_PLL_RATIO
635 hex
636 default 0x0 if CORE_PLL_BYPASS
637 default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
638 default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
639 default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
640 default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
641 default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
642 default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
643 default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
644 default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
645 default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
646 default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
647 default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
648 default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
649 default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
650 default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
651 default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
652
653config CORE_DISABLE_MODE
654 int
655 default 0 if CORE_DISABLE_MODE_OFF
656 default 1 if CORE_DISABLE_MODE_ON
657
658config BOOT_MEMORY_SPACE
659 int
660 default 0 if BOOT_MEMORY_SPACE_LOW
661 default 1 if BOOT_MEMORY_SPACE_HIGH
662
663config BOOT_SEQUENCER
664 int
665 default 0 if BOOT_SEQUENCER_DISABLED
666 default 1 if BOOT_SEQUENCER_NORMAL_I2C
667 default 2 if BOOT_SEQUENCER_EXTENDED_I2C
668
669config SOFTWARE_WATCHDOG
670 int
671 default 0 if SOFTWARE_WATCHDOG_DISABLED
672 default 1 if SOFTWARE_WATCHDOG_ENABLED
673
674config BOOT_ROM_INTERFACE
675 hex
676 default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
677 default 0x4 if BOOT_ROM_INTERFACE_PCI1
678 default 0x8 if BOOT_ROM_INTERFACE_PCI2
679 default 0x8 if BOOT_ROM_INTERFACE_ESDHC
680 default 0xc if BOOT_ROM_INTERFACE_SPI
681 default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
682 default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
683 default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
684 default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
685 default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
686 default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
687
688config TSEC1_MODE
689 hex
690 default 0x0 if !MPC83XX_TSEC1_SUPPORT
691 default 0x0 if TSEC1_MODE_MII
692 default 0x1 if TSEC1_MODE_RMII
693 default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
694 default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
695 default 0x6 if TSEC1_MODE_SGMII
696 default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
697 default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
698 default 0x2 if TSEC1_MODE_GMII
699 default 0x3 if TSEC1_MODE_TBI
700
701config TSEC2_MODE
702 hex
703 default 0x0 if !MPC83XX_TSEC2_SUPPORT
704 default 0x0 if TSEC2_MODE_MII
705 default 0x1 if TSEC2_MODE_RMII
706 default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
707 default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
708 default 0x6 if TSEC2_MODE_SGMII
709 default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
710 default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
711 default 0x2 if TSEC2_MODE_GMII
712 default 0x3 if TSEC2_MODE_TBI
713
714config SECONDARY_DDR_IO
715 int
716 default 0 if !ARCH_MPC8360
717 default 0 if SECONDARY_DDR_IO_DISABLE
718 default 1 if SECONDARY_DDR_IO_ENABLE
719
720config TRUE_LITTLE_ENDIAN
721 int
722 default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
723 default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
724
725config LALE_TIMING
726 int
727 default 0 if ARCH_MPC830X || ARCH_MPC837X
728 default 0 if LALE_TIMING_NORMAL
729 default 1 if LALE_TIMING_EARLIER
730
731config LDP_PIN_MUX_STATE
732 int
733 default 0 if !MPC83XX_LDP_PIN
734 default 0 if LDP_PIN_MUX_STATE_1
735 default 1 if LDP_PIN_MUX_STATE_0
736
737config QUICC_VCO_DIVIDER
738 int
739 default 0 if !MPC83XX_QUICC_ENGINE
740 default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
741 default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
742 default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
743 default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
744 default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
745 default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
746
747config QUICC_DIV_FACTOR
748 int
749 default 0 if !MPC83XX_QUICC_ENGINE
750 default 0 if QUICC_DIV_FACTOR_1
751 default 1 if QUICC_DIV_FACTOR_2
752
753config QUICC_MULT_FACTOR
754 int
755 default 0 if !MPC83XX_QUICC_ENGINE
756 default 2 if QUICC_MULT_FACTOR_2
757 default 3 if QUICC_MULT_FACTOR_3
758 default 4 if QUICC_MULT_FACTOR_4
759 default 5 if QUICC_MULT_FACTOR_5
760 default 6 if QUICC_MULT_FACTOR_6
761 default 7 if QUICC_MULT_FACTOR_7
762 default 8 if QUICC_MULT_FACTOR_8
763 default 9 if QUICC_MULT_FACTOR_9
764 default 10 if QUICC_MULT_FACTOR_10
765 default 11 if QUICC_MULT_FACTOR_11
766 default 12 if QUICC_MULT_FACTOR_12
767 default 13 if QUICC_MULT_FACTOR_13
768 default 14 if QUICC_MULT_FACTOR_14
769 default 15 if QUICC_MULT_FACTOR_15
770 default 16 if QUICC_MULT_FACTOR_16
771 default 17 if QUICC_MULT_FACTOR_17
772 default 18 if QUICC_MULT_FACTOR_18
773 default 19 if QUICC_MULT_FACTOR_19
774 default 20 if QUICC_MULT_FACTOR_20
775 default 21 if QUICC_MULT_FACTOR_21
776 default 22 if QUICC_MULT_FACTOR_22
777 default 23 if QUICC_MULT_FACTOR_23
778 default 24 if QUICC_MULT_FACTOR_24
779 default 25 if QUICC_MULT_FACTOR_25
780 default 26 if QUICC_MULT_FACTOR_26
781 default 27 if QUICC_MULT_FACTOR_27
782 default 28 if QUICC_MULT_FACTOR_28
783 default 29 if QUICC_MULT_FACTOR_29
784 default 30 if QUICC_MULT_FACTOR_30
785 default 31 if QUICC_MULT_FACTOR_31
786
787config PCI_HOST_MODE
788 int
789 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
790 default 0 if PCI_HOST_MODE_DISABLE
791 default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
792
793config PCI_64BIT_MODE
794 int
795 default 0 if !ARCH_MPC8349
796 default 0 if PCI_64BIT_MODE_DISABLE
797 default 1 if PCI_64BIT_MODE_ENABLE
798
799config PCI_INT_ARBITER1
800 int
801 default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
802 default 0 if PCI_INT_ARBITER1_DISABLE
803 default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
804
805config PCI_INT_ARBITER2
806 int
807 default 0 if !ARCH_MPC8349
808 default 0 if PCI_INT_ARBITER2_DISABLE
809 default 1 if PCI_INT_ARBITER2_ENABLE
810
811config PCI_CLOCK_OUTPUT_DRIVE
812 int
813 default 0 if !ARCH_MPC8360
814 default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
815 default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE