Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 1 | |
| 2 | config BITBANGMII |
| 3 | bool "Bit-banged ethernet MII management channel support" |
| 4 | |
Tom Rini | 8b08437 | 2022-03-21 21:33:31 -0400 | [diff] [blame] | 5 | config BITBANGMII_MULTI |
| 6 | bool "Enable the multi bus support" |
| 7 | depends on BITBANGMII |
| 8 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 9 | config MV88E6352_SWITCH |
| 10 | bool "Marvell 88E6352 switch support" |
| 11 | |
| 12 | menuconfig PHYLIB |
| 13 | bool "Ethernet PHY (physical media interface) support" |
Michal Simek | 5647da0 | 2018-02-06 13:23:52 +0100 | [diff] [blame] | 14 | depends on NET |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 15 | help |
| 16 | Enable Ethernet PHY (physical media interface) support. |
| 17 | |
| 18 | if PHYLIB |
| 19 | |
Joe Hershberger | 46b7bd1 | 2018-03-30 11:52:16 -0500 | [diff] [blame] | 20 | config PHY_ADDR_ENABLE |
| 21 | bool "Limit phy address" |
| 22 | default y if ARCH_SUNXI |
| 23 | help |
| 24 | Select this if you want to control which phy address is used |
| 25 | |
| 26 | if PHY_ADDR_ENABLE |
Stefan Mavrodiev | e3ee5f5 | 2018-02-02 15:53:38 +0200 | [diff] [blame] | 27 | config PHY_ADDR |
| 28 | int "PHY address" |
| 29 | default 1 if ARCH_SUNXI |
| 30 | default 0 |
| 31 | help |
| 32 | The address of PHY on MII bus. Usually in range of 0 to 31. |
Joe Hershberger | 46b7bd1 | 2018-03-30 11:52:16 -0500 | [diff] [blame] | 33 | endif |
Stefan Mavrodiev | e3ee5f5 | 2018-02-02 15:53:38 +0200 | [diff] [blame] | 34 | |
Florian Fainelli | 01b4ade | 2017-12-09 14:59:54 -0800 | [diff] [blame] | 35 | config B53_SWITCH |
| 36 | bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support." |
| 37 | help |
| 38 | Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches. |
| 39 | This currently supports BCM53125 and similar models. |
| 40 | |
| 41 | if B53_SWITCH |
| 42 | |
| 43 | config B53_CPU_PORT |
| 44 | int "CPU port" |
| 45 | default 8 |
| 46 | |
| 47 | config B53_PHY_PORTS |
| 48 | hex "Bitmask of PHY ports" |
| 49 | |
| 50 | endif # B53_SWITCH |
| 51 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 52 | config MV88E61XX_SWITCH |
Anatolij Gustschin | b8b1a9e | 2019-10-27 01:14:41 +0200 | [diff] [blame] | 53 | bool "Marvell MV88E61xx Ethernet switch PHY support." |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 54 | |
Tim Harvey | c2cc9d4 | 2017-03-17 07:29:51 -0700 | [diff] [blame] | 55 | if MV88E61XX_SWITCH |
| 56 | |
| 57 | config MV88E61XX_CPU_PORT |
| 58 | int "CPU Port" |
| 59 | |
| 60 | config MV88E61XX_PHY_PORTS |
| 61 | hex "Bitmask of PHY Ports" |
| 62 | |
| 63 | config MV88E61XX_FIXED_PORTS |
| 64 | hex "Bitmask of PHYless serdes Ports" |
| 65 | |
| 66 | endif # MV88E61XX_SWITCH |
| 67 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 68 | config PHYLIB_10G |
| 69 | bool "Generic 10G PHY support" |
| 70 | |
Nate Drude | a9521ea | 2022-04-08 11:28:14 -0500 | [diff] [blame] | 71 | config PHY_ADIN |
| 72 | bool "Analog Devices Industrial Ethernet PHYs" |
| 73 | help |
| 74 | Add support for configuring RGMII on Analog Devices ADIN PHYs. |
| 75 | |
Jeremy Gebben | e662c0d | 2018-09-18 15:49:36 -0600 | [diff] [blame] | 76 | menuconfig PHY_AQUANTIA |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 77 | bool "Aquantia Ethernet PHYs support" |
Jeremy Gebben | abe3edf | 2018-09-18 15:49:35 -0600 | [diff] [blame] | 78 | select PHY_GIGE |
| 79 | select PHYLIB_10G |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 80 | |
Jeremy Gebben | e662c0d | 2018-09-18 15:49:36 -0600 | [diff] [blame] | 81 | config PHY_AQUANTIA_UPLOAD_FW |
| 82 | bool "Aquantia firmware loading support" |
Jeremy Gebben | e662c0d | 2018-09-18 15:49:36 -0600 | [diff] [blame] | 83 | depends on PHY_AQUANTIA |
| 84 | help |
| 85 | Aquantia PHYs use firmware which can be either loaded automatically |
| 86 | from storage directly attached to the phy or loaded by the boot loader |
| 87 | via MDIO commands. The firmware is loaded from a file, specified by |
| 88 | the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options. |
| 89 | |
| 90 | config PHY_AQUANTIA_FW_PART |
| 91 | string "Aquantia firmware partition" |
| 92 | depends on PHY_AQUANTIA_UPLOAD_FW |
| 93 | help |
| 94 | Partition containing the firmware file. |
| 95 | |
| 96 | config PHY_AQUANTIA_FW_NAME |
| 97 | string "Aquantia firmware filename" |
| 98 | depends on PHY_AQUANTIA_UPLOAD_FW |
| 99 | help |
| 100 | Firmware filename. |
| 101 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 102 | config PHY_ATHEROS |
| 103 | bool "Atheros Ethernet PHYs support" |
| 104 | |
| 105 | config PHY_BROADCOM |
| 106 | bool "Broadcom Ethernet PHYs support" |
| 107 | |
| 108 | config PHY_CORTINA |
| 109 | bool "Cortina Ethernet PHYs support" |
| 110 | |
Meenakshi Aggarwal | f5ddc84 | 2020-10-29 19:16:15 +0530 | [diff] [blame] | 111 | config SYS_CORTINA_NO_FW_UPLOAD |
| 112 | bool "Cortina firmware loading support" |
Meenakshi Aggarwal | f5ddc84 | 2020-10-29 19:16:15 +0530 | [diff] [blame] | 113 | depends on PHY_CORTINA |
| 114 | help |
| 115 | Cortina phy has provision to store phy firmware in attached dedicated |
| 116 | EEPROM. And boards designed with such EEPROM does not require firmware |
| 117 | upload. |
| 118 | |
Tom Rini | 0b0342f | 2019-11-26 17:32:43 -0500 | [diff] [blame] | 119 | choice |
| 120 | prompt "Location of the Cortina firmware" |
| 121 | default SYS_CORTINA_FW_IN_NOR |
| 122 | depends on PHY_CORTINA |
| 123 | |
| 124 | config SYS_CORTINA_FW_IN_MMC |
| 125 | bool "Cortina firmware in MMC" |
| 126 | |
| 127 | config SYS_CORTINA_FW_IN_NAND |
| 128 | bool "Cortina firmware in NAND flash" |
| 129 | |
| 130 | config SYS_CORTINA_FW_IN_NOR |
| 131 | bool "Cortina firmware in NOR flash" |
| 132 | |
| 133 | config SYS_CORTINA_FW_IN_REMOTE |
| 134 | bool "Cortina firmware in remote device" |
| 135 | |
| 136 | config SYS_CORTINA_FW_IN_SPIFLASH |
| 137 | bool "Cortina firmware in SPI flash" |
| 138 | |
| 139 | endchoice |
| 140 | |
Kuldeep Singh | 016965f | 2021-08-10 11:20:07 +0530 | [diff] [blame] | 141 | config CORTINA_FW_ADDR |
| 142 | hex "Cortina Firmware Address" |
| 143 | depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD |
| 144 | default 0x0 |
| 145 | |
| 146 | config CORTINA_FW_LENGTH |
| 147 | hex "Cortina Firmware Length" |
| 148 | depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD |
| 149 | default 0x40000 |
| 150 | |
Abbie Chang | 556872f | 2021-01-14 13:34:12 -0800 | [diff] [blame] | 151 | config PHY_CORTINA_ACCESS |
| 152 | bool "Cortina Access Ethernet PHYs support" |
| 153 | default y |
| 154 | depends on CORTINA_NI_ENET |
| 155 | help |
| 156 | Cortina Access Ethernet PHYs init process |
| 157 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 158 | config PHY_DAVICOM |
| 159 | bool "Davicom Ethernet PHYs support" |
| 160 | |
| 161 | config PHY_ET1011C |
| 162 | bool "LSI TruePHY ET1011C support" |
| 163 | |
| 164 | config PHY_LXT |
| 165 | bool "LXT971 Ethernet PHY support" |
| 166 | |
| 167 | config PHY_MARVELL |
| 168 | bool "Marvell Ethernet PHYs support" |
| 169 | |
Neil Armstrong | 7a4c90d | 2017-10-18 10:02:10 +0200 | [diff] [blame] | 170 | config PHY_MESON_GXL |
| 171 | bool "Amlogic Meson GXL Internal PHY support" |
| 172 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 173 | config PHY_MICREL |
| 174 | bool "Micrel Ethernet PHYs support" |
Philipp Tomsich | 00c3361 | 2017-03-26 18:50:23 +0200 | [diff] [blame] | 175 | help |
| 176 | Enable support for the GbE PHYs manufactured by Micrel (now |
James Byrne | bc292c2 | 2019-03-06 12:48:27 +0000 | [diff] [blame] | 177 | a part of Microchip). This includes drivers for the KSZ804, KSZ8031, |
| 178 | KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx |
| 179 | family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel |
| 180 | KSZ90x1 family support" is selected). |
Philipp Tomsich | 00c3361 | 2017-03-26 18:50:23 +0200 | [diff] [blame] | 181 | |
| 182 | if PHY_MICREL |
| 183 | |
| 184 | config PHY_MICREL_KSZ9021 |
Alexandru Gagniuc | 4c69ccb | 2017-07-07 11:37:00 -0700 | [diff] [blame] | 185 | bool |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 186 | select PHY_MICREL_KSZ90X1 |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 187 | |
Philipp Tomsich | 00c3361 | 2017-03-26 18:50:23 +0200 | [diff] [blame] | 188 | config PHY_MICREL_KSZ9031 |
Alexandru Gagniuc | 4c69ccb | 2017-07-07 11:37:00 -0700 | [diff] [blame] | 189 | bool |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 190 | select PHY_MICREL_KSZ90X1 |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 191 | |
| 192 | config PHY_MICREL_KSZ90X1 |
| 193 | bool "Micrel KSZ90x1 family support" |
| 194 | select PHY_GIGE |
| 195 | help |
| 196 | Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If |
| 197 | enabled, the extended register read/write for KSZ90x1 PHYs |
| 198 | is supported through the 'mdio' command and any RGMII signal |
| 199 | delays configured in the device tree will be applied to the |
| 200 | PHY during initialization. |
| 201 | |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 202 | config PHY_MICREL_KSZ8XXX |
| 203 | bool "Micrel KSZ8xxx family support" |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 204 | help |
James Byrne | bc292c2 | 2019-03-06 12:48:27 +0000 | [diff] [blame] | 205 | Enable support for the 8000 series 10/100 PHYs manufactured by Micrel |
Alexandru Gagniuc | 757bb67 | 2017-07-07 11:36:57 -0700 | [diff] [blame] | 206 | (now a part of Microchip). This includes drivers for the KSZ804, |
| 207 | KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721. |
| 208 | |
Philipp Tomsich | 00c3361 | 2017-03-26 18:50:23 +0200 | [diff] [blame] | 209 | endif # PHY_MICREL |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 210 | |
John Haechten | ee253f9 | 2016-12-09 22:15:17 +0000 | [diff] [blame] | 211 | config PHY_MSCC |
| 212 | bool "Microsemi Corp Ethernet PHYs support" |
| 213 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 214 | config PHY_NATSEMI |
| 215 | bool "National Semiconductor Ethernet PHYs support" |
| 216 | |
Radu Pirea (NXP OSS) | f2d36cb | 2021-06-18 21:58:30 +0300 | [diff] [blame] | 217 | config PHY_NXP_C45_TJA11XX |
| 218 | tristate "NXP C45 TJA11XX PHYs" |
| 219 | help |
| 220 | Enable support for NXP C45 TJA11XX PHYs. |
| 221 | Currently supports only the TJA1103 PHY. |
| 222 | |
Michael Trimarchi | 80ba436 | 2022-04-12 10:31:37 -0300 | [diff] [blame] | 223 | config PHY_NXP_TJA11XX |
| 224 | bool "NXP TJA11XX Ethernet PHYs support" |
| 225 | help |
| 226 | Currently supports the NXP TJA1100 and TJA1101 PHY. |
| 227 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 228 | config PHY_REALTEK |
| 229 | bool "Realtek Ethernet PHYs support" |
| 230 | |
| 231 | config RTL8211X_PHY_FORCE_MASTER |
| 232 | bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode" |
| 233 | depends on PHY_REALTEK |
| 234 | help |
| 235 | Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F). |
| 236 | This can work around link stability and data corruption issues on gigabit |
| 237 | links which can occur in slave mode on certain PHYs, e.g. on the |
| 238 | RTL8211C(L). |
| 239 | |
| 240 | Please note that two directly connected devices (i.e. via crossover cable) |
| 241 | will not be able to establish a link between each other if they both force |
| 242 | master mode. Multiple devices forcing master mode when connected by a |
| 243 | network switch do not pose a problem as the switch configures its affected |
| 244 | ports into slave mode. |
| 245 | |
| 246 | This option only affects gigabit links. If you must establish a direct |
| 247 | connection between two devices which both force master mode, try forcing |
| 248 | the link speed to 100MBit/s. |
| 249 | |
| 250 | If unsure, say N. |
| 251 | |
Carlo Caione | cf93d02 | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 252 | config RTL8211F_PHY_FORCE_EEE_RXC_ON |
| 253 | bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" |
| 254 | depends on PHY_REALTEK |
Carlo Caione | cf93d02 | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 255 | help |
| 256 | The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate |
| 257 | transitions to/from a lower power consumption level (Low Power Idle |
| 258 | mode) based on link utilization. When no packets are being |
| 259 | transmitted, the system goes to Low Power Idle mode to save power. |
| 260 | |
| 261 | Under particular circumstances this setting can cause issues where |
| 262 | the PHY is unable to transmit or receive any packet when in LPI mode. |
| 263 | The problem is caused when the PHY is configured to stop receiving |
| 264 | the xMII clock while it is signaling LPI. For some PHYs the bit |
| 265 | configuring this behavior is set by the Linux kernel, causing the |
| 266 | issue in U-Boot on reboot if the PHY retains the register value. |
| 267 | |
| 268 | Default n, which means that the PHY state is not changed. To work |
| 269 | around the issues, change this setting to y. |
| 270 | |
Amit Singh Tomar | 4f21b2a | 2020-05-09 19:55:11 +0530 | [diff] [blame] | 271 | config RTL8201F_PHY_S700_RMII_TIMINGS |
| 272 | bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings" |
| 273 | depends on PHY_REALTEK |
| 274 | help |
| 275 | This provides an option to configure specific timing requirements (needed |
| 276 | for proper PHY operations) for the PHY module present on ACTION SEMI S700 |
| 277 | based cubieboard7. Exact timing requiremnets seems to be SoC specific |
| 278 | (and it's undocumented) that comes from vendor code itself. |
| 279 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 280 | config PHY_SMSC |
| 281 | bool "Microchip(SMSC) Ethernet PHYs support" |
| 282 | |
| 283 | config PHY_TERANETICS |
| 284 | bool "Teranetics Ethernet PHYs support" |
| 285 | |
| 286 | config PHY_TI |
| 287 | bool "Texas Instruments Ethernet PHYs support" |
Dan Murphy | 8b8d73a | 2020-05-04 16:14:39 -0500 | [diff] [blame] | 288 | ---help--- |
| 289 | Adds PHY registration support for TI PHYs. |
| 290 | |
| 291 | config PHY_TI_DP83867 |
| 292 | select PHY_TI |
| 293 | bool "Texas Instruments Ethernet DP83867 PHY support" |
| 294 | ---help--- |
| 295 | Adds support for the TI DP83867 1Gbit PHY. |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 296 | |
Dominic Rath | 11147e0 | 2021-12-22 08:57:46 +0100 | [diff] [blame] | 297 | config PHY_TI_DP83869 |
| 298 | select PHY_TI |
| 299 | bool "Texas Instruments Ethernet DP83869 PHY support" |
| 300 | ---help--- |
| 301 | Adds support for the TI DP83869 1Gbit PHY. |
| 302 | |
Dan Murphy | 3434cd7 | 2020-05-04 16:14:40 -0500 | [diff] [blame] | 303 | config PHY_TI_GENERIC |
| 304 | select PHY_TI |
| 305 | bool "Texas Instruments Generic Ethernet PHYs support" |
| 306 | ---help--- |
| 307 | Adds support for Generic TI PHYs that don't need special handling but |
| 308 | the PHY name is associated with a PHY ID. |
| 309 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 310 | config PHY_VITESSE |
| 311 | bool "Vitesse Ethernet PHYs support" |
| 312 | |
| 313 | config PHY_XILINX |
| 314 | bool "Xilinx Ethernet PHYs support" |
| 315 | |
Siva Durga Prasad Paladugu | d5c4e1e | 2018-11-27 11:49:11 +0530 | [diff] [blame] | 316 | config PHY_XILINX_GMII2RGMII |
| 317 | bool "Xilinx GMII to RGMII Ethernet PHYs support" |
Bin Meng | 7e11558 | 2021-03-14 20:14:51 +0800 | [diff] [blame] | 318 | depends on DM_ETH |
Siva Durga Prasad Paladugu | d5c4e1e | 2018-11-27 11:49:11 +0530 | [diff] [blame] | 319 | help |
| 320 | This adds support for Xilinx GMII to RGMII IP core. This IP acts |
| 321 | as bridge between MAC connected over GMII and external phy that |
| 322 | is connected over RGMII interface. |
| 323 | |
Michal Simek | 488eec5 | 2022-02-23 15:45:42 +0100 | [diff] [blame] | 324 | config PHY_ETHERNET_ID |
| 325 | bool "Read ethernet PHY id" |
| 326 | depends on DM_GPIO |
| 327 | default y if ZYNQ_GEM |
| 328 | help |
| 329 | Enable this config to read ethernet phy id from the phy node of DT |
| 330 | and create a phy device using id. |
| 331 | |
Hannes Schmelzer | da49460 | 2017-03-23 15:11:43 +0100 | [diff] [blame] | 332 | config PHY_FIXED |
| 333 | bool "Fixed-Link PHY" |
| 334 | depends on DM_ETH |
| 335 | help |
| 336 | Fixed PHY is used for having a 'fixed-link' to another MAC with a direct |
| 337 | connection (MII, RGMII, ...). |
| 338 | There is nothing like autoneogation and so |
| 339 | on, the link is always up with fixed speed and fixed duplex-setting. |
| 340 | More information: doc/device-tree-bindings/net/fixed-link.txt |
| 341 | |
Samuel Mendoza-Jonas | 2325c44 | 2019-06-18 11:37:17 +1000 | [diff] [blame] | 342 | config PHY_NCSI |
| 343 | bool "NC-SI based PHY" |
| 344 | depends on DM_ETH |
| 345 | |
Alex | 89e50d9 | 2017-02-06 19:17:34 -0800 | [diff] [blame] | 346 | endif #PHYLIB |
Tom Rini | 6c85151 | 2022-03-18 08:38:26 -0400 | [diff] [blame] | 347 | |
Tom Rini | 33ae6a7 | 2022-07-23 13:05:10 -0400 | [diff] [blame] | 348 | config FSL_MEMAC |
| 349 | bool "NXP mEMAC PHY support" |
| 350 | |
| 351 | config SYS_MEMAC_LITTLE_ENDIAN |
| 352 | bool "mEMAC is access in little endian mode" |
| 353 | depends on FSL_MEMAC || FSL_LS_MDIO |
| 354 | |
Tom Rini | 6c85151 | 2022-03-18 08:38:26 -0400 | [diff] [blame] | 355 | config PHY_RESET_DELAY |
| 356 | int "Extra delay after reset before MII register access" |
| 357 | default 0 |
| 358 | help |
| 359 | Some PHYs need extra delay after reset before any MII register access |
| 360 | is possible. For such PHY, set this option to the usec delay |
| 361 | required. |