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Alex89e50d92017-02-06 19:17:34 -08001
2config BITBANGMII
3 bool "Bit-banged ethernet MII management channel support"
4
5config MV88E6352_SWITCH
6 bool "Marvell 88E6352 switch support"
7
8menuconfig PHYLIB
9 bool "Ethernet PHY (physical media interface) support"
Michal Simek5647da02018-02-06 13:23:52 +010010 depends on NET
Alex89e50d92017-02-06 19:17:34 -080011 help
12 Enable Ethernet PHY (physical media interface) support.
13
14if PHYLIB
15
Joe Hershberger46b7bd12018-03-30 11:52:16 -050016config PHY_ADDR_ENABLE
17 bool "Limit phy address"
18 default y if ARCH_SUNXI
19 help
20 Select this if you want to control which phy address is used
21
22if PHY_ADDR_ENABLE
Stefan Mavrodieve3ee5f52018-02-02 15:53:38 +020023config PHY_ADDR
24 int "PHY address"
25 default 1 if ARCH_SUNXI
26 default 0
27 help
28 The address of PHY on MII bus. Usually in range of 0 to 31.
Joe Hershberger46b7bd12018-03-30 11:52:16 -050029endif
Stefan Mavrodieve3ee5f52018-02-02 15:53:38 +020030
Florian Fainelli01b4ade2017-12-09 14:59:54 -080031config B53_SWITCH
32 bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
33 help
34 Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
35 This currently supports BCM53125 and similar models.
36
37if B53_SWITCH
38
39config B53_CPU_PORT
40 int "CPU port"
41 default 8
42
43config B53_PHY_PORTS
44 hex "Bitmask of PHY ports"
45
46endif # B53_SWITCH
47
Alex89e50d92017-02-06 19:17:34 -080048config MV88E61XX_SWITCH
Anatolij Gustschinb8b1a9e2019-10-27 01:14:41 +020049 bool "Marvell MV88E61xx Ethernet switch PHY support."
Alex89e50d92017-02-06 19:17:34 -080050
Tim Harveyc2cc9d42017-03-17 07:29:51 -070051if MV88E61XX_SWITCH
52
53config MV88E61XX_CPU_PORT
54 int "CPU Port"
55
56config MV88E61XX_PHY_PORTS
57 hex "Bitmask of PHY Ports"
58
59config MV88E61XX_FIXED_PORTS
60 hex "Bitmask of PHYless serdes Ports"
61
62endif # MV88E61XX_SWITCH
63
Alex89e50d92017-02-06 19:17:34 -080064config PHYLIB_10G
65 bool "Generic 10G PHY support"
66
Jeremy Gebbene662c0d2018-09-18 15:49:36 -060067menuconfig PHY_AQUANTIA
Alex89e50d92017-02-06 19:17:34 -080068 bool "Aquantia Ethernet PHYs support"
Jeremy Gebbenabe3edf2018-09-18 15:49:35 -060069 select PHY_GIGE
70 select PHYLIB_10G
Alex89e50d92017-02-06 19:17:34 -080071
Jeremy Gebbene662c0d2018-09-18 15:49:36 -060072config PHY_AQUANTIA_UPLOAD_FW
73 bool "Aquantia firmware loading support"
Jeremy Gebbene662c0d2018-09-18 15:49:36 -060074 depends on PHY_AQUANTIA
75 help
76 Aquantia PHYs use firmware which can be either loaded automatically
77 from storage directly attached to the phy or loaded by the boot loader
78 via MDIO commands. The firmware is loaded from a file, specified by
79 the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
80
81config PHY_AQUANTIA_FW_PART
82 string "Aquantia firmware partition"
83 depends on PHY_AQUANTIA_UPLOAD_FW
84 help
85 Partition containing the firmware file.
86
87config PHY_AQUANTIA_FW_NAME
88 string "Aquantia firmware filename"
89 depends on PHY_AQUANTIA_UPLOAD_FW
90 help
91 Firmware filename.
92
Alex89e50d92017-02-06 19:17:34 -080093config PHY_ATHEROS
94 bool "Atheros Ethernet PHYs support"
95
96config PHY_BROADCOM
97 bool "Broadcom Ethernet PHYs support"
98
99config PHY_CORTINA
100 bool "Cortina Ethernet PHYs support"
101
Meenakshi Aggarwalf5ddc842020-10-29 19:16:15 +0530102config SYS_CORTINA_NO_FW_UPLOAD
103 bool "Cortina firmware loading support"
Meenakshi Aggarwalf5ddc842020-10-29 19:16:15 +0530104 depends on PHY_CORTINA
105 help
106 Cortina phy has provision to store phy firmware in attached dedicated
107 EEPROM. And boards designed with such EEPROM does not require firmware
108 upload.
109
Tom Rini0b0342f2019-11-26 17:32:43 -0500110choice
111 prompt "Location of the Cortina firmware"
112 default SYS_CORTINA_FW_IN_NOR
113 depends on PHY_CORTINA
114
115config SYS_CORTINA_FW_IN_MMC
116 bool "Cortina firmware in MMC"
117
118config SYS_CORTINA_FW_IN_NAND
119 bool "Cortina firmware in NAND flash"
120
121config SYS_CORTINA_FW_IN_NOR
122 bool "Cortina firmware in NOR flash"
123
124config SYS_CORTINA_FW_IN_REMOTE
125 bool "Cortina firmware in remote device"
126
127config SYS_CORTINA_FW_IN_SPIFLASH
128 bool "Cortina firmware in SPI flash"
129
130endchoice
131
Kuldeep Singh016965f2021-08-10 11:20:07 +0530132config CORTINA_FW_ADDR
133 hex "Cortina Firmware Address"
134 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
135 default 0x0
136
137config CORTINA_FW_LENGTH
138 hex "Cortina Firmware Length"
139 depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
140 default 0x40000
141
Abbie Chang556872f2021-01-14 13:34:12 -0800142config PHY_CORTINA_ACCESS
143 bool "Cortina Access Ethernet PHYs support"
144 default y
145 depends on CORTINA_NI_ENET
146 help
147 Cortina Access Ethernet PHYs init process
148
Alex89e50d92017-02-06 19:17:34 -0800149config PHY_DAVICOM
150 bool "Davicom Ethernet PHYs support"
151
152config PHY_ET1011C
153 bool "LSI TruePHY ET1011C support"
154
155config PHY_LXT
156 bool "LXT971 Ethernet PHY support"
157
158config PHY_MARVELL
159 bool "Marvell Ethernet PHYs support"
160
Neil Armstrong7a4c90d2017-10-18 10:02:10 +0200161config PHY_MESON_GXL
162 bool "Amlogic Meson GXL Internal PHY support"
163
Alex89e50d92017-02-06 19:17:34 -0800164config PHY_MICREL
165 bool "Micrel Ethernet PHYs support"
Philipp Tomsich00c33612017-03-26 18:50:23 +0200166 help
167 Enable support for the GbE PHYs manufactured by Micrel (now
James Byrnebc292c22019-03-06 12:48:27 +0000168 a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
169 KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
170 family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
171 KSZ90x1 family support" is selected).
Philipp Tomsich00c33612017-03-26 18:50:23 +0200172
173if PHY_MICREL
174
175config PHY_MICREL_KSZ9021
Alexandru Gagniuc4c69ccb2017-07-07 11:37:00 -0700176 bool
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700177 select PHY_MICREL_KSZ90X1
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700178
Philipp Tomsich00c33612017-03-26 18:50:23 +0200179config PHY_MICREL_KSZ9031
Alexandru Gagniuc4c69ccb2017-07-07 11:37:00 -0700180 bool
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700181 select PHY_MICREL_KSZ90X1
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700182
183config PHY_MICREL_KSZ90X1
184 bool "Micrel KSZ90x1 family support"
185 select PHY_GIGE
186 help
187 Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
188 enabled, the extended register read/write for KSZ90x1 PHYs
189 is supported through the 'mdio' command and any RGMII signal
190 delays configured in the device tree will be applied to the
191 PHY during initialization.
192
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700193config PHY_MICREL_KSZ8XXX
194 bool "Micrel KSZ8xxx family support"
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700195 help
James Byrnebc292c22019-03-06 12:48:27 +0000196 Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
Alexandru Gagniuc757bb672017-07-07 11:36:57 -0700197 (now a part of Microchip). This includes drivers for the KSZ804,
198 KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
199
Philipp Tomsich00c33612017-03-26 18:50:23 +0200200endif # PHY_MICREL
Alex89e50d92017-02-06 19:17:34 -0800201
John Haechtenee253f92016-12-09 22:15:17 +0000202config PHY_MSCC
203 bool "Microsemi Corp Ethernet PHYs support"
204
Alex89e50d92017-02-06 19:17:34 -0800205config PHY_NATSEMI
206 bool "National Semiconductor Ethernet PHYs support"
207
Radu Pirea (NXP OSS)f2d36cb2021-06-18 21:58:30 +0300208config PHY_NXP_C45_TJA11XX
209 tristate "NXP C45 TJA11XX PHYs"
210 help
211 Enable support for NXP C45 TJA11XX PHYs.
212 Currently supports only the TJA1103 PHY.
213
Alex89e50d92017-02-06 19:17:34 -0800214config PHY_REALTEK
215 bool "Realtek Ethernet PHYs support"
216
217config RTL8211X_PHY_FORCE_MASTER
218 bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
219 depends on PHY_REALTEK
220 help
221 Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
222 This can work around link stability and data corruption issues on gigabit
223 links which can occur in slave mode on certain PHYs, e.g. on the
224 RTL8211C(L).
225
226 Please note that two directly connected devices (i.e. via crossover cable)
227 will not be able to establish a link between each other if they both force
228 master mode. Multiple devices forcing master mode when connected by a
229 network switch do not pose a problem as the switch configures its affected
230 ports into slave mode.
231
232 This option only affects gigabit links. If you must establish a direct
233 connection between two devices which both force master mode, try forcing
234 the link speed to 100MBit/s.
235
236 If unsure, say N.
237
Carlo Caionecf93d022019-01-24 08:54:37 +0000238config RTL8211F_PHY_FORCE_EEE_RXC_ON
239 bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
240 depends on PHY_REALTEK
Carlo Caionecf93d022019-01-24 08:54:37 +0000241 help
242 The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
243 transitions to/from a lower power consumption level (Low Power Idle
244 mode) based on link utilization. When no packets are being
245 transmitted, the system goes to Low Power Idle mode to save power.
246
247 Under particular circumstances this setting can cause issues where
248 the PHY is unable to transmit or receive any packet when in LPI mode.
249 The problem is caused when the PHY is configured to stop receiving
250 the xMII clock while it is signaling LPI. For some PHYs the bit
251 configuring this behavior is set by the Linux kernel, causing the
252 issue in U-Boot on reboot if the PHY retains the register value.
253
254 Default n, which means that the PHY state is not changed. To work
255 around the issues, change this setting to y.
256
Amit Singh Tomar4f21b2a2020-05-09 19:55:11 +0530257config RTL8201F_PHY_S700_RMII_TIMINGS
258 bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
259 depends on PHY_REALTEK
260 help
261 This provides an option to configure specific timing requirements (needed
262 for proper PHY operations) for the PHY module present on ACTION SEMI S700
263 based cubieboard7. Exact timing requiremnets seems to be SoC specific
264 (and it's undocumented) that comes from vendor code itself.
265
Alex89e50d92017-02-06 19:17:34 -0800266config PHY_SMSC
267 bool "Microchip(SMSC) Ethernet PHYs support"
268
269config PHY_TERANETICS
270 bool "Teranetics Ethernet PHYs support"
271
272config PHY_TI
273 bool "Texas Instruments Ethernet PHYs support"
Dan Murphy8b8d73a2020-05-04 16:14:39 -0500274 ---help---
275 Adds PHY registration support for TI PHYs.
276
277config PHY_TI_DP83867
278 select PHY_TI
279 bool "Texas Instruments Ethernet DP83867 PHY support"
280 ---help---
281 Adds support for the TI DP83867 1Gbit PHY.
Alex89e50d92017-02-06 19:17:34 -0800282
Dominic Rath11147e02021-12-22 08:57:46 +0100283config PHY_TI_DP83869
284 select PHY_TI
285 bool "Texas Instruments Ethernet DP83869 PHY support"
286 ---help---
287 Adds support for the TI DP83869 1Gbit PHY.
288
Dan Murphy3434cd72020-05-04 16:14:40 -0500289config PHY_TI_GENERIC
290 select PHY_TI
291 bool "Texas Instruments Generic Ethernet PHYs support"
292 ---help---
293 Adds support for Generic TI PHYs that don't need special handling but
294 the PHY name is associated with a PHY ID.
295
Alex89e50d92017-02-06 19:17:34 -0800296config PHY_VITESSE
297 bool "Vitesse Ethernet PHYs support"
298
299config PHY_XILINX
300 bool "Xilinx Ethernet PHYs support"
301
Siva Durga Prasad Paladugud5c4e1e2018-11-27 11:49:11 +0530302config PHY_XILINX_GMII2RGMII
303 bool "Xilinx GMII to RGMII Ethernet PHYs support"
Bin Meng7e115582021-03-14 20:14:51 +0800304 depends on DM_ETH
Siva Durga Prasad Paladugud5c4e1e2018-11-27 11:49:11 +0530305 help
306 This adds support for Xilinx GMII to RGMII IP core. This IP acts
307 as bridge between MAC connected over GMII and external phy that
308 is connected over RGMII interface.
309
Michal Simek488eec52022-02-23 15:45:42 +0100310config PHY_ETHERNET_ID
311 bool "Read ethernet PHY id"
312 depends on DM_GPIO
313 default y if ZYNQ_GEM
314 help
315 Enable this config to read ethernet phy id from the phy node of DT
316 and create a phy device using id.
317
Hannes Schmelzerda494602017-03-23 15:11:43 +0100318config PHY_FIXED
319 bool "Fixed-Link PHY"
320 depends on DM_ETH
321 help
322 Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
323 connection (MII, RGMII, ...).
324 There is nothing like autoneogation and so
325 on, the link is always up with fixed speed and fixed duplex-setting.
326 More information: doc/device-tree-bindings/net/fixed-link.txt
327
Samuel Mendoza-Jonas2325c442019-06-18 11:37:17 +1000328config PHY_NCSI
329 bool "NC-SI based PHY"
330 depends on DM_ETH
331
Alex89e50d92017-02-06 19:17:34 -0800332endif #PHYLIB
Tom Rini6c851512022-03-18 08:38:26 -0400333
334config PHY_RESET_DELAY
335 int "Extra delay after reset before MII register access"
336 default 0
337 help
338 Some PHYs need extra delay after reset before any MII register access
339 is possible. For such PHY, set this option to the usec delay
340 required.