blob: 9bddb8b0072331ed1a7d6b89325186b3161be95d [file] [log] [blame]
Michal Simek2e53eb22022-09-19 14:21:02 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016 - 2022, Xilinx, Inc.
4 * Copyright (C) 2022, Advanced Micro Devices, Inc.
5 */
6
7#ifndef __ASSEMBLY__
8#include <linux/bitops.h>
9#endif
10
Ashok Reddy Soma81627322023-01-10 08:44:07 +010011struct crlapb_regs {
12 u32 reserved0[67];
13 u32 cpu_r5_ctrl;
14 u32 reserved;
15 u32 iou_switch_ctrl; /* 0x114 */
16 u32 reserved1[13];
17 u32 timestamp_ref_ctrl; /* 0x14c */
18 u32 reserved3[108];
19 u32 rst_cpu_r5;
20 u32 reserved2[17];
21 u32 rst_timestamp; /* 0x348 */
22};
23
24struct iou_scntrs_regs {
25 u32 counter_control_register; /* 0x0 */
26 u32 reserved0[7];
27 u32 base_frequency_id_register; /* 0x20 */
28};
29
Ashok Reddy Somaa7a5a1b2023-05-16 08:47:53 -060030struct crp_regs {
31 u32 reserved0[128];
32 u32 boot_mode_usr; /* 0x200 */
33};
34
Ashok Reddy Soma81627322023-01-10 08:44:07 +010035#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000
Ashok Reddy Somaa7a5a1b2023-05-16 08:47:53 -060036#define VERSAL_NET_CRP_BASEADDR 0xF1260000
Ashok Reddy Soma81627322023-01-10 08:44:07 +010037#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000
38
39#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
40#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
41#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
42#define IOU_SCNTRS_CONTROL_EN 1
43
44#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
Ashok Reddy Somaa7a5a1b2023-05-16 08:47:53 -060045#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
Ashok Reddy Soma81627322023-01-10 08:44:07 +010046#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
47
Michal Simek2e53eb22022-09-19 14:21:02 +020048#define PMC_TAP 0xF11A0000
49
50#define PMC_TAP_IDCODE (PMC_TAP + 0)
51#define PMC_TAP_VERSION (PMC_TAP + 0x4)
52# define PMC_VERSION_MASK GENMASK(7, 0)
53# define PS_VERSION_MASK GENMASK(15, 8)
Michal Simekba73d6e2023-05-17 10:21:32 +020054# define PS_VERSION_PRODUCTION 0x20
Michal Simek2e53eb22022-09-19 14:21:02 +020055# define RTL_VERSION_MASK GENMASK(23, 16)
56# define PLATFORM_MASK GENMASK(27, 24)
57# define PLATFORM_VERSION_MASK GENMASK(31, 28)
58#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
59
Ashok Reddy Somaa7a5a1b2023-05-16 08:47:53 -060060/* Bootmode setting values */
61#define BOOT_MODES_MASK 0x0000000F
62#define QSPI_MODE_24BIT 0x00000001
63#define QSPI_MODE_32BIT 0x00000002
64#define SD_MODE 0x00000003 /* sd 0 */
65#define SD_MODE1 0x00000005 /* sd 1 */
66#define EMMC_MODE 0x00000006
67#define USB_MODE 0x00000007
68#define OSPI_MODE 0x00000008
69#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
70#define JTAG_MODE 0x00000000
71#define BOOT_MODE_USE_ALT 0x100
72#define BOOT_MODE_ALT_SHIFT 12
73
Michal Simek2e53eb22022-09-19 14:21:02 +020074enum versal_net_platform {
75 VERSAL_NET_SILICON = 0,
76 VERSAL_NET_SPP = 1,
77 VERSAL_NET_EMU = 2,
78 VERSAL_NET_QEMU = 3,
79};
Michal Simek2895a222022-09-19 14:21:03 +020080
81#define VERSAL_SLCR_BASEADDR 0xF1060000
82#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
83#define VERSAL_OSPI_LINEAR_MODE BIT(1)
Ashok Reddy Somab6421112023-06-14 06:04:52 -060084
85#define FLASH_RESET_GPIO 0xc
86#define WPROT_CRP 0xF126001C
87#define RST_GPIO 0xF1260318
88#define WPROT_LPD_MIO 0xFF080728
89#define WPROT_PMC_MIO 0xF1060828
90#define BOOT_MODE_DIR 0xF1020204
91#define BOOT_MODE_OUT 0xF1020208
92#define MIO_PIN_12 0xF1060030
93#define BANK0_OUTPUT 0xF1020040
94#define BANK0_TRI 0xF1060200