cadence_qspi: Enable flash reset for Versal NET platform
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.
Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.
Add read_delay initialization for Versal NET also.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index 3f04104..9bddb8b 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -81,3 +81,14 @@
#define VERSAL_SLCR_BASEADDR 0xF1060000
#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
#define VERSAL_OSPI_LINEAR_MODE BIT(1)
+
+#define FLASH_RESET_GPIO 0xc
+#define WPROT_CRP 0xF126001C
+#define RST_GPIO 0xF1260318
+#define WPROT_LPD_MIO 0xFF080728
+#define WPROT_PMC_MIO 0xF1060828
+#define BOOT_MODE_DIR 0xF1020204
+#define BOOT_MODE_OUT 0xF1020208
+#define MIO_PIN_12 0xF1060030
+#define BANK0_OUTPUT 0xF1020040
+#define BANK0_TRI 0xF1060200