net: zynq_gem: Don't hardcode the MDC clock divisor
As per spec MDC must not exceed 2.5MHz, read the pclk clock
from the device tree and update the MDC clock divisor.
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on
the clock rate of the pclk clock.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
1 file changed