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git01.mediatek.com / filogic / uboot / b5f0372fea958517ac2b14a6bba3e44f436bd6b0 / . / arch / riscv / cpu / fu540 / Kconfig
blob: c68209d8fb29d79c54d6bba934622ad968f9b73c [file] [log] [blame]
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4
5config SIFIVE_FU540
6 bool
7 select ARCH_EARLY_INIT_R
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]8 select SUPPORT_SPL
9 select RAM
10 select SPL_RAM if SPL
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]11 imply CPU
12 imply CPU_RISCV
Sean Anderson9baaaef2020-09-28 10:52:21 -0400[diff] [blame]13 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
Bin Mengb5f03722023-06-21 23:11:46 +0800[diff] [blame^]14 imply SPL_RISCV_ACLINT
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]15 imply CMD_CPU
Simon Glass2f002162021-03-15 18:11:18 +1300[diff] [blame]16 imply SPL_CPU
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]17 imply SPL_OPENSBI
18 imply SPL_LOAD_FIT
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]19 imply SMP
20 imply CLK_SIFIVE
Green Wanecefa5f2021-05-27 06:52:08 -0700[diff] [blame]21 imply CLK_SIFIVE_PRCI
Zong Liec348492021-09-01 15:01:42 +0800[diff] [blame]22 imply SIFIVE_CACHE
23 imply SIFIVE_CCACHE
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]24 imply SIFIVE_SERIAL
25 imply MACB
26 imply MII
27 imply SPI
28 imply SPI_SIFIVE
29 imply MMC
30 imply MMC_SPI
31 imply MMC_BROKEN_CD
32 imply CMD_MMC
33 imply DM_GPIO
34 imply SIFIVE_GPIO
35 imply CMD_GPIO
36 imply MISC
37 imply SIFIVE_OTP
38 imply DM_PWM
39 imply PWM_SIFIVE
Pragnesh Patel4f1b4442020-11-14 14:42:35 +0530[diff] [blame]40 imply DM_I2C
41 imply SYS_I2C_OCORES
Jagan Tekie70ef902020-07-15 15:39:00 +0530[diff] [blame]42
43if ENV_IS_IN_SPI_FLASH
44
45config ENV_OFFSET
46 default 0x505000
47
48config ENV_SIZE
49 default 0x20000
50
51config ENV_SECT_SIZE
52 default 0x10000
53
54endif # ENV_IS_IN_SPI_FLASH