blob: ac3f183342f9ce271f13f3b5ad67614c824a47fa [file] [log] [blame]
Pragnesh Patel25269c02020-05-29 11:33:34 +05301# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4
5config SIFIVE_FU540
6 bool
7 select ARCH_EARLY_INIT_R
Bin Meng6b155512020-08-02 23:09:04 -07008 select SUPPORT_SPL
9 select RAM
10 select SPL_RAM if SPL
Pragnesh Patel25269c02020-05-29 11:33:34 +053011 imply CPU
12 imply CPU_RISCV
Sean Anderson9baaaef2020-09-28 10:52:21 -040013 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
Pragnesh Patel25269c02020-05-29 11:33:34 +053014 imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
15 imply CMD_CPU
16 imply SPL_CPU_SUPPORT
17 imply SPL_OPENSBI
18 imply SPL_LOAD_FIT
Bin Meng6b155512020-08-02 23:09:04 -070019 imply SMP
20 imply CLK_SIFIVE
21 imply CLK_SIFIVE_FU540_PRCI
22 imply SIFIVE_SERIAL
23 imply MACB
24 imply MII
25 imply SPI
26 imply SPI_SIFIVE
27 imply MMC
28 imply MMC_SPI
29 imply MMC_BROKEN_CD
30 imply CMD_MMC
31 imply DM_GPIO
32 imply SIFIVE_GPIO
33 imply CMD_GPIO
34 imply MISC
35 imply SIFIVE_OTP
36 imply DM_PWM
37 imply PWM_SIFIVE
Jagan Tekie70ef902020-07-15 15:39:00 +053038
39if ENV_IS_IN_SPI_FLASH
40
41config ENV_OFFSET
42 default 0x505000
43
44config ENV_SIZE
45 default 0x20000
46
47config ENV_SECT_SIZE
48 default 0x10000
49
50endif # ENV_IS_IN_SPI_FLASH