blob: 9abad3f82497564bcd3e211e94ade665498504cd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyap0d2f2772013-08-21 10:38:56 +05302/*
3 * Copyright (C) 2013 Samsung Electronics
Chander Kashyap0d2f2772013-08-21 10:38:56 +05304 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Inderpal Singh3260bc82014-01-08 09:19:57 +05309#include <usb.h>
Simon Glass37f11622014-10-20 19:48:37 -060010#include <asm/gpio.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053011#include <asm/arch/pinmux.h>
Inderpal Singh04bb7372013-08-21 10:38:57 +053012#include <asm/arch/dwmmc.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053013#include <asm/arch/power.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
Inderpal Singh3260bc82014-01-08 09:19:57 +053017#ifdef CONFIG_USB_EHCI_EXYNOS
18int board_usb_init(int index, enum usb_init_type init)
19{
Inderpal Singh3260bc82014-01-08 09:19:57 +053020 /* Configure gpios for usb 3503 hub:
21 * disconnect, toggle reset and connect
22 */
Simon Glass4f83d3d2014-10-20 19:48:39 -060023 gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
24 gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053025 gpio_direction_output(EXYNOS5_GPIO_D17, 0);
26 gpio_direction_output(EXYNOS5_GPIO_X35, 0);
Inderpal Singh3260bc82014-01-08 09:19:57 +053027
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053028 gpio_direction_output(EXYNOS5_GPIO_X35, 1);
29 gpio_direction_output(EXYNOS5_GPIO_D17, 1);
Inderpal Singh3260bc82014-01-08 09:19:57 +053030
31 return 0;
32}
33#endif
34
Chander Kashyap0d2f2772013-08-21 10:38:56 +053035int board_init(void)
36{
37 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
38 return 0;
39}
40
41int dram_init(void)
42{
43 int i;
44 u32 addr;
45
46 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
47 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
48 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
49 }
50 return 0;
51}
52
53int power_init_board(void)
54{
55 set_ps_hold_ctrl();
56 return 0;
57}
58
Simon Glass2f949c32017-03-31 08:40:32 -060059int dram_init_banksize(void)
Chander Kashyap0d2f2772013-08-21 10:38:56 +053060{
61 int i;
62 u32 addr, size;
63
64 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
65 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
66 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
67
68 gd->bd->bi_dram[i].start = addr;
69 gd->bd->bi_dram[i].size = size;
70 }
Simon Glass2f949c32017-03-31 08:40:32 -060071
72 return 0;
Chander Kashyap0d2f2772013-08-21 10:38:56 +053073}
74
Masahiro Yamada0a780172017-05-09 20:31:39 +090075#ifdef CONFIG_MMC
Inderpal Singh04bb7372013-08-21 10:38:57 +053076int board_mmc_init(bd_t *bis)
77{
78 int ret;
79 /* dwmmc initializattion for available channels */
80 ret = exynos_dwmmc_init(gd->fdt_blob);
81 if (ret)
82 debug("dwmmc init failed\n");
83
84 return ret;
85}
86#endif
87
Chander Kashyap0d2f2772013-08-21 10:38:56 +053088static int board_uart_init(void)
89{
90 int err = 0, uart_id;
91
92 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
93 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
94 if (err) {
95 debug("UART%d not configured\n",
96 (uart_id - PERIPH_ID_UART0));
97 return err;
98 }
99 }
100 return err;
101}
102
103#ifdef CONFIG_BOARD_EARLY_INIT_F
104int board_early_init_f(void)
105{
106 int err;
107
108 err = board_uart_init();
109 if (err) {
110 debug("UART init failed\n");
111 return err;
112 }
113 return err;
114}
115#endif
116
117#ifdef CONFIG_DISPLAY_BOARDINFO
118int checkboard(void)
119{
120 printf("\nBoard: Arndale\n");
121
122 return 0;
123}
124#endif
Andre Przywara64d4c222014-08-01 13:35:44 +0200125
126#ifdef CONFIG_S5P_PA_SYSRAM
127void smp_set_core_boot_addr(unsigned long addr, int corenr)
128{
129 writel(addr, CONFIG_S5P_PA_SYSRAM);
130
131 /* make sure this write is really executed */
132 __asm__ volatile ("dsb\n");
133}
134#endif