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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyap0d2f2772013-08-21 10:38:56 +05302/*
3 * Copyright (C) 2013 Samsung Electronics
Chander Kashyap0d2f2772013-08-21 10:38:56 +05304 */
5
6#include <common.h>
Simon Glass370382c2019-11-14 12:57:35 -07007#include <cpu_func.h>
Inderpal Singh3260bc82014-01-08 09:19:57 +05308#include <usb.h>
Simon Glass37f11622014-10-20 19:48:37 -06009#include <asm/gpio.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053010#include <asm/arch/pinmux.h>
Inderpal Singh04bb7372013-08-21 10:38:57 +053011#include <asm/arch/dwmmc.h>
Chander Kashyap0d2f2772013-08-21 10:38:56 +053012#include <asm/arch/power.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
Inderpal Singh3260bc82014-01-08 09:19:57 +053016#ifdef CONFIG_USB_EHCI_EXYNOS
17int board_usb_init(int index, enum usb_init_type init)
18{
Inderpal Singh3260bc82014-01-08 09:19:57 +053019 /* Configure gpios for usb 3503 hub:
20 * disconnect, toggle reset and connect
21 */
Simon Glass4f83d3d2014-10-20 19:48:39 -060022 gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
23 gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053024 gpio_direction_output(EXYNOS5_GPIO_D17, 0);
25 gpio_direction_output(EXYNOS5_GPIO_X35, 0);
Inderpal Singh3260bc82014-01-08 09:19:57 +053026
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053027 gpio_direction_output(EXYNOS5_GPIO_X35, 1);
28 gpio_direction_output(EXYNOS5_GPIO_D17, 1);
Inderpal Singh3260bc82014-01-08 09:19:57 +053029
30 return 0;
31}
32#endif
33
Chander Kashyap0d2f2772013-08-21 10:38:56 +053034int board_init(void)
35{
36 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
37 return 0;
38}
39
40int dram_init(void)
41{
42 int i;
43 u32 addr;
44
45 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
46 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
47 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
48 }
49 return 0;
50}
51
52int power_init_board(void)
53{
54 set_ps_hold_ctrl();
55 return 0;
56}
57
Simon Glass2f949c32017-03-31 08:40:32 -060058int dram_init_banksize(void)
Chander Kashyap0d2f2772013-08-21 10:38:56 +053059{
60 int i;
61 u32 addr, size;
62
63 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
64 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
65 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
66
67 gd->bd->bi_dram[i].start = addr;
68 gd->bd->bi_dram[i].size = size;
69 }
Simon Glass2f949c32017-03-31 08:40:32 -060070
71 return 0;
Chander Kashyap0d2f2772013-08-21 10:38:56 +053072}
73
Masahiro Yamada0a780172017-05-09 20:31:39 +090074#ifdef CONFIG_MMC
Inderpal Singh04bb7372013-08-21 10:38:57 +053075int board_mmc_init(bd_t *bis)
76{
77 int ret;
78 /* dwmmc initializattion for available channels */
79 ret = exynos_dwmmc_init(gd->fdt_blob);
80 if (ret)
81 debug("dwmmc init failed\n");
82
83 return ret;
84}
85#endif
86
Chander Kashyap0d2f2772013-08-21 10:38:56 +053087static int board_uart_init(void)
88{
89 int err = 0, uart_id;
90
91 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
92 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
93 if (err) {
94 debug("UART%d not configured\n",
95 (uart_id - PERIPH_ID_UART0));
96 return err;
97 }
98 }
99 return err;
100}
101
102#ifdef CONFIG_BOARD_EARLY_INIT_F
103int board_early_init_f(void)
104{
105 int err;
106
107 err = board_uart_init();
108 if (err) {
109 debug("UART init failed\n");
110 return err;
111 }
112 return err;
113}
114#endif
115
116#ifdef CONFIG_DISPLAY_BOARDINFO
117int checkboard(void)
118{
119 printf("\nBoard: Arndale\n");
120
121 return 0;
122}
123#endif
Andre Przywara64d4c222014-08-01 13:35:44 +0200124
125#ifdef CONFIG_S5P_PA_SYSRAM
126void smp_set_core_boot_addr(unsigned long addr, int corenr)
127{
128 writel(addr, CONFIG_S5P_PA_SYSRAM);
129
130 /* make sure this write is really executed */
131 __asm__ volatile ("dsb\n");
132}
133#endif