Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Marek Vasut | bc0d3c8 | 2021-01-19 00:58:33 +0100 | [diff] [blame] | 7 | #include <clk.h> |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 10 | #include <malloc.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 11 | #include <spi.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 13 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 16 | #include <linux/errno.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 17 | #include <asm/io.h> |
Stefano Babic | 7faee91 | 2011-08-21 10:45:44 +0200 | [diff] [blame] | 18 | #include <asm/gpio.h> |
Stefano Babic | 78129d9 | 2011-03-14 15:43:56 +0100 | [diff] [blame] | 19 | #include <asm/arch/imx-regs.h> |
| 20 | #include <asm/arch/clock.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 21 | #include <asm/mach-imx/spi.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 22 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
Marek Vasut | eb68aa1 | 2021-01-19 00:58:32 +0100 | [diff] [blame] | 25 | /* MX35 and older is CSPI */ |
Tom Rini | eac76b8 | 2021-09-09 07:54:50 -0400 | [diff] [blame] | 26 | #if defined(CONFIG_MX31) |
Marek Vasut | eb68aa1 | 2021-01-19 00:58:32 +0100 | [diff] [blame] | 27 | #define MXC_CSPI |
| 28 | struct cspi_regs { |
| 29 | u32 rxdata; |
| 30 | u32 txdata; |
| 31 | u32 ctrl; |
| 32 | u32 intr; |
| 33 | u32 dma; |
| 34 | u32 stat; |
| 35 | u32 period; |
| 36 | u32 test; |
| 37 | }; |
| 38 | |
| 39 | #define MXC_CSPICTRL_EN BIT(0) |
| 40 | #define MXC_CSPICTRL_MODE BIT(1) |
| 41 | #define MXC_CSPICTRL_XCH BIT(2) |
| 42 | #define MXC_CSPICTRL_SMC BIT(3) |
| 43 | #define MXC_CSPICTRL_POL BIT(4) |
| 44 | #define MXC_CSPICTRL_PHA BIT(5) |
| 45 | #define MXC_CSPICTRL_SSCTL BIT(6) |
| 46 | #define MXC_CSPICTRL_SSPOL BIT(7) |
| 47 | #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) |
| 48 | #define MXC_CSPICTRL_RXOVF BIT(6) |
| 49 | #define MXC_CSPIPERIOD_32KHZ BIT(15) |
| 50 | #define MAX_SPI_BYTES 4 |
Marek Vasut | eb68aa1 | 2021-01-19 00:58:32 +0100 | [diff] [blame] | 51 | #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) |
| 52 | #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) |
| 53 | #define MXC_CSPICTRL_TC BIT(8) |
| 54 | #define MXC_CSPICTRL_MAXBITS 0x1f |
Marek Vasut | eb68aa1 | 2021-01-19 00:58:32 +0100 | [diff] [blame] | 55 | |
| 56 | #else /* MX51 and newer is ECSPI */ |
| 57 | #define MXC_ECSPI |
| 58 | struct cspi_regs { |
| 59 | u32 rxdata; |
| 60 | u32 txdata; |
| 61 | u32 ctrl; |
| 62 | u32 cfg; |
| 63 | u32 intr; |
| 64 | u32 dma; |
| 65 | u32 stat; |
| 66 | u32 period; |
| 67 | }; |
| 68 | |
| 69 | #define MXC_CSPICTRL_EN BIT(0) |
| 70 | #define MXC_CSPICTRL_MODE BIT(1) |
| 71 | #define MXC_CSPICTRL_XCH BIT(2) |
| 72 | #define MXC_CSPICTRL_MODE_MASK (0xf << 4) |
| 73 | #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) |
| 74 | #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) |
| 75 | #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) |
| 76 | #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) |
| 77 | #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) |
| 78 | #define MXC_CSPICTRL_MAXBITS 0xfff |
| 79 | #define MXC_CSPICTRL_TC BIT(7) |
| 80 | #define MXC_CSPICTRL_RXOVF BIT(6) |
| 81 | #define MXC_CSPIPERIOD_32KHZ BIT(15) |
| 82 | #define MAX_SPI_BYTES 32 |
| 83 | |
| 84 | /* Bit position inside CTRL register to be associated with SS */ |
| 85 | #define MXC_CSPICTRL_CHAN 18 |
| 86 | |
| 87 | /* Bit position inside CON register to be associated with SS */ |
| 88 | #define MXC_CSPICON_PHA 0 /* SCLK phase control */ |
| 89 | #define MXC_CSPICON_POL 4 /* SCLK polarity */ |
| 90 | #define MXC_CSPICON_SSPOL 12 /* SS polarity */ |
| 91 | #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ |
| 92 | #endif |
| 93 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 94 | __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| 95 | { |
| 96 | return -1; |
| 97 | } |
| 98 | |
Stefano Babic | d77fe99 | 2010-07-06 17:05:06 +0200 | [diff] [blame] | 99 | #define OUT MXC_GPIO_DIRECTION_OUT |
| 100 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 101 | #define reg_read readl |
| 102 | #define reg_write(a, v) writel(v, a) |
| 103 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 104 | #if !defined(CFG_SYS_SPI_MXC_WAIT) |
| 105 | #define CFG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 106 | #endif |
| 107 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 108 | #define MAX_CS_COUNT 4 |
| 109 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 110 | struct mxc_spi_slave { |
| 111 | struct spi_slave slave; |
| 112 | unsigned long base; |
| 113 | u32 ctrl_reg; |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 114 | #if defined(MXC_ECSPI) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 115 | u32 cfg_reg; |
| 116 | #endif |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 117 | int gpio; |
Stefano Babic | d77fe99 | 2010-07-06 17:05:06 +0200 | [diff] [blame] | 118 | int ss_pol; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 119 | unsigned int max_hz; |
| 120 | unsigned int mode; |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 121 | struct gpio_desc ss; |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 122 | struct gpio_desc cs_gpios[MAX_CS_COUNT]; |
| 123 | struct udevice *dev; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 124 | }; |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 125 | |
| 126 | static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) |
| 127 | { |
| 128 | return container_of(slave, struct mxc_spi_slave, slave); |
| 129 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 130 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 131 | static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 132 | { |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 133 | #if CONFIG_IS_ENABLED(DM_SPI) |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 134 | struct udevice *dev = mxcs->dev; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 135 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 136 | |
| 137 | u32 cs = slave_plat->cs; |
| 138 | |
| 139 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) |
| 140 | return; |
| 141 | |
| 142 | dm_gpio_set_value(&mxcs->cs_gpios[cs], 1); |
| 143 | #else |
| 144 | if (mxcs->gpio > 0) |
| 145 | gpio_set_value(mxcs->gpio, mxcs->ss_pol); |
| 146 | #endif |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 147 | } |
| 148 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 149 | static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 150 | { |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 151 | #if CONFIG_IS_ENABLED(DM_SPI) |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 152 | struct udevice *dev = mxcs->dev; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 153 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 154 | |
| 155 | u32 cs = slave_plat->cs; |
| 156 | |
| 157 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) |
| 158 | return; |
| 159 | |
| 160 | dm_gpio_set_value(&mxcs->cs_gpios[cs], 0); |
| 161 | #else |
| 162 | if (mxcs->gpio > 0) |
| 163 | gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); |
| 164 | #endif |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 165 | } |
| 166 | |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 167 | u32 get_cspi_div(u32 div) |
| 168 | { |
| 169 | int i; |
| 170 | |
| 171 | for (i = 0; i < 8; i++) { |
| 172 | if (div <= (4 << i)) |
| 173 | return i; |
| 174 | } |
| 175 | return i; |
| 176 | } |
| 177 | |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 178 | #ifdef MXC_CSPI |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 179 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 180 | { |
| 181 | unsigned int ctrl_reg; |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 182 | u32 clk_src; |
| 183 | u32 div; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 184 | unsigned int max_hz = mxcs->max_hz; |
| 185 | unsigned int mode = mxcs->mode; |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 186 | |
| 187 | clk_src = mxc_get_clock(MXC_CSPI_CLK); |
| 188 | |
Benoît Thébaudeau | 884622b | 2012-08-10 08:51:50 +0000 | [diff] [blame] | 189 | div = DIV_ROUND_UP(clk_src, max_hz); |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 190 | div = get_cspi_div(div); |
| 191 | |
| 192 | debug("clk %d Hz, div %d, real clk %d Hz\n", |
| 193 | max_hz, div, clk_src / (4 << div)); |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 194 | |
| 195 | ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | |
| 196 | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 197 | MXC_CSPICTRL_DATARATE(div) | |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 198 | MXC_CSPICTRL_EN | |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 199 | MXC_CSPICTRL_MODE; |
| 200 | |
| 201 | if (mode & SPI_CPHA) |
| 202 | ctrl_reg |= MXC_CSPICTRL_PHA; |
| 203 | if (mode & SPI_CPOL) |
| 204 | ctrl_reg |= MXC_CSPICTRL_POL; |
| 205 | if (mode & SPI_CS_HIGH) |
| 206 | ctrl_reg |= MXC_CSPICTRL_SSPOL; |
| 207 | mxcs->ctrl_reg = ctrl_reg; |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | #endif |
| 212 | |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 213 | #ifdef MXC_ECSPI |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 214 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 215 | { |
| 216 | u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 217 | s32 reg_ctrl, reg_config; |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 218 | u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; |
| 219 | u32 pre_div = 0, post_div = 0; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 220 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 221 | unsigned int max_hz = mxcs->max_hz; |
| 222 | unsigned int mode = mxcs->mode; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 223 | |
Fabio Estevam | 833fb55 | 2013-04-09 13:06:25 +0000 | [diff] [blame] | 224 | /* |
| 225 | * Reset SPI and set all CSs to master mode, if toggling |
| 226 | * between slave and master mode we might see a glitch |
| 227 | * on the clock line |
| 228 | */ |
| 229 | reg_ctrl = MXC_CSPICTRL_MODE_MASK; |
| 230 | reg_write(®s->ctrl, reg_ctrl); |
| 231 | reg_ctrl |= MXC_CSPICTRL_EN; |
| 232 | reg_write(®s->ctrl, reg_ctrl); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 233 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 234 | if (clk_src > max_hz) { |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 235 | pre_div = (clk_src - 1) / max_hz; |
| 236 | /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ |
| 237 | post_div = fls(pre_div); |
| 238 | if (post_div > 4) { |
| 239 | post_div -= 4; |
| 240 | if (post_div >= 16) { |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 241 | printf("Error: no divider for the freq: %d\n", |
| 242 | max_hz); |
| 243 | return -1; |
| 244 | } |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 245 | pre_div >>= post_div; |
| 246 | } else { |
| 247 | post_div = 0; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 248 | } |
| 249 | } |
| 250 | |
| 251 | debug("pre_div = %d, post_div=%d\n", pre_div, post_div); |
| 252 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | |
| 253 | MXC_CSPICTRL_SELCHAN(cs); |
| 254 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | |
| 255 | MXC_CSPICTRL_PREDIV(pre_div); |
| 256 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | |
| 257 | MXC_CSPICTRL_POSTDIV(post_div); |
| 258 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 259 | if (mode & SPI_CS_HIGH) |
| 260 | ss_pol = 1; |
| 261 | |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 262 | if (mode & SPI_CPOL) { |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 263 | sclkpol = 1; |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 264 | sclkctl = 1; |
| 265 | } |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 266 | |
| 267 | if (mode & SPI_CPHA) |
| 268 | sclkpha = 1; |
| 269 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 270 | reg_config = reg_read(®s->cfg); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 271 | |
| 272 | /* |
| 273 | * Configuration register setup |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 274 | * The MX51 supports different setup for each SS |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 275 | */ |
| 276 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | |
| 277 | (ss_pol << (cs + MXC_CSPICON_SSPOL)); |
| 278 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | |
| 279 | (sclkpol << (cs + MXC_CSPICON_POL)); |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 280 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | |
| 281 | (sclkctl << (cs + MXC_CSPICON_CTL)); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 282 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | |
| 283 | (sclkpha << (cs + MXC_CSPICON_PHA)); |
| 284 | |
| 285 | debug("reg_ctrl = 0x%x\n", reg_ctrl); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 286 | reg_write(®s->ctrl, reg_ctrl); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 287 | debug("reg_config = 0x%x\n", reg_config); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 288 | reg_write(®s->cfg, reg_config); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 289 | |
| 290 | /* save config register and control register */ |
| 291 | mxcs->ctrl_reg = reg_ctrl; |
| 292 | mxcs->cfg_reg = reg_config; |
| 293 | |
| 294 | /* clear interrupt reg */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 295 | reg_write(®s->intr, 0); |
| 296 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | #endif |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 301 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 302 | int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 303 | const u8 *dout, u8 *din, unsigned long flags) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 304 | { |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 305 | int nbytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 306 | u32 data, cnt, i; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 307 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 308 | u32 ts; |
| 309 | int status; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 310 | |
Ye Li | 07955fb | 2019-01-04 09:26:00 +0000 | [diff] [blame] | 311 | debug("%s: bitlen %d dout 0x%lx din 0x%lx\n", |
| 312 | __func__, bitlen, (ulong)dout, (ulong)din); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 313 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 314 | mxcs->ctrl_reg = (mxcs->ctrl_reg & |
| 315 | ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 316 | MXC_CSPICTRL_BITCOUNT(bitlen - 1); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 317 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 318 | reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 319 | #ifdef MXC_ECSPI |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 320 | reg_write(®s->cfg, mxcs->cfg_reg); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 321 | #endif |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 322 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 323 | /* Clear interrupt register */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 324 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 325 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 326 | /* |
| 327 | * The SPI controller works only with words, |
| 328 | * check if less than a word is sent. |
| 329 | * Access to the FIFO is only 32 bit |
| 330 | */ |
| 331 | if (bitlen % 32) { |
| 332 | data = 0; |
| 333 | cnt = (bitlen % 32) / 8; |
| 334 | if (dout) { |
| 335 | for (i = 0; i < cnt; i++) { |
| 336 | data = (data << 8) | (*dout++ & 0xFF); |
| 337 | } |
| 338 | } |
| 339 | debug("Sending SPI 0x%x\n", data); |
| 340 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 341 | reg_write(®s->txdata, data); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 342 | nbytes -= cnt; |
| 343 | } |
| 344 | |
| 345 | data = 0; |
| 346 | |
| 347 | while (nbytes > 0) { |
| 348 | data = 0; |
| 349 | if (dout) { |
| 350 | /* Buffer is not 32-bit aligned */ |
| 351 | if ((unsigned long)dout & 0x03) { |
| 352 | data = 0; |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 353 | for (i = 0; i < 4; i++) |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 354 | data = (data << 8) | (*dout++ & 0xFF); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 355 | } else { |
| 356 | data = *(u32 *)dout; |
| 357 | data = cpu_to_be32(data); |
Timo Herbrecher | 6420320 | 2013-10-16 00:05:09 +0530 | [diff] [blame] | 358 | dout += 4; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 359 | } |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 360 | } |
| 361 | debug("Sending SPI 0x%x\n", data); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 362 | reg_write(®s->txdata, data); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 363 | nbytes -= 4; |
| 364 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 365 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 366 | /* FIFO is written, now starts the transfer setting the XCH bit */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 367 | reg_write(®s->ctrl, mxcs->ctrl_reg | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 368 | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 369 | |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 370 | ts = get_timer(0); |
| 371 | status = reg_read(®s->stat); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 372 | /* Wait until the TC (Transfer completed) bit is set */ |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 373 | while ((status & MXC_CSPICTRL_TC) == 0) { |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 374 | if (get_timer(ts) > CFG_SYS_SPI_MXC_WAIT) { |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 375 | printf("spi_xchg_single: Timeout!\n"); |
| 376 | return -1; |
| 377 | } |
| 378 | status = reg_read(®s->stat); |
| 379 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 380 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 381 | /* Transfer completed, clear any pending request */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 382 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 383 | |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 384 | nbytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 385 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 386 | if (bitlen % 32) { |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 387 | data = reg_read(®s->rxdata); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 388 | cnt = (bitlen % 32) / 8; |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 389 | data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 390 | debug("SPI Rx unaligned: 0x%x\n", data); |
| 391 | if (din) { |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 392 | memcpy(din, &data, cnt); |
| 393 | din += cnt; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 394 | } |
| 395 | nbytes -= cnt; |
| 396 | } |
| 397 | |
| 398 | while (nbytes > 0) { |
| 399 | u32 tmp; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 400 | tmp = reg_read(®s->rxdata); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 401 | data = cpu_to_be32(tmp); |
| 402 | debug("SPI Rx: 0x%x 0x%x\n", tmp, data); |
Masahiro Yamada | db20464 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 403 | cnt = min_t(u32, nbytes, sizeof(data)); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 404 | if (din) { |
| 405 | memcpy(din, &data, cnt); |
| 406 | din += cnt; |
| 407 | } |
| 408 | nbytes -= cnt; |
| 409 | } |
| 410 | |
| 411 | return 0; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 412 | |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 413 | } |
| 414 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 415 | static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs, |
| 416 | unsigned int bitlen, const void *dout, |
| 417 | void *din, unsigned long flags) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 418 | { |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 419 | int n_bytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 420 | int n_bits; |
| 421 | int ret; |
| 422 | u32 blk_size; |
| 423 | u8 *p_outbuf = (u8 *)dout; |
| 424 | u8 *p_inbuf = (u8 *)din; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 425 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 426 | if (!mxcs) |
| 427 | return -EINVAL; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 428 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 429 | if (flags & SPI_XFER_BEGIN) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 430 | mxc_spi_cs_activate(mxcs); |
Magnus Lilja | 1858a9a | 2010-02-09 22:05:39 +0100 | [diff] [blame] | 431 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 432 | while (n_bytes > 0) { |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 433 | if (n_bytes < MAX_SPI_BYTES) |
| 434 | blk_size = n_bytes; |
| 435 | else |
| 436 | blk_size = MAX_SPI_BYTES; |
| 437 | |
| 438 | n_bits = blk_size * 8; |
| 439 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 440 | ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 441 | |
| 442 | if (ret) |
| 443 | return ret; |
| 444 | if (dout) |
| 445 | p_outbuf += blk_size; |
| 446 | if (din) |
| 447 | p_inbuf += blk_size; |
| 448 | n_bytes -= blk_size; |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 449 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 450 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 451 | if (flags & SPI_XFER_END) { |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 452 | mxc_spi_cs_deactivate(mxcs); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 453 | } |
| 454 | |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 455 | return 0; |
| 456 | } |
| 457 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 458 | static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs) |
| 459 | { |
| 460 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
| 461 | int ret; |
| 462 | |
| 463 | reg_write(®s->rxdata, 1); |
| 464 | udelay(1); |
| 465 | ret = spi_cfg_mxc(mxcs, cs); |
| 466 | if (ret) { |
| 467 | printf("mxc_spi: cannot setup SPI controller\n"); |
| 468 | return ret; |
| 469 | } |
| 470 | reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); |
| 471 | reg_write(®s->intr, 0); |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 476 | #if !CONFIG_IS_ENABLED(DM_SPI) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 477 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
| 478 | void *din, unsigned long flags) |
| 479 | { |
| 480 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 481 | |
| 482 | return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); |
| 483 | } |
| 484 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 485 | /* |
| 486 | * Some SPI devices require active chip-select over multiple |
| 487 | * transactions, we achieve this using a GPIO. Still, the SPI |
| 488 | * controller has to be configured to use one of its own chipselects. |
| 489 | * To use this feature you have to implement board_spi_cs_gpio() to assign |
| 490 | * a gpio value for each cs (-1 if cs doesn't need to use gpio). |
| 491 | * You must use some unused on this SPI controller cs between 0 and 3. |
| 492 | */ |
| 493 | static int setup_cs_gpio(struct mxc_spi_slave *mxcs, |
| 494 | unsigned int bus, unsigned int cs) |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 495 | { |
| 496 | int ret; |
| 497 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 498 | mxcs->gpio = board_spi_cs_gpio(bus, cs); |
| 499 | if (mxcs->gpio == -1) |
| 500 | return 0; |
| 501 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 502 | gpio_request(mxcs->gpio, "spi-cs"); |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 503 | ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); |
| 504 | if (ret) { |
| 505 | printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); |
| 506 | return -EINVAL; |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 507 | } |
| 508 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 509 | return 0; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 510 | } |
| 511 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 512 | static unsigned long spi_bases[] = { |
| 513 | MXC_SPI_BASE_ADDRESSES |
| 514 | }; |
| 515 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 516 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
| 517 | unsigned int max_hz, unsigned int mode) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 518 | { |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 519 | struct mxc_spi_slave *mxcs; |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 520 | int ret; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 521 | |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 522 | if (bus >= ARRAY_SIZE(spi_bases)) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 523 | return NULL; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 524 | |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 525 | if (max_hz == 0) { |
| 526 | printf("Error: desired clock is 0\n"); |
| 527 | return NULL; |
| 528 | } |
| 529 | |
Simon Glass | d034a95 | 2013-03-18 19:23:40 +0000 | [diff] [blame] | 530 | mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 531 | if (!mxcs) { |
| 532 | puts("mxc_spi: SPI Slave not allocated !\n"); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 533 | return NULL; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 534 | } |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 535 | |
Fabio Estevam | 17cd2a8 | 2012-11-15 11:23:23 +0000 | [diff] [blame] | 536 | mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; |
| 537 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 538 | ret = setup_cs_gpio(mxcs, bus, cs); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 539 | if (ret < 0) { |
| 540 | free(mxcs); |
| 541 | return NULL; |
| 542 | } |
| 543 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 544 | mxcs->base = spi_bases[bus]; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 545 | mxcs->max_hz = max_hz; |
| 546 | mxcs->mode = mode; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 547 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 548 | return &mxcs->slave; |
| 549 | } |
| 550 | |
| 551 | void spi_free_slave(struct spi_slave *slave) |
| 552 | { |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 553 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 554 | |
| 555 | free(mxcs); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 556 | } |
| 557 | |
| 558 | int spi_claim_bus(struct spi_slave *slave) |
| 559 | { |
| 560 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 561 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 562 | return mxc_spi_claim_bus_internal(mxcs, slave->cs); |
| 563 | } |
| 564 | |
| 565 | void spi_release_bus(struct spi_slave *slave) |
| 566 | { |
| 567 | /* TODO: Shut the controller down */ |
| 568 | } |
| 569 | #else |
| 570 | |
| 571 | static int mxc_spi_probe(struct udevice *bus) |
| 572 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 573 | struct mxc_spi_slave *mxcs = dev_get_plat(bus); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 574 | int ret; |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 575 | int i; |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 576 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 577 | ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios, |
| 578 | ARRAY_SIZE(mxcs->cs_gpios), 0); |
| 579 | if (ret < 0) { |
| 580 | pr_err("Can't get %s gpios! Error: %d", bus->name, ret); |
| 581 | return ret; |
| 582 | } |
| 583 | |
| 584 | for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) { |
| 585 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[i])) |
| 586 | continue; |
| 587 | |
| 588 | ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i], |
| 589 | GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); |
| 590 | if (ret) { |
| 591 | dev_err(bus, "Setting cs %d error\n", i); |
| 592 | return ret; |
| 593 | } |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 594 | } |
| 595 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 596 | mxcs->base = dev_read_addr(bus); |
Heiko Schocher | 6d49b4e | 2019-05-26 12:15:46 +0200 | [diff] [blame] | 597 | if (mxcs->base == FDT_ADDR_T_NONE) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 598 | return -ENODEV; |
| 599 | |
Marek Vasut | bc0d3c8 | 2021-01-19 00:58:33 +0100 | [diff] [blame] | 600 | #if CONFIG_IS_ENABLED(CLK) |
| 601 | struct clk clk; |
| 602 | ret = clk_get_by_index(bus, 0, &clk); |
| 603 | if (ret) |
| 604 | return ret; |
| 605 | |
| 606 | clk_enable(&clk); |
| 607 | |
| 608 | mxcs->max_hz = clk_get_rate(&clk); |
| 609 | #else |
Stefano Babic | 2fb2417 | 2021-07-10 16:31:29 +0200 | [diff] [blame] | 610 | int node = dev_of_offset(bus); |
| 611 | const void *blob = gd->fdt_blob; |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 612 | mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", |
| 613 | 20000000); |
Marek Vasut | bc0d3c8 | 2021-01-19 00:58:33 +0100 | [diff] [blame] | 614 | #endif |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 615 | |
| 616 | return 0; |
| 617 | } |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 618 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 619 | static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 620 | const void *dout, void *din, unsigned long flags) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 621 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 622 | struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 623 | |
| 624 | |
| 625 | return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); |
| 626 | } |
| 627 | |
| 628 | static int mxc_spi_claim_bus(struct udevice *dev) |
| 629 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 630 | struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 631 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 632 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 633 | mxcs->dev = dev; |
| 634 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 635 | return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 636 | } |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 637 | |
| 638 | static int mxc_spi_release_bus(struct udevice *dev) |
| 639 | { |
| 640 | return 0; |
| 641 | } |
| 642 | |
| 643 | static int mxc_spi_set_speed(struct udevice *bus, uint speed) |
| 644 | { |
Marek Vasut | 060ae38 | 2021-02-03 17:53:57 +0100 | [diff] [blame] | 645 | struct mxc_spi_slave *mxcs = dev_get_plat(bus); |
| 646 | |
| 647 | mxcs->max_hz = speed; |
| 648 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static int mxc_spi_set_mode(struct udevice *bus, uint mode) |
| 653 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 654 | struct mxc_spi_slave *mxcs = dev_get_plat(bus); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 655 | |
| 656 | mxcs->mode = mode; |
| 657 | mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; |
| 658 | |
| 659 | return 0; |
| 660 | } |
| 661 | |
| 662 | static const struct dm_spi_ops mxc_spi_ops = { |
| 663 | .claim_bus = mxc_spi_claim_bus, |
| 664 | .release_bus = mxc_spi_release_bus, |
| 665 | .xfer = mxc_spi_xfer, |
| 666 | .set_speed = mxc_spi_set_speed, |
| 667 | .set_mode = mxc_spi_set_mode, |
| 668 | }; |
| 669 | |
| 670 | static const struct udevice_id mxc_spi_ids[] = { |
| 671 | { .compatible = "fsl,imx51-ecspi" }, |
| 672 | { } |
| 673 | }; |
| 674 | |
| 675 | U_BOOT_DRIVER(mxc_spi) = { |
| 676 | .name = "mxc_spi", |
| 677 | .id = UCLASS_SPI, |
| 678 | .of_match = mxc_spi_ids, |
| 679 | .ops = &mxc_spi_ops, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 680 | .plat_auto = sizeof(struct mxc_spi_slave), |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 681 | .probe = mxc_spi_probe, |
| 682 | }; |
| 683 | #endif |