blob: 840660ffe9a346de537423c8108b8f3ea91c4b03 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +02002/*
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +02004 */
5
6#include <common.h>
Marek Vasutbc0d3c82021-01-19 00:58:33 +01007#include <clk.h>
Peng Fanea0bce62017-08-09 13:09:33 +08008#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Haavard Skinnemoend74084a2008-05-16 11:10:31 +020010#include <malloc.h>
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +020011#include <spi.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070013#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060015#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090016#include <linux/errno.h>
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +020017#include <asm/io.h>
Stefano Babic7faee912011-08-21 10:45:44 +020018#include <asm/gpio.h>
Stefano Babic78129d92011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
20#include <asm/arch/clock.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020021#include <asm/mach-imx/spi.h>
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +020022
Peng Fanea0bce62017-08-09 13:09:33 +080023DECLARE_GLOBAL_DATA_PTR;
24
Marek Vasuteb68aa12021-01-19 00:58:32 +010025/* MX35 and older is CSPI */
Tom Rinieac76b82021-09-09 07:54:50 -040026#if defined(CONFIG_MX31)
Marek Vasuteb68aa12021-01-19 00:58:32 +010027#define MXC_CSPI
28struct cspi_regs {
29 u32 rxdata;
30 u32 txdata;
31 u32 ctrl;
32 u32 intr;
33 u32 dma;
34 u32 stat;
35 u32 period;
36 u32 test;
37};
38
39#define MXC_CSPICTRL_EN BIT(0)
40#define MXC_CSPICTRL_MODE BIT(1)
41#define MXC_CSPICTRL_XCH BIT(2)
42#define MXC_CSPICTRL_SMC BIT(3)
43#define MXC_CSPICTRL_POL BIT(4)
44#define MXC_CSPICTRL_PHA BIT(5)
45#define MXC_CSPICTRL_SSCTL BIT(6)
46#define MXC_CSPICTRL_SSPOL BIT(7)
47#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
48#define MXC_CSPICTRL_RXOVF BIT(6)
49#define MXC_CSPIPERIOD_32KHZ BIT(15)
50#define MAX_SPI_BYTES 4
Marek Vasuteb68aa12021-01-19 00:58:32 +010051#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
52#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
53#define MXC_CSPICTRL_TC BIT(8)
54#define MXC_CSPICTRL_MAXBITS 0x1f
Marek Vasuteb68aa12021-01-19 00:58:32 +010055
56#else /* MX51 and newer is ECSPI */
57#define MXC_ECSPI
58struct cspi_regs {
59 u32 rxdata;
60 u32 txdata;
61 u32 ctrl;
62 u32 cfg;
63 u32 intr;
64 u32 dma;
65 u32 stat;
66 u32 period;
67};
68
69#define MXC_CSPICTRL_EN BIT(0)
70#define MXC_CSPICTRL_MODE BIT(1)
71#define MXC_CSPICTRL_XCH BIT(2)
72#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
73#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
74#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
75#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
76#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
77#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
78#define MXC_CSPICTRL_MAXBITS 0xfff
79#define MXC_CSPICTRL_TC BIT(7)
80#define MXC_CSPICTRL_RXOVF BIT(6)
81#define MXC_CSPIPERIOD_32KHZ BIT(15)
82#define MAX_SPI_BYTES 32
83
84/* Bit position inside CTRL register to be associated with SS */
85#define MXC_CSPICTRL_CHAN 18
86
87/* Bit position inside CON register to be associated with SS */
88#define MXC_CSPICON_PHA 0 /* SCLK phase control */
89#define MXC_CSPICON_POL 4 /* SCLK polarity */
90#define MXC_CSPICON_SSPOL 12 /* SS polarity */
91#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
92#endif
93
Nikita Kiryanov00cd7382014-08-20 15:08:50 +030094__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
95{
96 return -1;
97}
98
Stefano Babicd77fe992010-07-06 17:05:06 +020099#define OUT MXC_GPIO_DIRECTION_OUT
100
Stefano Babic28580452011-01-19 22:46:33 +0000101#define reg_read readl
102#define reg_write(a, v) writel(v, a)
103
Tom Rini364d0022023-01-10 11:19:45 -0500104#if !defined(CFG_SYS_SPI_MXC_WAIT)
105#define CFG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
Heiko Schocherb77c8882014-07-14 10:22:11 +0200106#endif
107
Heiko Schocher053c2442019-05-26 12:15:47 +0200108#define MAX_CS_COUNT 4
109
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200110struct mxc_spi_slave {
111 struct spi_slave slave;
112 unsigned long base;
113 u32 ctrl_reg;
Eric Nelsonfe1e7612012-01-31 07:52:03 +0000114#if defined(MXC_ECSPI)
Stefano Babic6e6f4552010-04-04 22:43:38 +0200115 u32 cfg_reg;
116#endif
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100117 int gpio;
Stefano Babicd77fe992010-07-06 17:05:06 +0200118 int ss_pol;
Markus Niebel8f769cf2014-10-23 16:09:39 +0200119 unsigned int max_hz;
120 unsigned int mode;
Peng Fanea0bce62017-08-09 13:09:33 +0800121 struct gpio_desc ss;
Heiko Schocher053c2442019-05-26 12:15:47 +0200122 struct gpio_desc cs_gpios[MAX_CS_COUNT];
123 struct udevice *dev;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200124};
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200125
126static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
127{
128 return container_of(slave, struct mxc_spi_slave, slave);
129}
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200130
Peng Fanea0bce62017-08-09 13:09:33 +0800131static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
Stefano Babic6e6f4552010-04-04 22:43:38 +0200132{
Lukasz Majewski76f442982020-06-04 23:11:53 +0800133#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher053c2442019-05-26 12:15:47 +0200134 struct udevice *dev = mxcs->dev;
Simon Glassb75b15b2020-12-03 16:55:23 -0700135 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Heiko Schocher053c2442019-05-26 12:15:47 +0200136
137 u32 cs = slave_plat->cs;
138
139 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
140 return;
141
142 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
143#else
144 if (mxcs->gpio > 0)
145 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
146#endif
Stefano Babic6e6f4552010-04-04 22:43:38 +0200147}
148
Peng Fanea0bce62017-08-09 13:09:33 +0800149static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
Stefano Babic6e6f4552010-04-04 22:43:38 +0200150{
Lukasz Majewski76f442982020-06-04 23:11:53 +0800151#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher053c2442019-05-26 12:15:47 +0200152 struct udevice *dev = mxcs->dev;
Simon Glassb75b15b2020-12-03 16:55:23 -0700153 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Heiko Schocher053c2442019-05-26 12:15:47 +0200154
155 u32 cs = slave_plat->cs;
156
157 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
158 return;
159
160 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
161#else
162 if (mxcs->gpio > 0)
163 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
164#endif
Stefano Babic6e6f4552010-04-04 22:43:38 +0200165}
166
Anatolij Gustschin0aa35fd2011-01-19 22:46:32 +0000167u32 get_cspi_div(u32 div)
168{
169 int i;
170
171 for (i = 0; i < 8; i++) {
172 if (div <= (4 << i))
173 return i;
174 }
175 return i;
176}
177
Eric Nelsonfe1e7612012-01-31 07:52:03 +0000178#ifdef MXC_CSPI
Markus Niebel8f769cf2014-10-23 16:09:39 +0200179static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicdcd73cd2011-01-19 22:46:30 +0000180{
181 unsigned int ctrl_reg;
Anatolij Gustschin0aa35fd2011-01-19 22:46:32 +0000182 u32 clk_src;
183 u32 div;
Markus Niebel8f769cf2014-10-23 16:09:39 +0200184 unsigned int max_hz = mxcs->max_hz;
185 unsigned int mode = mxcs->mode;
Anatolij Gustschin0aa35fd2011-01-19 22:46:32 +0000186
187 clk_src = mxc_get_clock(MXC_CSPI_CLK);
188
Benoît Thébaudeau884622b2012-08-10 08:51:50 +0000189 div = DIV_ROUND_UP(clk_src, max_hz);
Anatolij Gustschin0aa35fd2011-01-19 22:46:32 +0000190 div = get_cspi_div(div);
191
192 debug("clk %d Hz, div %d, real clk %d Hz\n",
193 max_hz, div, clk_src / (4 << div));
Stefano Babicdcd73cd2011-01-19 22:46:30 +0000194
195 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
196 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
Anatolij Gustschin0aa35fd2011-01-19 22:46:32 +0000197 MXC_CSPICTRL_DATARATE(div) |
Stefano Babicdcd73cd2011-01-19 22:46:30 +0000198 MXC_CSPICTRL_EN |
Stefano Babicdcd73cd2011-01-19 22:46:30 +0000199 MXC_CSPICTRL_MODE;
200
201 if (mode & SPI_CPHA)
202 ctrl_reg |= MXC_CSPICTRL_PHA;
203 if (mode & SPI_CPOL)
204 ctrl_reg |= MXC_CSPICTRL_POL;
205 if (mode & SPI_CS_HIGH)
206 ctrl_reg |= MXC_CSPICTRL_SSPOL;
207 mxcs->ctrl_reg = ctrl_reg;
208
209 return 0;
210}
211#endif
212
Eric Nelsonfe1e7612012-01-31 07:52:03 +0000213#ifdef MXC_ECSPI
Markus Niebel8f769cf2014-10-23 16:09:39 +0200214static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babic6e6f4552010-04-04 22:43:38 +0200215{
216 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
Dirk Behmeb177b712013-05-11 07:25:54 +0200217 s32 reg_ctrl, reg_config;
Markus Niebel6683e622014-02-17 17:33:17 +0100218 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
219 u32 pre_div = 0, post_div = 0;
Stefano Babic28580452011-01-19 22:46:33 +0000220 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Markus Niebel8f769cf2014-10-23 16:09:39 +0200221 unsigned int max_hz = mxcs->max_hz;
222 unsigned int mode = mxcs->mode;
Stefano Babic6e6f4552010-04-04 22:43:38 +0200223
Fabio Estevam833fb552013-04-09 13:06:25 +0000224 /*
225 * Reset SPI and set all CSs to master mode, if toggling
226 * between slave and master mode we might see a glitch
227 * on the clock line
228 */
229 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
230 reg_write(&regs->ctrl, reg_ctrl);
231 reg_ctrl |= MXC_CSPICTRL_EN;
232 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200233
Stefano Babic6e6f4552010-04-04 22:43:38 +0200234 if (clk_src > max_hz) {
Dirk Behmeb177b712013-05-11 07:25:54 +0200235 pre_div = (clk_src - 1) / max_hz;
236 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
237 post_div = fls(pre_div);
238 if (post_div > 4) {
239 post_div -= 4;
240 if (post_div >= 16) {
Stefano Babic6e6f4552010-04-04 22:43:38 +0200241 printf("Error: no divider for the freq: %d\n",
242 max_hz);
243 return -1;
244 }
Dirk Behmeb177b712013-05-11 07:25:54 +0200245 pre_div >>= post_div;
246 } else {
247 post_div = 0;
Stefano Babic6e6f4552010-04-04 22:43:38 +0200248 }
249 }
250
251 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
252 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
253 MXC_CSPICTRL_SELCHAN(cs);
254 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
255 MXC_CSPICTRL_PREDIV(pre_div);
256 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
257 MXC_CSPICTRL_POSTDIV(post_div);
258
Stefano Babic6e6f4552010-04-04 22:43:38 +0200259 if (mode & SPI_CS_HIGH)
260 ss_pol = 1;
261
Markus Niebel6683e622014-02-17 17:33:17 +0100262 if (mode & SPI_CPOL) {
Stefano Babic6e6f4552010-04-04 22:43:38 +0200263 sclkpol = 1;
Markus Niebel6683e622014-02-17 17:33:17 +0100264 sclkctl = 1;
265 }
Stefano Babic6e6f4552010-04-04 22:43:38 +0200266
267 if (mode & SPI_CPHA)
268 sclkpha = 1;
269
Stefano Babic28580452011-01-19 22:46:33 +0000270 reg_config = reg_read(&regs->cfg);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200271
272 /*
273 * Configuration register setup
Stefano Babicdcd73cd2011-01-19 22:46:30 +0000274 * The MX51 supports different setup for each SS
Stefano Babic6e6f4552010-04-04 22:43:38 +0200275 */
276 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
277 (ss_pol << (cs + MXC_CSPICON_SSPOL));
278 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
279 (sclkpol << (cs + MXC_CSPICON_POL));
Markus Niebel6683e622014-02-17 17:33:17 +0100280 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
281 (sclkctl << (cs + MXC_CSPICON_CTL));
Stefano Babic6e6f4552010-04-04 22:43:38 +0200282 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
283 (sclkpha << (cs + MXC_CSPICON_PHA));
284
285 debug("reg_ctrl = 0x%x\n", reg_ctrl);
Stefano Babic28580452011-01-19 22:46:33 +0000286 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200287 debug("reg_config = 0x%x\n", reg_config);
Stefano Babic28580452011-01-19 22:46:33 +0000288 reg_write(&regs->cfg, reg_config);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200289
290 /* save config register and control register */
291 mxcs->ctrl_reg = reg_ctrl;
292 mxcs->cfg_reg = reg_config;
293
294 /* clear interrupt reg */
Stefano Babic28580452011-01-19 22:46:33 +0000295 reg_write(&regs->intr, 0);
296 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200297
298 return 0;
299}
300#endif
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200301
Peng Fanea0bce62017-08-09 13:09:33 +0800302int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
Stefano Babic125f82a2010-08-20 12:05:03 +0200303 const u8 *dout, u8 *din, unsigned long flags)
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200304{
Axel Linfb7def92013-06-14 21:13:32 +0800305 int nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic125f82a2010-08-20 12:05:03 +0200306 u32 data, cnt, i;
Stefano Babic28580452011-01-19 22:46:33 +0000307 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Heiko Schocherb77c8882014-07-14 10:22:11 +0200308 u32 ts;
309 int status;
Stefano Babic6e6f4552010-04-04 22:43:38 +0200310
Ye Li07955fb2019-01-04 09:26:00 +0000311 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
312 __func__, bitlen, (ulong)dout, (ulong)din);
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200313
Stefano Babic6e6f4552010-04-04 22:43:38 +0200314 mxcs->ctrl_reg = (mxcs->ctrl_reg &
315 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
Guennadi Liakhovetskid3380132009-02-07 00:09:12 +0100316 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200317
Stefano Babic28580452011-01-19 22:46:33 +0000318 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
Eric Nelsonfe1e7612012-01-31 07:52:03 +0000319#ifdef MXC_ECSPI
Stefano Babic28580452011-01-19 22:46:33 +0000320 reg_write(&regs->cfg, mxcs->cfg_reg);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200321#endif
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200322
Stefano Babic6e6f4552010-04-04 22:43:38 +0200323 /* Clear interrupt register */
Stefano Babic28580452011-01-19 22:46:33 +0000324 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100325
Stefano Babic125f82a2010-08-20 12:05:03 +0200326 /*
327 * The SPI controller works only with words,
328 * check if less than a word is sent.
329 * Access to the FIFO is only 32 bit
330 */
331 if (bitlen % 32) {
332 data = 0;
333 cnt = (bitlen % 32) / 8;
334 if (dout) {
335 for (i = 0; i < cnt; i++) {
336 data = (data << 8) | (*dout++ & 0xFF);
337 }
338 }
339 debug("Sending SPI 0x%x\n", data);
340
Stefano Babic28580452011-01-19 22:46:33 +0000341 reg_write(&regs->txdata, data);
Stefano Babic125f82a2010-08-20 12:05:03 +0200342 nbytes -= cnt;
343 }
344
345 data = 0;
346
347 while (nbytes > 0) {
348 data = 0;
349 if (dout) {
350 /* Buffer is not 32-bit aligned */
351 if ((unsigned long)dout & 0x03) {
352 data = 0;
Anatolij Gustschin089ebe02011-01-20 07:53:06 +0000353 for (i = 0; i < 4; i++)
Stefano Babic125f82a2010-08-20 12:05:03 +0200354 data = (data << 8) | (*dout++ & 0xFF);
Stefano Babic125f82a2010-08-20 12:05:03 +0200355 } else {
356 data = *(u32 *)dout;
357 data = cpu_to_be32(data);
Timo Herbrecher64203202013-10-16 00:05:09 +0530358 dout += 4;
Stefano Babic125f82a2010-08-20 12:05:03 +0200359 }
Stefano Babic125f82a2010-08-20 12:05:03 +0200360 }
361 debug("Sending SPI 0x%x\n", data);
Stefano Babic28580452011-01-19 22:46:33 +0000362 reg_write(&regs->txdata, data);
Stefano Babic125f82a2010-08-20 12:05:03 +0200363 nbytes -= 4;
364 }
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200365
Stefano Babic6e6f4552010-04-04 22:43:38 +0200366 /* FIFO is written, now starts the transfer setting the XCH bit */
Stefano Babic28580452011-01-19 22:46:33 +0000367 reg_write(&regs->ctrl, mxcs->ctrl_reg |
Stefano Babic6e6f4552010-04-04 22:43:38 +0200368 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200369
Heiko Schocherb77c8882014-07-14 10:22:11 +0200370 ts = get_timer(0);
371 status = reg_read(&regs->stat);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200372 /* Wait until the TC (Transfer completed) bit is set */
Heiko Schocherb77c8882014-07-14 10:22:11 +0200373 while ((status & MXC_CSPICTRL_TC) == 0) {
Tom Rini364d0022023-01-10 11:19:45 -0500374 if (get_timer(ts) > CFG_SYS_SPI_MXC_WAIT) {
Heiko Schocherb77c8882014-07-14 10:22:11 +0200375 printf("spi_xchg_single: Timeout!\n");
376 return -1;
377 }
378 status = reg_read(&regs->stat);
379 }
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200380
Stefano Babic6e6f4552010-04-04 22:43:38 +0200381 /* Transfer completed, clear any pending request */
Stefano Babic28580452011-01-19 22:46:33 +0000382 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200383
Axel Linfb7def92013-06-14 21:13:32 +0800384 nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic6e6f4552010-04-04 22:43:38 +0200385
Stefano Babic125f82a2010-08-20 12:05:03 +0200386 if (bitlen % 32) {
Stefano Babic28580452011-01-19 22:46:33 +0000387 data = reg_read(&regs->rxdata);
Stefano Babic125f82a2010-08-20 12:05:03 +0200388 cnt = (bitlen % 32) / 8;
Anatolij Gustschin089ebe02011-01-20 07:53:06 +0000389 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
Stefano Babic125f82a2010-08-20 12:05:03 +0200390 debug("SPI Rx unaligned: 0x%x\n", data);
391 if (din) {
Anatolij Gustschin089ebe02011-01-20 07:53:06 +0000392 memcpy(din, &data, cnt);
393 din += cnt;
Stefano Babic125f82a2010-08-20 12:05:03 +0200394 }
395 nbytes -= cnt;
396 }
397
398 while (nbytes > 0) {
399 u32 tmp;
Stefano Babic28580452011-01-19 22:46:33 +0000400 tmp = reg_read(&regs->rxdata);
Stefano Babic125f82a2010-08-20 12:05:03 +0200401 data = cpu_to_be32(tmp);
402 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
Masahiro Yamadadb204642014-11-07 03:03:31 +0900403 cnt = min_t(u32, nbytes, sizeof(data));
Stefano Babic125f82a2010-08-20 12:05:03 +0200404 if (din) {
405 memcpy(din, &data, cnt);
406 din += cnt;
407 }
408 nbytes -= cnt;
409 }
410
411 return 0;
Stefano Babic6e6f4552010-04-04 22:43:38 +0200412
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200413}
414
Peng Fanea0bce62017-08-09 13:09:33 +0800415static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
416 unsigned int bitlen, const void *dout,
417 void *din, unsigned long flags)
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200418{
Axel Linfb7def92013-06-14 21:13:32 +0800419 int n_bytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic125f82a2010-08-20 12:05:03 +0200420 int n_bits;
421 int ret;
422 u32 blk_size;
423 u8 *p_outbuf = (u8 *)dout;
424 u8 *p_inbuf = (u8 *)din;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200425
Peng Fanea0bce62017-08-09 13:09:33 +0800426 if (!mxcs)
427 return -EINVAL;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200428
Stefano Babic125f82a2010-08-20 12:05:03 +0200429 if (flags & SPI_XFER_BEGIN)
Peng Fanea0bce62017-08-09 13:09:33 +0800430 mxc_spi_cs_activate(mxcs);
Magnus Lilja1858a9a2010-02-09 22:05:39 +0100431
Stefano Babic125f82a2010-08-20 12:05:03 +0200432 while (n_bytes > 0) {
Stefano Babic125f82a2010-08-20 12:05:03 +0200433 if (n_bytes < MAX_SPI_BYTES)
434 blk_size = n_bytes;
435 else
436 blk_size = MAX_SPI_BYTES;
437
438 n_bits = blk_size * 8;
439
Peng Fanea0bce62017-08-09 13:09:33 +0800440 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
Stefano Babic125f82a2010-08-20 12:05:03 +0200441
442 if (ret)
443 return ret;
444 if (dout)
445 p_outbuf += blk_size;
446 if (din)
447 p_inbuf += blk_size;
448 n_bytes -= blk_size;
Guennadi Liakhovetskid3380132009-02-07 00:09:12 +0100449 }
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200450
Stefano Babic125f82a2010-08-20 12:05:03 +0200451 if (flags & SPI_XFER_END) {
Peng Fanea0bce62017-08-09 13:09:33 +0800452 mxc_spi_cs_deactivate(mxcs);
Stefano Babic125f82a2010-08-20 12:05:03 +0200453 }
454
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200455 return 0;
456}
457
Peng Fanea0bce62017-08-09 13:09:33 +0800458static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
459{
460 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
461 int ret;
462
463 reg_write(&regs->rxdata, 1);
464 udelay(1);
465 ret = spi_cfg_mxc(mxcs, cs);
466 if (ret) {
467 printf("mxc_spi: cannot setup SPI controller\n");
468 return ret;
469 }
470 reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
471 reg_write(&regs->intr, 0);
472
473 return 0;
474}
475
Lukasz Majewski76f442982020-06-04 23:11:53 +0800476#if !CONFIG_IS_ENABLED(DM_SPI)
Peng Fanea0bce62017-08-09 13:09:33 +0800477int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
478 void *din, unsigned long flags)
479{
480 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
481
482 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
483}
484
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300485/*
486 * Some SPI devices require active chip-select over multiple
487 * transactions, we achieve this using a GPIO. Still, the SPI
488 * controller has to be configured to use one of its own chipselects.
489 * To use this feature you have to implement board_spi_cs_gpio() to assign
490 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
491 * You must use some unused on this SPI controller cs between 0 and 3.
492 */
493static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
494 unsigned int bus, unsigned int cs)
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100495{
496 int ret;
497
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300498 mxcs->gpio = board_spi_cs_gpio(bus, cs);
499 if (mxcs->gpio == -1)
500 return 0;
501
Peng Fanea0bce62017-08-09 13:09:33 +0800502 gpio_request(mxcs->gpio, "spi-cs");
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300503 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
504 if (ret) {
505 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
506 return -EINVAL;
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100507 }
508
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300509 return 0;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200510}
511
Peng Fanea0bce62017-08-09 13:09:33 +0800512static unsigned long spi_bases[] = {
513 MXC_SPI_BASE_ADDRESSES
514};
515
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200516struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
517 unsigned int max_hz, unsigned int mode)
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200518{
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200519 struct mxc_spi_slave *mxcs;
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100520 int ret;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200521
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100522 if (bus >= ARRAY_SIZE(spi_bases))
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200523 return NULL;
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200524
Markus Niebel8f769cf2014-10-23 16:09:39 +0200525 if (max_hz == 0) {
526 printf("Error: desired clock is 0\n");
527 return NULL;
528 }
529
Simon Glassd034a952013-03-18 19:23:40 +0000530 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
Stefano Babic125f82a2010-08-20 12:05:03 +0200531 if (!mxcs) {
532 puts("mxc_spi: SPI Slave not allocated !\n");
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100533 return NULL;
Stefano Babic125f82a2010-08-20 12:05:03 +0200534 }
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100535
Fabio Estevam17cd2a82012-11-15 11:23:23 +0000536 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
537
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300538 ret = setup_cs_gpio(mxcs, bus, cs);
Guennadi Liakhovetski9a88d702009-02-13 09:26:40 +0100539 if (ret < 0) {
540 free(mxcs);
541 return NULL;
542 }
543
Stefano Babic6e6f4552010-04-04 22:43:38 +0200544 mxcs->base = spi_bases[bus];
Markus Niebel8f769cf2014-10-23 16:09:39 +0200545 mxcs->max_hz = max_hz;
546 mxcs->mode = mode;
Stefano Babic6e6f4552010-04-04 22:43:38 +0200547
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200548 return &mxcs->slave;
549}
550
551void spi_free_slave(struct spi_slave *slave)
552{
Guennadi Liakhovetskid3380132009-02-07 00:09:12 +0100553 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
554
555 free(mxcs);
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200556}
557
558int spi_claim_bus(struct spi_slave *slave)
559{
560 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
561
Peng Fanea0bce62017-08-09 13:09:33 +0800562 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
563}
564
565void spi_release_bus(struct spi_slave *slave)
566{
567 /* TODO: Shut the controller down */
568}
569#else
570
571static int mxc_spi_probe(struct udevice *bus)
572{
Simon Glassfa20e932020-12-03 16:55:20 -0700573 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
Peng Fanea0bce62017-08-09 13:09:33 +0800574 int ret;
Heiko Schocher053c2442019-05-26 12:15:47 +0200575 int i;
Peng Fanea0bce62017-08-09 13:09:33 +0800576
Heiko Schocher053c2442019-05-26 12:15:47 +0200577 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
578 ARRAY_SIZE(mxcs->cs_gpios), 0);
579 if (ret < 0) {
580 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
581 return ret;
582 }
583
584 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
585 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
586 continue;
587
588 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
589 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
590 if (ret) {
591 dev_err(bus, "Setting cs %d error\n", i);
592 return ret;
593 }
Peng Fanea0bce62017-08-09 13:09:33 +0800594 }
595
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900596 mxcs->base = dev_read_addr(bus);
Heiko Schocher6d49b4e2019-05-26 12:15:46 +0200597 if (mxcs->base == FDT_ADDR_T_NONE)
Peng Fanea0bce62017-08-09 13:09:33 +0800598 return -ENODEV;
599
Marek Vasutbc0d3c82021-01-19 00:58:33 +0100600#if CONFIG_IS_ENABLED(CLK)
601 struct clk clk;
602 ret = clk_get_by_index(bus, 0, &clk);
603 if (ret)
604 return ret;
605
606 clk_enable(&clk);
607
608 mxcs->max_hz = clk_get_rate(&clk);
609#else
Stefano Babic2fb24172021-07-10 16:31:29 +0200610 int node = dev_of_offset(bus);
611 const void *blob = gd->fdt_blob;
Peng Fanea0bce62017-08-09 13:09:33 +0800612 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
613 20000000);
Marek Vasutbc0d3c82021-01-19 00:58:33 +0100614#endif
Guennadi Liakhovetski07327a52008-04-15 14:14:25 +0200615
616 return 0;
617}
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200618
Peng Fanea0bce62017-08-09 13:09:33 +0800619static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
620 const void *dout, void *din, unsigned long flags)
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200621{
Simon Glassfa20e932020-12-03 16:55:20 -0700622 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
Peng Fanea0bce62017-08-09 13:09:33 +0800623
624
625 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
626}
627
628static int mxc_spi_claim_bus(struct udevice *dev)
629{
Simon Glassfa20e932020-12-03 16:55:20 -0700630 struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent);
Simon Glassb75b15b2020-12-03 16:55:23 -0700631 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Peng Fanea0bce62017-08-09 13:09:33 +0800632
Heiko Schocher053c2442019-05-26 12:15:47 +0200633 mxcs->dev = dev;
634
Peng Fanea0bce62017-08-09 13:09:33 +0800635 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200636}
Peng Fanea0bce62017-08-09 13:09:33 +0800637
638static int mxc_spi_release_bus(struct udevice *dev)
639{
640 return 0;
641}
642
643static int mxc_spi_set_speed(struct udevice *bus, uint speed)
644{
Marek Vasut060ae382021-02-03 17:53:57 +0100645 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
646
647 mxcs->max_hz = speed;
648
Peng Fanea0bce62017-08-09 13:09:33 +0800649 return 0;
650}
651
652static int mxc_spi_set_mode(struct udevice *bus, uint mode)
653{
Simon Glassfa20e932020-12-03 16:55:20 -0700654 struct mxc_spi_slave *mxcs = dev_get_plat(bus);
Peng Fanea0bce62017-08-09 13:09:33 +0800655
656 mxcs->mode = mode;
657 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
658
659 return 0;
660}
661
662static const struct dm_spi_ops mxc_spi_ops = {
663 .claim_bus = mxc_spi_claim_bus,
664 .release_bus = mxc_spi_release_bus,
665 .xfer = mxc_spi_xfer,
666 .set_speed = mxc_spi_set_speed,
667 .set_mode = mxc_spi_set_mode,
668};
669
670static const struct udevice_id mxc_spi_ids[] = {
671 { .compatible = "fsl,imx51-ecspi" },
672 { }
673};
674
675U_BOOT_DRIVER(mxc_spi) = {
676 .name = "mxc_spi",
677 .id = UCLASS_SPI,
678 .of_match = mxc_spi_ids,
679 .ops = &mxc_spi_ops,
Simon Glass71fa5b42020-12-03 16:55:18 -0700680 .plat_auto = sizeof(struct mxc_spi_slave),
Peng Fanea0bce62017-08-09 13:09:33 +0800681 .probe = mxc_spi_probe,
682};
683#endif