Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 7 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 9 | #include <malloc.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 10 | #include <spi.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 11 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 12 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 14 | #include <linux/errno.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 15 | #include <asm/io.h> |
Stefano Babic | 7faee91 | 2011-08-21 10:45:44 +0200 | [diff] [blame] | 16 | #include <asm/gpio.h> |
Stefano Babic | 78129d9 | 2011-03-14 15:43:56 +0100 | [diff] [blame] | 17 | #include <asm/arch/imx-regs.h> |
| 18 | #include <asm/arch/clock.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 19 | #include <asm/mach-imx/spi.h> |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 20 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 23 | #ifdef CONFIG_MX27 |
| 24 | /* i.MX27 has a completely wrong register layout and register definitions in the |
| 25 | * datasheet, the correct one is in the Freescale's Linux driver */ |
| 26 | |
Helmut Raiger | 785efc9 | 2011-06-15 01:45:45 +0000 | [diff] [blame] | 27 | #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 28 | "See linux mxc_spi driver from Freescale for details." |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 29 | #endif |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 30 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 31 | __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| 32 | { |
| 33 | return -1; |
| 34 | } |
| 35 | |
Stefano Babic | d77fe99 | 2010-07-06 17:05:06 +0200 | [diff] [blame] | 36 | #define OUT MXC_GPIO_DIRECTION_OUT |
| 37 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 38 | #define reg_read readl |
| 39 | #define reg_write(a, v) writel(v, a) |
| 40 | |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 41 | #if !defined(CONFIG_SYS_SPI_MXC_WAIT) |
| 42 | #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ |
| 43 | #endif |
| 44 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 45 | #define MAX_CS_COUNT 4 |
| 46 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 47 | struct mxc_spi_slave { |
| 48 | struct spi_slave slave; |
| 49 | unsigned long base; |
| 50 | u32 ctrl_reg; |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 51 | #if defined(MXC_ECSPI) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 52 | u32 cfg_reg; |
| 53 | #endif |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 54 | int gpio; |
Stefano Babic | d77fe99 | 2010-07-06 17:05:06 +0200 | [diff] [blame] | 55 | int ss_pol; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 56 | unsigned int max_hz; |
| 57 | unsigned int mode; |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 58 | struct gpio_desc ss; |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 59 | struct gpio_desc cs_gpios[MAX_CS_COUNT]; |
| 60 | struct udevice *dev; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 61 | }; |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 62 | |
| 63 | static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) |
| 64 | { |
| 65 | return container_of(slave, struct mxc_spi_slave, slave); |
| 66 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 67 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 68 | static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 69 | { |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 70 | #if CONFIG_IS_ENABLED(DM_SPI) |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 71 | struct udevice *dev = mxcs->dev; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 72 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 73 | |
| 74 | u32 cs = slave_plat->cs; |
| 75 | |
| 76 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) |
| 77 | return; |
| 78 | |
| 79 | dm_gpio_set_value(&mxcs->cs_gpios[cs], 1); |
| 80 | #else |
| 81 | if (mxcs->gpio > 0) |
| 82 | gpio_set_value(mxcs->gpio, mxcs->ss_pol); |
| 83 | #endif |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 84 | } |
| 85 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 86 | static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 87 | { |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 88 | #if CONFIG_IS_ENABLED(DM_SPI) |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 89 | struct udevice *dev = mxcs->dev; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 90 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 91 | |
| 92 | u32 cs = slave_plat->cs; |
| 93 | |
| 94 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs])) |
| 95 | return; |
| 96 | |
| 97 | dm_gpio_set_value(&mxcs->cs_gpios[cs], 0); |
| 98 | #else |
| 99 | if (mxcs->gpio > 0) |
| 100 | gpio_set_value(mxcs->gpio, !(mxcs->ss_pol)); |
| 101 | #endif |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 102 | } |
| 103 | |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 104 | u32 get_cspi_div(u32 div) |
| 105 | { |
| 106 | int i; |
| 107 | |
| 108 | for (i = 0; i < 8; i++) { |
| 109 | if (div <= (4 << i)) |
| 110 | return i; |
| 111 | } |
| 112 | return i; |
| 113 | } |
| 114 | |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 115 | #ifdef MXC_CSPI |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 116 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 117 | { |
| 118 | unsigned int ctrl_reg; |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 119 | u32 clk_src; |
| 120 | u32 div; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 121 | unsigned int max_hz = mxcs->max_hz; |
| 122 | unsigned int mode = mxcs->mode; |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 123 | |
| 124 | clk_src = mxc_get_clock(MXC_CSPI_CLK); |
| 125 | |
Benoît Thébaudeau | 884622b | 2012-08-10 08:51:50 +0000 | [diff] [blame] | 126 | div = DIV_ROUND_UP(clk_src, max_hz); |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 127 | div = get_cspi_div(div); |
| 128 | |
| 129 | debug("clk %d Hz, div %d, real clk %d Hz\n", |
| 130 | max_hz, div, clk_src / (4 << div)); |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 131 | |
| 132 | ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | |
| 133 | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | |
Anatolij Gustschin | 0aa35fd | 2011-01-19 22:46:32 +0000 | [diff] [blame] | 134 | MXC_CSPICTRL_DATARATE(div) | |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 135 | MXC_CSPICTRL_EN | |
| 136 | #ifdef CONFIG_MX35 |
| 137 | MXC_CSPICTRL_SSCTL | |
| 138 | #endif |
| 139 | MXC_CSPICTRL_MODE; |
| 140 | |
| 141 | if (mode & SPI_CPHA) |
| 142 | ctrl_reg |= MXC_CSPICTRL_PHA; |
| 143 | if (mode & SPI_CPOL) |
| 144 | ctrl_reg |= MXC_CSPICTRL_POL; |
| 145 | if (mode & SPI_CS_HIGH) |
| 146 | ctrl_reg |= MXC_CSPICTRL_SSPOL; |
| 147 | mxcs->ctrl_reg = ctrl_reg; |
| 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | #endif |
| 152 | |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 153 | #ifdef MXC_ECSPI |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 154 | static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 155 | { |
| 156 | u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 157 | s32 reg_ctrl, reg_config; |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 158 | u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; |
| 159 | u32 pre_div = 0, post_div = 0; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 160 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 161 | unsigned int max_hz = mxcs->max_hz; |
| 162 | unsigned int mode = mxcs->mode; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 163 | |
Fabio Estevam | 833fb55 | 2013-04-09 13:06:25 +0000 | [diff] [blame] | 164 | /* |
| 165 | * Reset SPI and set all CSs to master mode, if toggling |
| 166 | * between slave and master mode we might see a glitch |
| 167 | * on the clock line |
| 168 | */ |
| 169 | reg_ctrl = MXC_CSPICTRL_MODE_MASK; |
| 170 | reg_write(®s->ctrl, reg_ctrl); |
| 171 | reg_ctrl |= MXC_CSPICTRL_EN; |
| 172 | reg_write(®s->ctrl, reg_ctrl); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 173 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 174 | if (clk_src > max_hz) { |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 175 | pre_div = (clk_src - 1) / max_hz; |
| 176 | /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ |
| 177 | post_div = fls(pre_div); |
| 178 | if (post_div > 4) { |
| 179 | post_div -= 4; |
| 180 | if (post_div >= 16) { |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 181 | printf("Error: no divider for the freq: %d\n", |
| 182 | max_hz); |
| 183 | return -1; |
| 184 | } |
Dirk Behme | b177b71 | 2013-05-11 07:25:54 +0200 | [diff] [blame] | 185 | pre_div >>= post_div; |
| 186 | } else { |
| 187 | post_div = 0; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 188 | } |
| 189 | } |
| 190 | |
| 191 | debug("pre_div = %d, post_div=%d\n", pre_div, post_div); |
| 192 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | |
| 193 | MXC_CSPICTRL_SELCHAN(cs); |
| 194 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | |
| 195 | MXC_CSPICTRL_PREDIV(pre_div); |
| 196 | reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | |
| 197 | MXC_CSPICTRL_POSTDIV(post_div); |
| 198 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 199 | if (mode & SPI_CS_HIGH) |
| 200 | ss_pol = 1; |
| 201 | |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 202 | if (mode & SPI_CPOL) { |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 203 | sclkpol = 1; |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 204 | sclkctl = 1; |
| 205 | } |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 206 | |
| 207 | if (mode & SPI_CPHA) |
| 208 | sclkpha = 1; |
| 209 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 210 | reg_config = reg_read(®s->cfg); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 211 | |
| 212 | /* |
| 213 | * Configuration register setup |
Stefano Babic | dcd73cd | 2011-01-19 22:46:30 +0000 | [diff] [blame] | 214 | * The MX51 supports different setup for each SS |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 215 | */ |
| 216 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | |
| 217 | (ss_pol << (cs + MXC_CSPICON_SSPOL)); |
| 218 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | |
| 219 | (sclkpol << (cs + MXC_CSPICON_POL)); |
Markus Niebel | 6683e62 | 2014-02-17 17:33:17 +0100 | [diff] [blame] | 220 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | |
| 221 | (sclkctl << (cs + MXC_CSPICON_CTL)); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 222 | reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | |
| 223 | (sclkpha << (cs + MXC_CSPICON_PHA)); |
| 224 | |
| 225 | debug("reg_ctrl = 0x%x\n", reg_ctrl); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 226 | reg_write(®s->ctrl, reg_ctrl); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 227 | debug("reg_config = 0x%x\n", reg_config); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 228 | reg_write(®s->cfg, reg_config); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 229 | |
| 230 | /* save config register and control register */ |
| 231 | mxcs->ctrl_reg = reg_ctrl; |
| 232 | mxcs->cfg_reg = reg_config; |
| 233 | |
| 234 | /* clear interrupt reg */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 235 | reg_write(®s->intr, 0); |
| 236 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | #endif |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 241 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 242 | int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen, |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 243 | const u8 *dout, u8 *din, unsigned long flags) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 244 | { |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 245 | int nbytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 246 | u32 data, cnt, i; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 247 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 248 | u32 ts; |
| 249 | int status; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 250 | |
Ye Li | 07955fb | 2019-01-04 09:26:00 +0000 | [diff] [blame] | 251 | debug("%s: bitlen %d dout 0x%lx din 0x%lx\n", |
| 252 | __func__, bitlen, (ulong)dout, (ulong)din); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 253 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 254 | mxcs->ctrl_reg = (mxcs->ctrl_reg & |
| 255 | ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 256 | MXC_CSPICTRL_BITCOUNT(bitlen - 1); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 257 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 258 | reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); |
Eric Nelson | fe1e761 | 2012-01-31 07:52:03 +0000 | [diff] [blame] | 259 | #ifdef MXC_ECSPI |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 260 | reg_write(®s->cfg, mxcs->cfg_reg); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 261 | #endif |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 262 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 263 | /* Clear interrupt register */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 264 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 265 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 266 | /* |
| 267 | * The SPI controller works only with words, |
| 268 | * check if less than a word is sent. |
| 269 | * Access to the FIFO is only 32 bit |
| 270 | */ |
| 271 | if (bitlen % 32) { |
| 272 | data = 0; |
| 273 | cnt = (bitlen % 32) / 8; |
| 274 | if (dout) { |
| 275 | for (i = 0; i < cnt; i++) { |
| 276 | data = (data << 8) | (*dout++ & 0xFF); |
| 277 | } |
| 278 | } |
| 279 | debug("Sending SPI 0x%x\n", data); |
| 280 | |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 281 | reg_write(®s->txdata, data); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 282 | nbytes -= cnt; |
| 283 | } |
| 284 | |
| 285 | data = 0; |
| 286 | |
| 287 | while (nbytes > 0) { |
| 288 | data = 0; |
| 289 | if (dout) { |
| 290 | /* Buffer is not 32-bit aligned */ |
| 291 | if ((unsigned long)dout & 0x03) { |
| 292 | data = 0; |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 293 | for (i = 0; i < 4; i++) |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 294 | data = (data << 8) | (*dout++ & 0xFF); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 295 | } else { |
| 296 | data = *(u32 *)dout; |
| 297 | data = cpu_to_be32(data); |
Timo Herbrecher | 6420320 | 2013-10-16 00:05:09 +0530 | [diff] [blame] | 298 | dout += 4; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 299 | } |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 300 | } |
| 301 | debug("Sending SPI 0x%x\n", data); |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 302 | reg_write(®s->txdata, data); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 303 | nbytes -= 4; |
| 304 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 305 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 306 | /* FIFO is written, now starts the transfer setting the XCH bit */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 307 | reg_write(®s->ctrl, mxcs->ctrl_reg | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 308 | MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 309 | |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 310 | ts = get_timer(0); |
| 311 | status = reg_read(®s->stat); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 312 | /* Wait until the TC (Transfer completed) bit is set */ |
Heiko Schocher | b77c888 | 2014-07-14 10:22:11 +0200 | [diff] [blame] | 313 | while ((status & MXC_CSPICTRL_TC) == 0) { |
| 314 | if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) { |
| 315 | printf("spi_xchg_single: Timeout!\n"); |
| 316 | return -1; |
| 317 | } |
| 318 | status = reg_read(®s->stat); |
| 319 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 320 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 321 | /* Transfer completed, clear any pending request */ |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 322 | reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 323 | |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 324 | nbytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 325 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 326 | cnt = nbytes % 32; |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 327 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 328 | if (bitlen % 32) { |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 329 | data = reg_read(®s->rxdata); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 330 | cnt = (bitlen % 32) / 8; |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 331 | data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 332 | debug("SPI Rx unaligned: 0x%x\n", data); |
| 333 | if (din) { |
Anatolij Gustschin | 089ebe0 | 2011-01-20 07:53:06 +0000 | [diff] [blame] | 334 | memcpy(din, &data, cnt); |
| 335 | din += cnt; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 336 | } |
| 337 | nbytes -= cnt; |
| 338 | } |
| 339 | |
| 340 | while (nbytes > 0) { |
| 341 | u32 tmp; |
Stefano Babic | 2858045 | 2011-01-19 22:46:33 +0000 | [diff] [blame] | 342 | tmp = reg_read(®s->rxdata); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 343 | data = cpu_to_be32(tmp); |
| 344 | debug("SPI Rx: 0x%x 0x%x\n", tmp, data); |
Masahiro Yamada | db20464 | 2014-11-07 03:03:31 +0900 | [diff] [blame] | 345 | cnt = min_t(u32, nbytes, sizeof(data)); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 346 | if (din) { |
| 347 | memcpy(din, &data, cnt); |
| 348 | din += cnt; |
| 349 | } |
| 350 | nbytes -= cnt; |
| 351 | } |
| 352 | |
| 353 | return 0; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 354 | |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 355 | } |
| 356 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 357 | static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs, |
| 358 | unsigned int bitlen, const void *dout, |
| 359 | void *din, unsigned long flags) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 360 | { |
Axel Lin | fb7def9 | 2013-06-14 21:13:32 +0800 | [diff] [blame] | 361 | int n_bytes = DIV_ROUND_UP(bitlen, 8); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 362 | int n_bits; |
| 363 | int ret; |
| 364 | u32 blk_size; |
| 365 | u8 *p_outbuf = (u8 *)dout; |
| 366 | u8 *p_inbuf = (u8 *)din; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 367 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 368 | if (!mxcs) |
| 369 | return -EINVAL; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 370 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 371 | if (flags & SPI_XFER_BEGIN) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 372 | mxc_spi_cs_activate(mxcs); |
Magnus Lilja | 1858a9a | 2010-02-09 22:05:39 +0100 | [diff] [blame] | 373 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 374 | while (n_bytes > 0) { |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 375 | if (n_bytes < MAX_SPI_BYTES) |
| 376 | blk_size = n_bytes; |
| 377 | else |
| 378 | blk_size = MAX_SPI_BYTES; |
| 379 | |
| 380 | n_bits = blk_size * 8; |
| 381 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 382 | ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 383 | |
| 384 | if (ret) |
| 385 | return ret; |
| 386 | if (dout) |
| 387 | p_outbuf += blk_size; |
| 388 | if (din) |
| 389 | p_inbuf += blk_size; |
| 390 | n_bytes -= blk_size; |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 391 | } |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 392 | |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 393 | if (flags & SPI_XFER_END) { |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 394 | mxc_spi_cs_deactivate(mxcs); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 395 | } |
| 396 | |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 397 | return 0; |
| 398 | } |
| 399 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 400 | static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs) |
| 401 | { |
| 402 | struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; |
| 403 | int ret; |
| 404 | |
| 405 | reg_write(®s->rxdata, 1); |
| 406 | udelay(1); |
| 407 | ret = spi_cfg_mxc(mxcs, cs); |
| 408 | if (ret) { |
| 409 | printf("mxc_spi: cannot setup SPI controller\n"); |
| 410 | return ret; |
| 411 | } |
| 412 | reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); |
| 413 | reg_write(®s->intr, 0); |
| 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
Lukasz Majewski | 76f44298 | 2020-06-04 23:11:53 +0800 | [diff] [blame] | 418 | #if !CONFIG_IS_ENABLED(DM_SPI) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 419 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
| 420 | void *din, unsigned long flags) |
| 421 | { |
| 422 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 423 | |
| 424 | return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); |
| 425 | } |
| 426 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 427 | /* |
| 428 | * Some SPI devices require active chip-select over multiple |
| 429 | * transactions, we achieve this using a GPIO. Still, the SPI |
| 430 | * controller has to be configured to use one of its own chipselects. |
| 431 | * To use this feature you have to implement board_spi_cs_gpio() to assign |
| 432 | * a gpio value for each cs (-1 if cs doesn't need to use gpio). |
| 433 | * You must use some unused on this SPI controller cs between 0 and 3. |
| 434 | */ |
| 435 | static int setup_cs_gpio(struct mxc_spi_slave *mxcs, |
| 436 | unsigned int bus, unsigned int cs) |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 437 | { |
| 438 | int ret; |
| 439 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 440 | mxcs->gpio = board_spi_cs_gpio(bus, cs); |
| 441 | if (mxcs->gpio == -1) |
| 442 | return 0; |
| 443 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 444 | gpio_request(mxcs->gpio, "spi-cs"); |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 445 | ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol)); |
| 446 | if (ret) { |
| 447 | printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); |
| 448 | return -EINVAL; |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 449 | } |
| 450 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 451 | return 0; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 452 | } |
| 453 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 454 | static unsigned long spi_bases[] = { |
| 455 | MXC_SPI_BASE_ADDRESSES |
| 456 | }; |
| 457 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 458 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
| 459 | unsigned int max_hz, unsigned int mode) |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 460 | { |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 461 | struct mxc_spi_slave *mxcs; |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 462 | int ret; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 463 | |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 464 | if (bus >= ARRAY_SIZE(spi_bases)) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 465 | return NULL; |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 466 | |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 467 | if (max_hz == 0) { |
| 468 | printf("Error: desired clock is 0\n"); |
| 469 | return NULL; |
| 470 | } |
| 471 | |
Simon Glass | d034a95 | 2013-03-18 19:23:40 +0000 | [diff] [blame] | 472 | mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 473 | if (!mxcs) { |
| 474 | puts("mxc_spi: SPI Slave not allocated !\n"); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 475 | return NULL; |
Stefano Babic | 125f82a | 2010-08-20 12:05:03 +0200 | [diff] [blame] | 476 | } |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 477 | |
Fabio Estevam | 17cd2a8 | 2012-11-15 11:23:23 +0000 | [diff] [blame] | 478 | mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; |
| 479 | |
Nikita Kiryanov | 00cd738 | 2014-08-20 15:08:50 +0300 | [diff] [blame] | 480 | ret = setup_cs_gpio(mxcs, bus, cs); |
Guennadi Liakhovetski | 9a88d70 | 2009-02-13 09:26:40 +0100 | [diff] [blame] | 481 | if (ret < 0) { |
| 482 | free(mxcs); |
| 483 | return NULL; |
| 484 | } |
| 485 | |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 486 | mxcs->base = spi_bases[bus]; |
Markus Niebel | 8f769cf | 2014-10-23 16:09:39 +0200 | [diff] [blame] | 487 | mxcs->max_hz = max_hz; |
| 488 | mxcs->mode = mode; |
Stefano Babic | 6e6f455 | 2010-04-04 22:43:38 +0200 | [diff] [blame] | 489 | |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 490 | return &mxcs->slave; |
| 491 | } |
| 492 | |
| 493 | void spi_free_slave(struct spi_slave *slave) |
| 494 | { |
Guennadi Liakhovetski | d338013 | 2009-02-07 00:09:12 +0100 | [diff] [blame] | 495 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 496 | |
| 497 | free(mxcs); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | int spi_claim_bus(struct spi_slave *slave) |
| 501 | { |
| 502 | struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); |
| 503 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 504 | return mxc_spi_claim_bus_internal(mxcs, slave->cs); |
| 505 | } |
| 506 | |
| 507 | void spi_release_bus(struct spi_slave *slave) |
| 508 | { |
| 509 | /* TODO: Shut the controller down */ |
| 510 | } |
| 511 | #else |
| 512 | |
| 513 | static int mxc_spi_probe(struct udevice *bus) |
| 514 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 515 | struct mxc_spi_slave *mxcs = dev_get_plat(bus); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 516 | int node = dev_of_offset(bus); |
| 517 | const void *blob = gd->fdt_blob; |
| 518 | int ret; |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 519 | int i; |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 520 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 521 | ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios, |
| 522 | ARRAY_SIZE(mxcs->cs_gpios), 0); |
| 523 | if (ret < 0) { |
| 524 | pr_err("Can't get %s gpios! Error: %d", bus->name, ret); |
| 525 | return ret; |
| 526 | } |
| 527 | |
| 528 | for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) { |
| 529 | if (!dm_gpio_is_valid(&mxcs->cs_gpios[i])) |
| 530 | continue; |
| 531 | |
| 532 | ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i], |
| 533 | GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); |
| 534 | if (ret) { |
| 535 | dev_err(bus, "Setting cs %d error\n", i); |
| 536 | return ret; |
| 537 | } |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 538 | } |
| 539 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 540 | mxcs->base = dev_read_addr(bus); |
Heiko Schocher | 6d49b4e | 2019-05-26 12:15:46 +0200 | [diff] [blame] | 541 | if (mxcs->base == FDT_ADDR_T_NONE) |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 542 | return -ENODEV; |
| 543 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 544 | mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", |
| 545 | 20000000); |
Guennadi Liakhovetski | 07327a5 | 2008-04-15 14:14:25 +0200 | [diff] [blame] | 546 | |
| 547 | return 0; |
| 548 | } |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 549 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 550 | static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 551 | const void *dout, void *din, unsigned long flags) |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 552 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 553 | struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 554 | |
| 555 | |
| 556 | return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags); |
| 557 | } |
| 558 | |
| 559 | static int mxc_spi_claim_bus(struct udevice *dev) |
| 560 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 561 | struct mxc_spi_slave *mxcs = dev_get_plat(dev->parent); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame^] | 562 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 563 | |
Heiko Schocher | 053c244 | 2019-05-26 12:15:47 +0200 | [diff] [blame] | 564 | mxcs->dev = dev; |
| 565 | |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 566 | return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs); |
Haavard Skinnemoen | d74084a | 2008-05-16 11:10:31 +0200 | [diff] [blame] | 567 | } |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 568 | |
| 569 | static int mxc_spi_release_bus(struct udevice *dev) |
| 570 | { |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | static int mxc_spi_set_speed(struct udevice *bus, uint speed) |
| 575 | { |
| 576 | /* Nothing to do */ |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | static int mxc_spi_set_mode(struct udevice *bus, uint mode) |
| 581 | { |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 582 | struct mxc_spi_slave *mxcs = dev_get_plat(bus); |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 583 | |
| 584 | mxcs->mode = mode; |
| 585 | mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | static const struct dm_spi_ops mxc_spi_ops = { |
| 591 | .claim_bus = mxc_spi_claim_bus, |
| 592 | .release_bus = mxc_spi_release_bus, |
| 593 | .xfer = mxc_spi_xfer, |
| 594 | .set_speed = mxc_spi_set_speed, |
| 595 | .set_mode = mxc_spi_set_mode, |
| 596 | }; |
| 597 | |
| 598 | static const struct udevice_id mxc_spi_ids[] = { |
| 599 | { .compatible = "fsl,imx51-ecspi" }, |
| 600 | { } |
| 601 | }; |
| 602 | |
| 603 | U_BOOT_DRIVER(mxc_spi) = { |
| 604 | .name = "mxc_spi", |
| 605 | .id = UCLASS_SPI, |
| 606 | .of_match = mxc_spi_ids, |
| 607 | .ops = &mxc_spi_ops, |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 608 | .plat_auto = sizeof(struct mxc_spi_slave), |
Peng Fan | ea0bce6 | 2017-08-09 13:09:33 +0800 | [diff] [blame] | 609 | .probe = mxc_spi_probe, |
| 610 | }; |
| 611 | #endif |