blob: 1847d1f6ecd23416aec899a9aa1a0605d101137c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek76bed832012-09-14 00:55:24 +00002/*
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
Michal Simek76bed832012-09-14 00:55:24 +00005 */
6
Michal Simekeea9d962016-07-14 14:40:03 +02007#include <clk.h>
Michal Simek76bed832012-09-14 00:55:24 +00008#include <common.h>
Simon Glass23d9b622015-10-17 19:41:27 -06009#include <debug_uart.h>
10#include <dm.h>
Simon Glass091f6a32015-10-17 19:41:22 -060011#include <errno.h>
Michal Simek3554b2b2014-02-24 11:16:33 +010012#include <fdtdec.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Michal Simek76bed832012-09-14 00:55:24 +000014#include <watchdog.h>
15#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -070016#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Michal Simek76bed832012-09-14 00:55:24 +000018#include <linux/compiler.h>
19#include <serial.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070020#include <linux/err.h>
Michal Simek76bed832012-09-14 00:55:24 +000021
Michal Simek5e3c4c72018-06-14 11:13:41 +020022#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
Michal Simek6b8dcec2018-06-14 09:43:34 +020023#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
Michal Simekb5fb1be2022-03-25 11:50:07 +010024#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */
Michal Simek5e3c4c72018-06-14 11:13:41 +020025#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
Michal Simek76bed832012-09-14 00:55:24 +000026
Michal Simek5e3c4c72018-06-14 11:13:41 +020027#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
28#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
29#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
30#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
Michal Simek76bed832012-09-14 00:55:24 +000031
Kunihiko Hayashia7077032021-06-25 20:19:11 +090032#define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
33#define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */
34#define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
35
Michal Simek76bed832012-09-14 00:55:24 +000036#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
Kunihiko Hayashia7077032021-06-25 20:19:11 +090037#define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
38#define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
39
40#define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
41#define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
42#define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
Michal Simek76bed832012-09-14 00:55:24 +000043
Michal Simek76bed832012-09-14 00:55:24 +000044struct uart_zynq {
Michal Simek0c33c0f2015-01-07 15:00:47 +010045 u32 control; /* 0x0 - Control Register [8:0] */
46 u32 mode; /* 0x4 - Mode Register [10:0] */
Michal Simek76bed832012-09-14 00:55:24 +000047 u32 reserved1[4];
Michal Simek0c33c0f2015-01-07 15:00:47 +010048 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
Michal Simek76bed832012-09-14 00:55:24 +000049 u32 reserved2[4];
Michal Simek0c33c0f2015-01-07 15:00:47 +010050 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
51 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
52 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
Michal Simek76bed832012-09-14 00:55:24 +000053};
54
Simon Glassb75b15b2020-12-03 16:55:23 -070055struct zynq_uart_plat {
Simon Glass23d9b622015-10-17 19:41:27 -060056 struct uart_zynq *regs;
Michal Simek20d1ebf2013-12-19 23:38:58 +053057};
58
Michal Simekb3f33102020-03-24 11:31:42 +010059/* Set up the baud rate */
Simon Glass091f6a32015-10-17 19:41:22 -060060static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
61 unsigned long clock, unsigned long baud)
Michal Simek76bed832012-09-14 00:55:24 +000062{
63 /* Calculation results. */
64 unsigned int calc_bauderror, bdiv, bgen;
65 unsigned long calc_baud = 0;
Michal Simek76bed832012-09-14 00:55:24 +000066
Michal Simek1a4d32e2015-04-15 13:05:06 +020067 /* Covering case where input clock is so slow */
Simon Glass091f6a32015-10-17 19:41:22 -060068 if (clock < 1000000 && baud > 4800)
69 baud = 4800;
Michal Simek1a4d32e2015-04-15 13:05:06 +020070
Michal Simek76bed832012-09-14 00:55:24 +000071 /* master clock
72 * Baud rate = ------------------
73 * bgen * (bdiv + 1)
74 *
75 * Find acceptable values for baud generation.
76 */
77 for (bdiv = 4; bdiv < 255; bdiv++) {
Kunihiko Hayashi49622a12022-07-13 10:38:59 +090078 bgen = DIV_ROUND_CLOSEST(clock, baud * (bdiv + 1));
Michal Simek76bed832012-09-14 00:55:24 +000079 if (bgen < 2 || bgen > 65535)
80 continue;
81
82 calc_baud = clock / (bgen * (bdiv + 1));
83
84 /*
85 * Use first calculated baudrate with
86 * an acceptable (<3%) error
87 */
88 if (baud > calc_baud)
89 calc_bauderror = baud - calc_baud;
90 else
91 calc_bauderror = calc_baud - baud;
92 if (((calc_bauderror * 100) / baud) < 3)
93 break;
94 }
95
96 writel(bdiv, &regs->baud_rate_divider);
97 writel(bgen, &regs->baud_rate_gen);
98}
99
Simon Glass091f6a32015-10-17 19:41:22 -0600100/* Initialize the UART, with...some settings. */
101static void _uart_zynq_serial_init(struct uart_zynq *regs)
102{
Michal Simek76bed832012-09-14 00:55:24 +0000103 /* RX/TX enabled & reset */
104 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
105 ZYNQ_UART_CR_RXRST, &regs->control);
106 writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
Simon Glass091f6a32015-10-17 19:41:22 -0600107}
108
Simon Glass091f6a32015-10-17 19:41:22 -0600109static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
110{
Simon Glassabdd2562023-02-05 15:39:32 -0700111 if (IS_ENABLED(CONFIG_DEBUG_UART_ZYNQ)) {
Michal Simekb5fb1be2022-03-25 11:50:07 +0100112 if (!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
113 return -EAGAIN;
114 } else {
115 if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
116 return -EAGAIN;
117 }
Simon Glass091f6a32015-10-17 19:41:22 -0600118
119 writel(c, &regs->tx_rx_fifo);
120
121 return 0;
122}
123
Michal Simek8d5f8432018-06-14 11:19:57 +0200124static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
Michal Simek76bed832012-09-14 00:55:24 +0000125{
Simon Glassb75b15b2020-12-03 16:55:23 -0700126 struct zynq_uart_plat *plat = dev_get_plat(dev);
Michal Simekeea9d962016-07-14 14:40:03 +0200127 unsigned long clock;
Michal Simek76bed832012-09-14 00:55:24 +0000128
Michal Simekeea9d962016-07-14 14:40:03 +0200129 int ret;
130 struct clk clk;
131
132 ret = clk_get_by_index(dev, 0, &clk);
133 if (ret < 0) {
134 dev_err(dev, "failed to get clock\n");
135 return ret;
136 }
137
138 clock = clk_get_rate(&clk);
139 if (IS_ERR_VALUE(clock)) {
140 dev_err(dev, "failed to get rate\n");
141 return clock;
142 }
143 debug("%s: CLK %ld\n", __func__, clock);
144
145 ret = clk_enable(&clk);
Michal Simek41710952021-02-09 15:28:15 +0100146 if (ret) {
Michal Simekeea9d962016-07-14 14:40:03 +0200147 dev_err(dev, "failed to enable clock\n");
148 return ret;
149 }
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +0100150
Simon Glass71fa5b42020-12-03 16:55:18 -0700151 _uart_zynq_serial_setbrg(plat->regs, clock, baudrate);
Michal Simek76bed832012-09-14 00:55:24 +0000152
Simon Glass23d9b622015-10-17 19:41:27 -0600153 return 0;
Michal Simek76bed832012-09-14 00:55:24 +0000154}
Kunihiko Hayashia7077032021-06-25 20:19:11 +0900155
156#if !defined(CONFIG_SPL_BUILD)
157static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
158{
159 struct zynq_uart_plat *plat = dev_get_plat(dev);
160 struct uart_zynq *regs = plat->regs;
161 u32 val = 0;
162
163 switch (SERIAL_GET_BITS(serial_config)) {
164 case SERIAL_6_BITS:
165 val |= ZYNQ_UART_MR_CHARLEN_6_BIT;
166 break;
167 case SERIAL_7_BITS:
168 val |= ZYNQ_UART_MR_CHARLEN_7_BIT;
169 break;
170 case SERIAL_8_BITS:
171 val |= ZYNQ_UART_MR_CHARLEN_8_BIT;
172 break;
173 default:
174 return -ENOTSUPP; /* not supported in driver */
175 }
176
177 switch (SERIAL_GET_STOP(serial_config)) {
178 case SERIAL_ONE_STOP:
179 val |= ZYNQ_UART_MR_STOPMODE_1_BIT;
180 break;
181 case SERIAL_ONE_HALF_STOP:
182 val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT;
183 break;
184 case SERIAL_TWO_STOP:
185 val |= ZYNQ_UART_MR_STOPMODE_2_BIT;
186 break;
187 default:
188 return -ENOTSUPP; /* not supported in driver */
189 }
190
191 switch (SERIAL_GET_PARITY(serial_config)) {
192 case SERIAL_PAR_NONE:
193 val |= ZYNQ_UART_MR_PARITY_NONE;
194 break;
195 case SERIAL_PAR_ODD:
196 val |= ZYNQ_UART_MR_PARITY_ODD;
197 break;
198 case SERIAL_PAR_EVEN:
199 val |= ZYNQ_UART_MR_PARITY_EVEN;
200 break;
201 default:
202 return -ENOTSUPP; /* not supported in driver */
203 }
204
205 writel(val, &regs->mode);
206
207 return 0;
208}
209#else
210#define zynq_serial_setconfig NULL
211#endif
Michal Simek76bed832012-09-14 00:55:24 +0000212
Simon Glass23d9b622015-10-17 19:41:27 -0600213static int zynq_serial_probe(struct udevice *dev)
Michal Simek76bed832012-09-14 00:55:24 +0000214{
Simon Glassb75b15b2020-12-03 16:55:23 -0700215 struct zynq_uart_plat *plat = dev_get_plat(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -0700216 struct uart_zynq *regs = plat->regs;
Michal Simekb3f33102020-03-24 11:31:42 +0100217 u32 val;
Michal Simek76bed832012-09-14 00:55:24 +0000218
Michal Simekb3f33102020-03-24 11:31:42 +0100219 /* No need to reinitialize the UART if TX already enabled */
220 val = readl(&regs->control);
221 if (val & ZYNQ_UART_CR_TX_EN)
Michal Simeke68f4ab2018-06-14 10:41:35 +0200222 return 0;
223
Simon Glass71fa5b42020-12-03 16:55:18 -0700224 _uart_zynq_serial_init(plat->regs);
Michal Simek76bed832012-09-14 00:55:24 +0000225
Simon Glass23d9b622015-10-17 19:41:27 -0600226 return 0;
Michal Simek76bed832012-09-14 00:55:24 +0000227}
228
Simon Glass23d9b622015-10-17 19:41:27 -0600229static int zynq_serial_getc(struct udevice *dev)
Michal Simek76bed832012-09-14 00:55:24 +0000230{
Simon Glassb75b15b2020-12-03 16:55:23 -0700231 struct zynq_uart_plat *plat = dev_get_plat(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -0700232 struct uart_zynq *regs = plat->regs;
Simon Glass23d9b622015-10-17 19:41:27 -0600233
234 if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
235 return -EAGAIN;
Michal Simek76bed832012-09-14 00:55:24 +0000236
Michal Simek76bed832012-09-14 00:55:24 +0000237 return readl(&regs->tx_rx_fifo);
238}
239
Simon Glass23d9b622015-10-17 19:41:27 -0600240static int zynq_serial_putc(struct udevice *dev, const char ch)
241{
Simon Glassb75b15b2020-12-03 16:55:23 -0700242 struct zynq_uart_plat *plat = dev_get_plat(dev);
Michal Simek76bed832012-09-14 00:55:24 +0000243
Simon Glass71fa5b42020-12-03 16:55:18 -0700244 return _uart_zynq_serial_putc(plat->regs, ch);
Michal Simek76bed832012-09-14 00:55:24 +0000245}
246
Simon Glass23d9b622015-10-17 19:41:27 -0600247static int zynq_serial_pending(struct udevice *dev, bool input)
Michal Simek76bed832012-09-14 00:55:24 +0000248{
Simon Glassb75b15b2020-12-03 16:55:23 -0700249 struct zynq_uart_plat *plat = dev_get_plat(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -0700250 struct uart_zynq *regs = plat->regs;
Michal Simek3554b2b2014-02-24 11:16:33 +0100251
Simon Glass23d9b622015-10-17 19:41:27 -0600252 if (input)
253 return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
254 else
255 return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
256}
Michal Simek3554b2b2014-02-24 11:16:33 +0100257
Simon Glassaad29ae2020-12-03 16:55:21 -0700258static int zynq_serial_of_to_plat(struct udevice *dev)
Simon Glass23d9b622015-10-17 19:41:27 -0600259{
Simon Glassb75b15b2020-12-03 16:55:23 -0700260 struct zynq_uart_plat *plat = dev_get_plat(dev);
Michal Simek3554b2b2014-02-24 11:16:33 +0100261
Johan Jonker8d5d8e02023-03-13 01:32:04 +0100262 plat->regs = dev_read_addr_ptr(dev);
263 if (!plat->regs)
264 return -EINVAL;
Michal Simek3554b2b2014-02-24 11:16:33 +0100265
Simon Glass23d9b622015-10-17 19:41:27 -0600266 return 0;
Michal Simek3554b2b2014-02-24 11:16:33 +0100267}
Tom Rini354531e2012-10-08 14:46:23 -0700268
Simon Glass23d9b622015-10-17 19:41:27 -0600269static const struct dm_serial_ops zynq_serial_ops = {
270 .putc = zynq_serial_putc,
271 .pending = zynq_serial_pending,
272 .getc = zynq_serial_getc,
273 .setbrg = zynq_serial_setbrg,
Kunihiko Hayashia7077032021-06-25 20:19:11 +0900274 .setconfig = zynq_serial_setconfig,
Simon Glass23d9b622015-10-17 19:41:27 -0600275};
276
277static const struct udevice_id zynq_serial_ids[] = {
278 { .compatible = "xlnx,xuartps" },
279 { .compatible = "cdns,uart-r1p8" },
Michal Simekf0a71d02016-01-14 11:45:52 +0100280 { .compatible = "cdns,uart-r1p12" },
Michal Simek9ec379b2022-01-11 13:55:19 +0100281 { .compatible = "xlnx,zynqmp-uart" },
Simon Glass23d9b622015-10-17 19:41:27 -0600282 { }
283};
284
Michal Simek49e12762015-12-01 14:29:34 +0100285U_BOOT_DRIVER(serial_zynq) = {
Simon Glass23d9b622015-10-17 19:41:27 -0600286 .name = "serial_zynq",
287 .id = UCLASS_SERIAL,
288 .of_match = zynq_serial_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700289 .of_to_plat = zynq_serial_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -0700290 .plat_auto = sizeof(struct zynq_uart_plat),
Simon Glass23d9b622015-10-17 19:41:27 -0600291 .probe = zynq_serial_probe,
292 .ops = &zynq_serial_ops,
Simon Glass23d9b622015-10-17 19:41:27 -0600293};
Simon Glass091f6a32015-10-17 19:41:22 -0600294
295#ifdef CONFIG_DEBUG_UART_ZYNQ
Michal Simekd9afb232016-01-05 12:49:21 +0100296static inline void _debug_uart_init(void)
Simon Glass091f6a32015-10-17 19:41:22 -0600297{
Pali Rohár8864b352022-05-27 22:15:24 +0200298 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
Simon Glass091f6a32015-10-17 19:41:22 -0600299
300 _uart_zynq_serial_init(regs);
301 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
302 CONFIG_BAUDRATE);
303}
304
305static inline void _debug_uart_putc(int ch)
306{
Pali Rohár8864b352022-05-27 22:15:24 +0200307 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
Simon Glass091f6a32015-10-17 19:41:22 -0600308
309 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
Stefan Roese80877fa2022-09-02 14:10:46 +0200310 schedule();
Simon Glass091f6a32015-10-17 19:41:22 -0600311}
312
313DEBUG_UART_FUNCS
314
315#endif