| commit | 6b8dcec5f6e31fc814da0ed193dc4f4b475d542a | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Thu Jun 14 09:43:34 2018 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Fri Jun 15 08:54:05 2018 +0200 |
| tree | 7f163cb75a279c0fbfc8d4310a8d90d2660ae2e0 | |
| parent | 5e3c4c7d1460659cd351e62964812bf4c1d4aded [diff] |
serial: zynq: Write chars till output fifo is full Change logic and put char to fifo till there is a space in output fifo. Origin logic was that output fifo needs to be empty. It means only one char was in output queue. Also remove unused ZYNQ_UART_SR_TXEMPTY macro. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>