Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | .. sectionauthor:: Udit Kumar <u-kumar1@ti.com> |
| 3 | |
| 4 | J7200 Platforms |
| 5 | =============== |
| 6 | |
| 7 | Introduction: |
| 8 | ------------- |
| 9 | The J7200 family of SoCs are part of K3 Multicore SoC architecture platform |
| 10 | targeting automotive applications. They are designed as a low power, high |
| 11 | performance and highly integrated device architecture, adding significant |
| 12 | enhancement on processing power, graphics capability, video and imaging |
| 13 | processing, virtualization and coherent memory support. |
| 14 | |
| 15 | The device is partitioned into three functional domains, each containing |
| 16 | specific processing cores and peripherals: |
| 17 | |
| 18 | 1. Wake-up (WKUP) domain: |
| 19 | * Device Management and Security Controller (DMSC) |
| 20 | |
| 21 | 2. Microcontroller (MCU) domain: |
| 22 | * Dual Core ARM Cortex-R5F processor |
| 23 | |
| 24 | 3. MAIN domain: |
| 25 | * Dual core 64-bit ARM Cortex-A72 |
| 26 | |
| 27 | More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 |
| 28 | |
| 29 | Boot Flow: |
| 30 | ---------- |
| 31 | Below is the pictorial representation of boot flow: |
| 32 | |
Nishanth Menon | b47c9f7 | 2023-07-27 13:58:45 -0500 | [diff] [blame] | 33 | .. image:: img/boot_diagram_k3_current.svg |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 34 | |
| 35 | - Here DMSC acts as master and provides all the critical services. R5/A72 |
| 36 | requests DMSC to get these services done as shown in the above diagram. |
| 37 | |
| 38 | Sources: |
| 39 | -------- |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 40 | |
Nishanth Menon | ee91e48 | 2023-07-27 13:58:44 -0500 | [diff] [blame] | 41 | .. include:: k3.rst |
| 42 | :start-after: .. k3_rst_include_start_boot_sources |
| 43 | :end-before: .. k3_rst_include_end_boot_sources |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 44 | |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 45 | Build procedure: |
| 46 | ---------------- |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 47 | 0. Setup the environment variables: |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 48 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 49 | .. include:: k3.rst |
| 50 | :start-after: .. k3_rst_include_start_common_env_vars_desc |
| 51 | :end-before: .. k3_rst_include_end_common_env_vars_desc |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 52 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 53 | .. include:: k3.rst |
| 54 | :start-after: .. k3_rst_include_start_board_env_vars_desc |
| 55 | :end-before: .. k3_rst_include_end_board_env_vars_desc |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 56 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 57 | Set the variables corresponding to this platform: |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 58 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 59 | .. include:: k3.rst |
| 60 | :start-after: .. k3_rst_include_start_common_env_vars_defn |
| 61 | :end-before: .. k3_rst_include_end_common_env_vars_defn |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 62 | .. code-block:: bash |
| 63 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 64 | $ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig |
| 65 | $ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig |
| 66 | $ export TFA_BOARD=generic |
| 67 | $ # we dont use any extra TFA parameters |
| 68 | $ unset TFA_EXTRA_ARGS |
| 69 | $ export OPTEE_PLATFORM=k3-j7200 |
| 70 | $ # we dont use any extra OP-TEE parameters |
| 71 | $ unset OPTEE_EXTRA_ARGS |
| 72 | |
| 73 | .. j7200_evm_rst_include_start_build_steps |
| 74 | |
| 75 | 1. Trusted Firmware-A: |
| 76 | |
| 77 | .. include:: k3.rst |
| 78 | :start-after: .. k3_rst_include_start_build_steps_tfa |
| 79 | :end-before: .. k3_rst_include_end_build_steps_tfa |
| 80 | |
| 81 | |
| 82 | 2. OP-TEE: |
| 83 | |
| 84 | .. include:: k3.rst |
| 85 | :start-after: .. k3_rst_include_start_build_steps_optee |
| 86 | :end-before: .. k3_rst_include_end_build_steps_optee |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 87 | |
Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 88 | 3. U-Boot: |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 89 | |
| 90 | * 4.1 R5: |
| 91 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 92 | .. include:: k3.rst |
| 93 | :start-after: .. k3_rst_include_start_build_steps_spl_r5 |
| 94 | :end-before: .. k3_rst_include_end_build_steps_spl_r5 |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 95 | |
| 96 | * 4.2 A72: |
| 97 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 98 | .. include:: k3.rst |
| 99 | :start-after: .. k3_rst_include_start_build_steps_uboot |
| 100 | :end-before: .. k3_rst_include_end_build_steps_uboot |
| 101 | .. j7200_evm_rst_include_end_build_steps |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 102 | |
| 103 | Target Images |
| 104 | -------------- |
Tom Rini | fdf4503 | 2023-07-25 12:44:16 -0400 | [diff] [blame] | 105 | In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC |
| 106 | variant (GP, HS-FS, HS-SE) requires a different source for these files. |
Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 107 | |
| 108 | - GP |
| 109 | |
| 110 | * tiboot3-j7200-gp-evm.bin from step 4.1 |
| 111 | * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 |
| 112 | |
| 113 | - HS-FS |
| 114 | |
| 115 | * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1 |
| 116 | * tispl.bin, u-boot.img from step 4.2 |
| 117 | |
| 118 | - HS-SE |
| 119 | |
| 120 | * tiboot3-j7200_sr2-hs-evm.bin from step 4.1 |
| 121 | * tispl.bin, u-boot.img from step 4.2 |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 122 | |
| 123 | Image formats: |
| 124 | -------------- |
| 125 | |
Nishanth Menon | b1e1c3b | 2023-07-27 13:58:49 -0500 | [diff] [blame^] | 126 | - tiboot3.bin |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 127 | |
Nishanth Menon | b1e1c3b | 2023-07-27 13:58:49 -0500 | [diff] [blame^] | 128 | .. image:: img/j7200_tiboot3.bin.svg |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 129 | |
| 130 | - tispl.bin |
| 131 | |
Nishanth Menon | b1e1c3b | 2023-07-27 13:58:49 -0500 | [diff] [blame^] | 132 | .. image:: img/dm_tispl.bin.svg |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 133 | |
Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 134 | |
| 135 | |
| 136 | Switch Setting for Boot Mode |
| 137 | ---------------------------- |
| 138 | |
| 139 | Boot Mode pins provide means to select the boot mode and options before the |
| 140 | device is powered up. After every POR, they are the main source to populate |
| 141 | the Boot Parameter Tables. |
| 142 | |
| 143 | The following table shows some common boot modes used on J7200 platform. More |
| 144 | details can be found in the Technical Reference Manual: |
| 145 | https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. |
| 146 | |
| 147 | |
| 148 | *Boot Modes* |
| 149 | |
| 150 | ============ ============= ============= |
| 151 | Switch Label SW9: 12345678 SW8: 12345678 |
| 152 | ============ ============= ============= |
| 153 | SD 00000000 10000010 |
| 154 | EMMC 01000000 10000000 |
| 155 | OSPI 01000000 00000110 |
| 156 | UART 01110000 00000000 |
| 157 | USB DFU 00100000 10000000 |
| 158 | ============ ============= ============= |
| 159 | |
| 160 | For SW8 and SW9, the switch state in the "ON" position = 1. |
| 161 | |
| 162 | eMMC: |
| 163 | ----- |
| 164 | ROM supports booting from eMMC raw read or UDA FS mode. |
| 165 | |
| 166 | Below is memory layout in case of booting from |
| 167 | boot 0/1 partition in raw mode. |
| 168 | |
| 169 | Current allocated size for tiboot3 size is 1MB, tispl is 2MB. |
| 170 | |
| 171 | Size of u-boot.img is taken 4MB for refernece, |
| 172 | But this is subject to change depending upon atf, optee size |
| 173 | |
| 174 | .. code-block:: console |
| 175 | |
| 176 | boot0/1 partition (8 MB) user partition |
| 177 | 0x0+----------------------------------+ 0x0+------------------------+ |
| 178 | | tiboot3.bin (1 MB) | | | |
| 179 | 0x800+----------------------------------+ | | |
| 180 | | tispl.bin (2 MB) | | | |
| 181 | 0x1800+----------------------------------+ | | |
| 182 | | u-boot.img (4MB) | | | |
| 183 | 0x3800+----------------------------------+ | | |
| 184 | | | | | |
| 185 | 0x3900+ environment | | | |
| 186 | | | | | |
| 187 | 0x3A00+----------------------------------+ +-------------------------+ |
| 188 | |
| 189 | In case of UDA FS mode booting, following is layout. |
| 190 | |
| 191 | All boot images tiboot3.bin, tispl and u-boot should be written to |
| 192 | fat formatted UDA FS as file. |
| 193 | |
| 194 | .. code-block:: console |
| 195 | |
| 196 | boot0/1 partition (8 MB) user partition |
| 197 | 0x0+---------------------------------+ 0x0+-------------------------+ |
| 198 | | | | tiboot3.bin* | |
| 199 | 0x800+----------------------------------+ | | |
| 200 | | | | tispl.bin | |
| 201 | 0x1800+----------------------------------+ | | |
| 202 | | | | u-boot.img | |
| 203 | 0x3800+----------------------------------+ | | |
| 204 | | | | | |
| 205 | 0x3900+ | | environment | |
| 206 | | | | | |
| 207 | 0x3A00+----------------------------------+ +-------------------------+ |
| 208 | |
| 209 | |
| 210 | |
| 211 | In case of booting from eMMC, write above images into raw or UDA FS. |
| 212 | and set mmc partconf accordingly. |