| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | .. sectionauthor:: Udit Kumar <u-kumar1@ti.com> |
| 3 | |
| 4 | J7200 Platforms |
| 5 | =============== |
| 6 | |
| 7 | Introduction: |
| 8 | ------------- |
| 9 | The J7200 family of SoCs are part of K3 Multicore SoC architecture platform |
| 10 | targeting automotive applications. They are designed as a low power, high |
| 11 | performance and highly integrated device architecture, adding significant |
| 12 | enhancement on processing power, graphics capability, video and imaging |
| 13 | processing, virtualization and coherent memory support. |
| 14 | |
| 15 | The device is partitioned into three functional domains, each containing |
| 16 | specific processing cores and peripherals: |
| 17 | |
| 18 | 1. Wake-up (WKUP) domain: |
| 19 | * Device Management and Security Controller (DMSC) |
| 20 | |
| 21 | 2. Microcontroller (MCU) domain: |
| 22 | * Dual Core ARM Cortex-R5F processor |
| 23 | |
| 24 | 3. MAIN domain: |
| 25 | * Dual core 64-bit ARM Cortex-A72 |
| 26 | |
| 27 | More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 |
| 28 | |
| 29 | Boot Flow: |
| 30 | ---------- |
| 31 | Below is the pictorial representation of boot flow: |
| 32 | |
| 33 | .. code-block:: text |
| 34 | |
| 35 | +------------------------------------------------------------------------+-----------------------+ |
| 36 | | DMSC | MCU R5 | A72 | MAIN R5/C7x | |
| 37 | +------------------------------------------------------------------------+-----------------------+ |
| 38 | | +--------+ | | | | |
| 39 | | | Reset | | | | | |
| 40 | | +--------+ | | | | |
| 41 | | : | | | | |
| 42 | | +--------+ | +-----------+ | | | |
| 43 | | | *ROM* |----------|-->| Reset rls | | | | |
| 44 | | +--------+ | +-----------+ | | | |
| 45 | | | | | : | | | |
| 46 | | | ROM | | : | | | |
| 47 | | |services| | : | | | |
| 48 | | | | | +-------------+ | | | |
| 49 | | | | | | *R5 ROM* | | | | |
| 50 | | | | | +-------------+ | | | |
| 51 | | | |<---------|---|Load and auth| | | | |
| 52 | | | | | | tiboot3.bin | | | | |
| 53 | | | Start | | +-------------+ | | | |
| 54 | | | TIFS |<---------|---| Start | | | | |
| 55 | | | | | | TIFS | | | | |
| 56 | | +--------+ | +-------------+ | | | |
| 57 | | : | | | | | | |
| 58 | | +---------+ | | Load | | | | |
| 59 | | | *TIFS* | | | system | | | | |
| 60 | | +---------+ | | Config data | | | | |
| 61 | | | |<--------|---| | | | | |
| 62 | | | | | +-------------+ | | | |
| 63 | | | | | : | | | |
| 64 | | | | | : | | | |
| 65 | | | | | : | | | |
| 66 | | | | | +-------------+ | | | |
| 67 | | | | | | *R5 SPL* | | | | |
| 68 | | | | | +-------------+ | | | |
| 69 | | | | | | DDR | | | | |
| 70 | | | | | | config | | | | |
| 71 | | | | | +-------------+ | | | |
| 72 | | | | | | Load | | | | |
| 73 | | | | | | tispl.bin | | | | |
| 74 | | | | | +-------------+ | | | |
| 75 | | | | | | Load R5 | | | | |
| 76 | | | | | | firmware | | | | |
| 77 | | | | | +-------------+ | | | |
| 78 | | | |<--------|---| Start A72 | | | | |
| 79 | | | | | | and jump to | | | | |
| 80 | | | | | | DM fw image | | | | |
| 81 | | | | | +-------------+ | | | |
| 82 | | | | | | +-----------+ | | |
| 83 | | | |---------|-----------------------|---->| Reset rls | | | |
| 84 | | | | | | +-----------+ | | |
| 85 | | | TIFS | | | : | | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 86 | | |Services | | | +-------------+ | | |
| 87 | | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | |
| 88 | | | | | | +-------------+ | | |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 89 | | | | | | : | | |
| 90 | | | | | | +-----------+ | | |
| 91 | | | |<--------|-----------------------|---->| *A72 SPL* | | | |
| 92 | | | | | | +-----------+ | | |
| 93 | | | | | | | Load | | | |
| 94 | | | | | | | u-boot.img| | | |
| 95 | | | | | | +-----------+ | | |
| 96 | | | | | | : | | |
| 97 | | | | | | +-----------+ | | |
| 98 | | | |<--------|-----------------------|---->| *U-Boot* | | | |
| 99 | | | | | | +-----------+ | | |
| 100 | | | | | | | prompt | | | |
| 101 | | | | | | +-----------+ | | |
| 102 | | | | | | | Load R5 | | | |
| 103 | | | | | | | Firmware | | | |
| 104 | | | | | | +-----------+ | | |
| 105 | | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | |
| 106 | | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | |
| 107 | | | | | | | Load C7 | | +-----------+ | |
| 108 | | | | | | | Firmware | | | |
| 109 | | | | | | +-----------+ | | |
| 110 | | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | |
| 111 | | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | |
| 112 | | | | | | | +-----------+ | |
| 113 | | | | | | | | |
| 114 | | +---------+ | | | | |
| 115 | | | | | | |
| 116 | +------------------------------------------------------------------------+-----------------------+ |
| 117 | |
| 118 | - Here DMSC acts as master and provides all the critical services. R5/A72 |
| 119 | requests DMSC to get these services done as shown in the above diagram. |
| 120 | |
| 121 | Sources: |
| 122 | -------- |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 123 | |
| Nishanth Menon | ee91e48 | 2023-07-27 13:58:44 -0500 | [diff] [blame^] | 124 | .. include:: k3.rst |
| 125 | :start-after: .. k3_rst_include_start_boot_sources |
| 126 | :end-before: .. k3_rst_include_end_boot_sources |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 127 | |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 128 | Build procedure: |
| 129 | ---------------- |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 130 | 1. Trusted Firmware-A: |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 131 | |
| 132 | .. code-block:: bash |
| 133 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 134 | $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 135 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 136 | 2. OP-TEE: |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 137 | |
| 138 | .. code-block:: bash |
| 139 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 140 | $ make PLATFORM=k3-j7200 CFG_ARM64_core=y |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 141 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 142 | 3. U-Boot: |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 143 | |
| 144 | * 4.1 R5: |
| 145 | |
| 146 | .. code-block:: bash |
| 147 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 148 | $ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 |
| 149 | $ make CROSS_COMPILE=arm-linux-gnueabihf- \ |
| 150 | BINMAN_INDIRS=<path/to/ti-linux-firmware> |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 151 | |
| 152 | * 4.2 A72: |
| 153 | |
| 154 | .. code-block:: bash |
| 155 | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 156 | $ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 |
| 157 | $ make CROSS_COMPILE=aarch64-linux-gnu- \ |
| 158 | BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \ |
| 159 | TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \ |
| 160 | BINMAN_INDIRS=<path/to/ti-linux-firmware> |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 161 | |
| 162 | Target Images |
| 163 | -------------- |
| Tom Rini | fdf4503 | 2023-07-25 12:44:16 -0400 | [diff] [blame] | 164 | In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC |
| 165 | variant (GP, HS-FS, HS-SE) requires a different source for these files. |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 166 | |
| 167 | - GP |
| 168 | |
| 169 | * tiboot3-j7200-gp-evm.bin from step 4.1 |
| 170 | * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 |
| 171 | |
| 172 | - HS-FS |
| 173 | |
| 174 | * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1 |
| 175 | * tispl.bin, u-boot.img from step 4.2 |
| 176 | |
| 177 | - HS-SE |
| 178 | |
| 179 | * tiboot3-j7200_sr2-hs-evm.bin from step 4.1 |
| 180 | * tispl.bin, u-boot.img from step 4.2 |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 181 | |
| 182 | Image formats: |
| 183 | -------------- |
| 184 | |
| 185 | - tiboot3.bin: |
| 186 | |
| 187 | .. code-block:: console |
| 188 | |
| 189 | +-----------------------+ |
| 190 | | X.509 | |
| 191 | | Certificate | |
| 192 | | +-------------------+ | |
| 193 | | | | | |
| 194 | | | R5 | | |
| 195 | | | u-boot-spl.bin | | |
| 196 | | | | | |
| 197 | | +-------------------+ | |
| 198 | | | | | |
| 199 | | | FIT header | | |
| 200 | | | +---------------+ | | |
| 201 | | | | | | | |
| 202 | | | | DTB 1...N | | | |
| 203 | | | +---------------+ | | |
| 204 | | +-------------------+ | |
| 205 | | | | | |
| 206 | | | FIT HEADER | | |
| 207 | | | +---------------+ | | |
| 208 | | | | | | | |
| 209 | | | | sysfw.bin | | | |
| 210 | | | +---------------+ | | |
| 211 | | | | | | | |
| 212 | | | | board config | | | |
| 213 | | | +---------------+ | | |
| 214 | | | | | | | |
| 215 | | | | PM config | | | |
| 216 | | | +---------------+ | | |
| 217 | | | | | | | |
| 218 | | | | RM config | | | |
| 219 | | | +---------------+ | | |
| 220 | | | | | | | |
| 221 | | | | Secure config | | | |
| 222 | | | +---------------+ | | |
| 223 | | +-------------------+ | |
| 224 | +-----------------------+ |
| 225 | |
| 226 | - tispl.bin |
| 227 | |
| 228 | .. code-block:: console |
| 229 | |
| 230 | +-----------------------+ |
| 231 | | | |
| 232 | | FIT HEADER | |
| 233 | | +-------------------+ | |
| 234 | | | | | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 235 | | | A72 TF-A | | |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 236 | | +-------------------+ | |
| 237 | | | | | |
| Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 238 | | | A72 OP-TEE | | |
| Udit Kumar | ed92ede | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 239 | | +-------------------+ | |
| 240 | | | | | |
| 241 | | | R5 DM FW | | |
| 242 | | +-------------------+ | |
| 243 | | | | | |
| 244 | | | A72 SPL | | |
| 245 | | +-------------------+ | |
| 246 | | | | | |
| 247 | | | SPL DTB 1...N | | |
| 248 | | +-------------------+ | |
| 249 | +-----------------------+ |
| 250 | |
| 251 | |
| 252 | Switch Setting for Boot Mode |
| 253 | ---------------------------- |
| 254 | |
| 255 | Boot Mode pins provide means to select the boot mode and options before the |
| 256 | device is powered up. After every POR, they are the main source to populate |
| 257 | the Boot Parameter Tables. |
| 258 | |
| 259 | The following table shows some common boot modes used on J7200 platform. More |
| 260 | details can be found in the Technical Reference Manual: |
| 261 | https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. |
| 262 | |
| 263 | |
| 264 | *Boot Modes* |
| 265 | |
| 266 | ============ ============= ============= |
| 267 | Switch Label SW9: 12345678 SW8: 12345678 |
| 268 | ============ ============= ============= |
| 269 | SD 00000000 10000010 |
| 270 | EMMC 01000000 10000000 |
| 271 | OSPI 01000000 00000110 |
| 272 | UART 01110000 00000000 |
| 273 | USB DFU 00100000 10000000 |
| 274 | ============ ============= ============= |
| 275 | |
| 276 | For SW8 and SW9, the switch state in the "ON" position = 1. |
| 277 | |
| 278 | eMMC: |
| 279 | ----- |
| 280 | ROM supports booting from eMMC raw read or UDA FS mode. |
| 281 | |
| 282 | Below is memory layout in case of booting from |
| 283 | boot 0/1 partition in raw mode. |
| 284 | |
| 285 | Current allocated size for tiboot3 size is 1MB, tispl is 2MB. |
| 286 | |
| 287 | Size of u-boot.img is taken 4MB for refernece, |
| 288 | But this is subject to change depending upon atf, optee size |
| 289 | |
| 290 | .. code-block:: console |
| 291 | |
| 292 | boot0/1 partition (8 MB) user partition |
| 293 | 0x0+----------------------------------+ 0x0+------------------------+ |
| 294 | | tiboot3.bin (1 MB) | | | |
| 295 | 0x800+----------------------------------+ | | |
| 296 | | tispl.bin (2 MB) | | | |
| 297 | 0x1800+----------------------------------+ | | |
| 298 | | u-boot.img (4MB) | | | |
| 299 | 0x3800+----------------------------------+ | | |
| 300 | | | | | |
| 301 | 0x3900+ environment | | | |
| 302 | | | | | |
| 303 | 0x3A00+----------------------------------+ +-------------------------+ |
| 304 | |
| 305 | In case of UDA FS mode booting, following is layout. |
| 306 | |
| 307 | All boot images tiboot3.bin, tispl and u-boot should be written to |
| 308 | fat formatted UDA FS as file. |
| 309 | |
| 310 | .. code-block:: console |
| 311 | |
| 312 | boot0/1 partition (8 MB) user partition |
| 313 | 0x0+---------------------------------+ 0x0+-------------------------+ |
| 314 | | | | tiboot3.bin* | |
| 315 | 0x800+----------------------------------+ | | |
| 316 | | | | tispl.bin | |
| 317 | 0x1800+----------------------------------+ | | |
| 318 | | | | u-boot.img | |
| 319 | 0x3800+----------------------------------+ | | |
| 320 | | | | | |
| 321 | 0x3900+ | | environment | |
| 322 | | | | | |
| 323 | 0x3A00+----------------------------------+ +-------------------------+ |
| 324 | |
| 325 | |
| 326 | |
| 327 | In case of booting from eMMC, write above images into raw or UDA FS. |
| 328 | and set mmc partconf accordingly. |