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git01.mediatek.com / filogic / uboot / b121cb85cf21244d672f417865c53fb9daf20359 / . / arch / arm / include / asm / arch-rockchip / cru_rk3308.h
blob: 091ae82d7cc1750b7cca84095b2ef6fb43872ce7 [file] [log] [blame]
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
4 */
5#ifndef _ASM_ARCH_CRU_RK3308_H
6#define _ASM_ARCH_CRU_RK3308_H
7
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]8#define MHz 1000000
9#define OSC_HZ (24 * MHz)
10
11#define APLL_HZ (816 * MHz)
12
13#define CORE_ACLK_HZ 408000000
14#define CORE_DBG_HZ 204000000
15
16#define BUS_ACLK_HZ 200000000
17#define BUS_HCLK_HZ 100000000
18#define BUS_PCLK_HZ 100000000
19
20#define PERI_ACLK_HZ 200000000
21#define PERI_HCLK_HZ 100000000
22#define PERI_PCLK_HZ 100000000
23
24#define AUDIO_HCLK_HZ 100000000
25#define AUDIO_PCLK_HZ 100000000
26
27#define RK3308_PLL_CON(x) ((x) * 0x4)
28#define RK3308_MODE_CON 0xa0
29
30/* RK3308 pll id */
31enum rk3308_pll_id {
32 APLL,
33 DPLL,
34 VPLL0,
35 VPLL1,
36 PLL_COUNT,
37};
38
39struct rk3308_clk_info {
40 unsigned long id;
41 char *name;
42};
43
44/* Private data for the clock driver - used by rockchip_get_cru() */
45struct rk3308_clk_priv {
46 struct rk3308_cru *cru;
47 ulong armclk_hz;
48 ulong dpll_hz;
49 ulong vpll0_hz;
50 ulong vpll1_hz;
51};
52
53struct rk3308_cru {
54 struct rk3308_pll {
55 unsigned int con0;
56 unsigned int con1;
57 unsigned int con2;
58 unsigned int con3;
59 unsigned int con4;
60 unsigned int reserved0[3];
61 } pll[4];
62 unsigned int reserved1[8];
63 unsigned int mode;
64 unsigned int misc;
65 unsigned int reserved2[2];
66 unsigned int glb_cnt_th;
67 unsigned int glb_rst_st;
68 unsigned int glb_srst_fst;
69 unsigned int glb_srst_snd;
70 unsigned int glb_rst_con;
71 unsigned int pll_lock;
72 unsigned int reserved3[6];
73 unsigned int hwffc_con0;
74 unsigned int reserved4;
75 unsigned int hwffc_th;
76 unsigned int hwffc_intst;
77 unsigned int apll_con0_s;
78 unsigned int apll_con1_s;
79 unsigned int clksel_con0_s;
80 unsigned int reserved5;
81 unsigned int clksel_con[74];
82 unsigned int reserved6[54];
83 unsigned int clkgate_con[15];
84 unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
85 unsigned int ssgtbl[32];
86 unsigned int softrst_con[10];
87 unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
88 unsigned int sdmmc_con[2];
89 unsigned int sdio_con[2];
90 unsigned int emmc_con[2];
91};
92
93enum {
94 /* PLLCON0*/
95 PLL_BP_SHIFT = 15,
96 PLL_POSTDIV1_SHIFT = 12,
97 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
98 PLL_FBDIV_SHIFT = 0,
99 PLL_FBDIV_MASK = 0xfff,
100
101 /* PLLCON1 */
102 PLL_PDSEL_SHIFT = 15,
103 PLL_PD1_SHIFT = 14,
104 PLL_PD_SHIFT = 13,
105 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
106 PLL_DSMPD_SHIFT = 12,
107 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
108 PLL_LOCK_STATUS_SHIFT = 10,
109 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
110 PLL_POSTDIV2_SHIFT = 6,
111 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
112 PLL_REFDIV_SHIFT = 0,
113 PLL_REFDIV_MASK = 0x3f,
114
115 /* PLLCON2 */
116 PLL_FOUT4PHASEPD_SHIFT = 27,
117 PLL_FOUTVCOPD_SHIFT = 26,
118 PLL_FOUTPOSTDIVPD_SHIFT = 25,
119 PLL_DACPD_SHIFT = 24,
120 PLL_FRAC_DIV = 0xffffff,
121
122 /* CRU_MODE */
123 PLLMUX_FROM_XIN24M = 0,
124 PLLMUX_FROM_PLL,
125 PLLMUX_FROM_RTC32K,
126 USBPHY480M_MODE_SHIFT = 8,
127 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
128 VPLL1_MODE_SHIFT = 6,
129 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
130 VPLL0_MODE_SHIFT = 4,
131 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
132 DPLL_MODE_SHIFT = 2,
133 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
134 APLL_MODE_SHIFT = 0,
135 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
136
137 /* CRU_CLK_SEL0_CON */
138 CORE_ACLK_DIV_SHIFT = 12,
139 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
140 CORE_DBG_DIV_SHIFT = 8,
141 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
142 CORE_CLK_PLL_SEL_SHIFT = 6,
143 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
144 CORE_CLK_PLL_SEL_APLL = 0,
145 CORE_CLK_PLL_SEL_VPLL0,
146 CORE_CLK_PLL_SEL_VPLL1,
147 CORE_DIV_CON_SHIFT = 0,
148 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
149
Finley Xiao37241492024-04-08 18:14:04 +0000[diff] [blame]150 /* CRU_CLK_SEL2_CON */
151 CLK_RTC32K_SEL_SHIFT = 8,
152 CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT,
153 CLK_RTC32K_IO = 0,
154 CLK_RTC32K_PVTM,
155 CLK_RTC32K_FRAC_DIV,
156 CLK_RTC32K_DIV,
157
158 /* CRU_CLK_SEL3_CON */
159 CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16,
160 CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
161 CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
162 CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
163
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]164 /* CRU_CLK_SEL5_CON */
165 BUS_PLL_SEL_SHIFT = 6,
166 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
167 BUS_PLL_SEL_DPLL = 0,
168 BUS_PLL_SEL_VPLL0,
169 BUS_PLL_SEL_VPLL1,
170 BUS_ACLK_DIV_SHIFT = 0,
171 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
172
173 /* CRU_CLK_SEL6_CON */
174 BUS_PCLK_DIV_SHIFT = 8,
175 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
176 BUS_HCLK_DIV_SHIFT = 0,
177 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
178
179 /* CRU_CLK_SEL7_CON */
180 CRYPTO_APK_SEL_SHIFT = 14,
181 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
182 CRYPTO_PLL_SEL_DPLL = 0,
183 CRYPTO_PLL_SEL_VPLL0,
184 CRYPTO_PLL_SEL_VPLL1 = 0,
185 CRYPTO_APK_DIV_SHIFT = 8,
186 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
187 CRYPTO_PLL_SEL_SHIFT = 6,
188 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
189 CRYPTO_DIV_SHIFT = 0,
190 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
191
192 /* CRU_CLK_SEL8_CON */
193 DCLK_VOP_SEL_SHIFT = 14,
194 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
195 DCLK_VOP_SEL_DIVOUT = 0,
196 DCLK_VOP_SEL_FRACOUT,
197 DCLK_VOP_SEL_24M,
198 DCLK_VOP_PLL_SEL_SHIFT = 10,
199 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
200 DCLK_VOP_PLL_SEL_DPLL = 0,
201 DCLK_VOP_PLL_SEL_VPLL0,
202 DCLK_VOP_PLL_SEL_VPLL1,
203 DCLK_VOP_DIV_SHIFT = 0,
204 DCLK_VOP_DIV_MASK = 0xff,
205
Massimo Pegorer2d7b0d02023-08-03 13:08:12 +0200[diff] [blame]206 /* CRU_CLKSEL_CON10 */
207 /* CRU_CLKSEL_CON13 */
208 /* CRU_CLKSEL_CON16 */
209 /* CRU_CLKSEL_CON19 */
210 /* CRU_CLKSEL_CON22 */
211 CLK_UART_PLL_SEL_SHIFT = 13,
212 CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
213 CLK_UART_PLL_SEL_DPLL = 0,
214 CLK_UART_PLL_SEL_VPLL0,
215 CLK_UART_PLL_SEL_VPLL1,
216 CLK_UART_PLL_SEL_480M,
217 CLK_UART_PLL_SEL_24M,
218 CLK_UART_DIV_CON_SHIFT = 0,
219 CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
220
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]221 /* CRU_CLK_SEL25_CON */
222 /* CRU_CLK_SEL26_CON */
223 /* CRU_CLK_SEL27_CON */
224 /* CRU_CLK_SEL28_CON */
225 CLK_I2C_PLL_SEL_SHIFT = 14,
226 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
227 CLK_I2C_PLL_SEL_DPLL = 0,
228 CLK_I2C_PLL_SEL_VPLL0,
229 CLK_I2C_PLL_SEL_24M,
230 CLK_I2C_DIV_CON_SHIFT = 0,
231 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
232
233 /* CRU_CLK_SEL29_CON */
234 CLK_PWM_PLL_SEL_SHIFT = 14,
235 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
236 CLK_PWM_PLL_SEL_DPLL = 0,
237 CLK_PWM_PLL_SEL_VPLL0,
238 CLK_PWM_PLL_SEL_24M,
239 CLK_PWM_DIV_CON_SHIFT = 0,
240 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
241
242 /* CRU_CLK_SEL30_CON */
243 /* CRU_CLK_SEL31_CON */
244 /* CRU_CLK_SEL32_CON */
245 CLK_SPI_PLL_SEL_SHIFT = 14,
246 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
247 CLK_SPI_PLL_SEL_DPLL = 0,
248 CLK_SPI_PLL_SEL_VPLL0,
249 CLK_SPI_PLL_SEL_24M,
250 CLK_SPI_DIV_CON_SHIFT = 0,
251 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
252
253 /* CRU_CLK_SEL34_CON */
254 CLK_SARADC_DIV_CON_SHIFT = 0,
255 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
256
257 /* CRU_CLK_SEL36_CON */
258 PERI_PLL_SEL_SHIFT = 6,
259 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
260 PERI_PLL_DPLL = 0,
261 PERI_PLL_VPLL0,
262 PERI_PLL_VPLL1,
263 PERI_ACLK_DIV_SHIFT = 0,
264 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
265
266 /* CRU_CLK_SEL37_CON */
267 PERI_PCLK_DIV_SHIFT = 8,
268 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
269 PERI_HCLK_DIV_SHIFT = 0,
270 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
271
272 /* CRU_CLKSEL41_CON */
273 EMMC_CLK_SEL_SHIFT = 15,
274 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
275 EMMC_CLK_SEL_EMMC = 0,
276 EMMC_CLK_SEL_EMMC_DIV50,
277 EMMC_PLL_SHIFT = 8,
278 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
279 EMMC_SEL_DPLL = 0,
280 EMMC_SEL_VPLL0,
281 EMMC_SEL_VPLL1,
282 EMMC_SEL_24M,
283 EMMC_DIV_SHIFT = 0,
284 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
285
286 /* CRU_CLKSEL43_CON */
287 MAC_CLK_SPEED_SEL_SHIFT = 15,
288 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
289 MAC_CLK_SPEED_SEL_10M = 0,
290 MAC_CLK_SPEED_SEL_100M,
291 MAC_CLK_SOURCE_SEL_SHIFT = 14,
292 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
293 MAC_CLK_SOURCE_SEL_INTERNAL = 0,
294 MAC_CLK_SOURCE_SEL_EXTERNAL,
295 MAC_PLL_SHIFT = 6,
296 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
297 MAC_SEL_DPLL = 0,
298 MAC_SEL_VPLL0,
299 MAC_SEL_VPLL1,
300 MAC_DIV_SHIFT = 0,
301 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
302
303 /* CRU_CLK_SEL45_CON */
304 AUDIO_PCLK_DIV_SHIFT = 8,
305 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
306 AUDIO_PLL_SEL_SHIFT = 6,
307 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
308 AUDIO_PLL_VPLL0 = 0,
309 AUDIO_PLL_VPLL1,
310 AUDIO_PLL_24M,
311 AUDIO_HCLK_DIV_SHIFT = 0,
312 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
313};
314
315check_member(rk3308_cru, emmc_con[1], 0x494);
316
317#endif