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git01.mediatek.com / filogic / uboot / 2d7b0d0937345f4ac67284039177d9db8113505c / . / arch / arm / include / asm / arch-rk3308 / cru_rk3308.h
blob: 84b63e4d5682b94aca7e55f41f9b397b374a14b9 [file] [log] [blame]
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
4 */
5#ifndef _ASM_ARCH_CRU_RK3308_H
6#define _ASM_ARCH_CRU_RK3308_H
7
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]8#define MHz 1000000
9#define OSC_HZ (24 * MHz)
10
11#define APLL_HZ (816 * MHz)
12
13#define CORE_ACLK_HZ 408000000
14#define CORE_DBG_HZ 204000000
15
16#define BUS_ACLK_HZ 200000000
17#define BUS_HCLK_HZ 100000000
18#define BUS_PCLK_HZ 100000000
19
20#define PERI_ACLK_HZ 200000000
21#define PERI_HCLK_HZ 100000000
22#define PERI_PCLK_HZ 100000000
23
24#define AUDIO_HCLK_HZ 100000000
25#define AUDIO_PCLK_HZ 100000000
26
27#define RK3308_PLL_CON(x) ((x) * 0x4)
28#define RK3308_MODE_CON 0xa0
29
30/* RK3308 pll id */
31enum rk3308_pll_id {
32 APLL,
33 DPLL,
34 VPLL0,
35 VPLL1,
36 PLL_COUNT,
37};
38
39struct rk3308_clk_info {
40 unsigned long id;
41 char *name;
42};
43
44/* Private data for the clock driver - used by rockchip_get_cru() */
45struct rk3308_clk_priv {
46 struct rk3308_cru *cru;
47 ulong armclk_hz;
48 ulong dpll_hz;
49 ulong vpll0_hz;
50 ulong vpll1_hz;
51};
52
53struct rk3308_cru {
54 struct rk3308_pll {
55 unsigned int con0;
56 unsigned int con1;
57 unsigned int con2;
58 unsigned int con3;
59 unsigned int con4;
60 unsigned int reserved0[3];
61 } pll[4];
62 unsigned int reserved1[8];
63 unsigned int mode;
64 unsigned int misc;
65 unsigned int reserved2[2];
66 unsigned int glb_cnt_th;
67 unsigned int glb_rst_st;
68 unsigned int glb_srst_fst;
69 unsigned int glb_srst_snd;
70 unsigned int glb_rst_con;
71 unsigned int pll_lock;
72 unsigned int reserved3[6];
73 unsigned int hwffc_con0;
74 unsigned int reserved4;
75 unsigned int hwffc_th;
76 unsigned int hwffc_intst;
77 unsigned int apll_con0_s;
78 unsigned int apll_con1_s;
79 unsigned int clksel_con0_s;
80 unsigned int reserved5;
81 unsigned int clksel_con[74];
82 unsigned int reserved6[54];
83 unsigned int clkgate_con[15];
84 unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
85 unsigned int ssgtbl[32];
86 unsigned int softrst_con[10];
87 unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
88 unsigned int sdmmc_con[2];
89 unsigned int sdio_con[2];
90 unsigned int emmc_con[2];
91};
92
93enum {
94 /* PLLCON0*/
95 PLL_BP_SHIFT = 15,
96 PLL_POSTDIV1_SHIFT = 12,
97 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
98 PLL_FBDIV_SHIFT = 0,
99 PLL_FBDIV_MASK = 0xfff,
100
101 /* PLLCON1 */
102 PLL_PDSEL_SHIFT = 15,
103 PLL_PD1_SHIFT = 14,
104 PLL_PD_SHIFT = 13,
105 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
106 PLL_DSMPD_SHIFT = 12,
107 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
108 PLL_LOCK_STATUS_SHIFT = 10,
109 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
110 PLL_POSTDIV2_SHIFT = 6,
111 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
112 PLL_REFDIV_SHIFT = 0,
113 PLL_REFDIV_MASK = 0x3f,
114
115 /* PLLCON2 */
116 PLL_FOUT4PHASEPD_SHIFT = 27,
117 PLL_FOUTVCOPD_SHIFT = 26,
118 PLL_FOUTPOSTDIVPD_SHIFT = 25,
119 PLL_DACPD_SHIFT = 24,
120 PLL_FRAC_DIV = 0xffffff,
121
122 /* CRU_MODE */
123 PLLMUX_FROM_XIN24M = 0,
124 PLLMUX_FROM_PLL,
125 PLLMUX_FROM_RTC32K,
126 USBPHY480M_MODE_SHIFT = 8,
127 USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
128 VPLL1_MODE_SHIFT = 6,
129 VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
130 VPLL0_MODE_SHIFT = 4,
131 VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
132 DPLL_MODE_SHIFT = 2,
133 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
134 APLL_MODE_SHIFT = 0,
135 APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
136
137 /* CRU_CLK_SEL0_CON */
138 CORE_ACLK_DIV_SHIFT = 12,
139 CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
140 CORE_DBG_DIV_SHIFT = 8,
141 CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
142 CORE_CLK_PLL_SEL_SHIFT = 6,
143 CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
144 CORE_CLK_PLL_SEL_APLL = 0,
145 CORE_CLK_PLL_SEL_VPLL0,
146 CORE_CLK_PLL_SEL_VPLL1,
147 CORE_DIV_CON_SHIFT = 0,
148 CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
149
150 /* CRU_CLK_SEL5_CON */
151 BUS_PLL_SEL_SHIFT = 6,
152 BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
153 BUS_PLL_SEL_DPLL = 0,
154 BUS_PLL_SEL_VPLL0,
155 BUS_PLL_SEL_VPLL1,
156 BUS_ACLK_DIV_SHIFT = 0,
157 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
158
159 /* CRU_CLK_SEL6_CON */
160 BUS_PCLK_DIV_SHIFT = 8,
161 BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
162 BUS_HCLK_DIV_SHIFT = 0,
163 BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
164
165 /* CRU_CLK_SEL7_CON */
166 CRYPTO_APK_SEL_SHIFT = 14,
167 CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
168 CRYPTO_PLL_SEL_DPLL = 0,
169 CRYPTO_PLL_SEL_VPLL0,
170 CRYPTO_PLL_SEL_VPLL1 = 0,
171 CRYPTO_APK_DIV_SHIFT = 8,
172 CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
173 CRYPTO_PLL_SEL_SHIFT = 6,
174 CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
175 CRYPTO_DIV_SHIFT = 0,
176 CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
177
178 /* CRU_CLK_SEL8_CON */
179 DCLK_VOP_SEL_SHIFT = 14,
180 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
181 DCLK_VOP_SEL_DIVOUT = 0,
182 DCLK_VOP_SEL_FRACOUT,
183 DCLK_VOP_SEL_24M,
184 DCLK_VOP_PLL_SEL_SHIFT = 10,
185 DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
186 DCLK_VOP_PLL_SEL_DPLL = 0,
187 DCLK_VOP_PLL_SEL_VPLL0,
188 DCLK_VOP_PLL_SEL_VPLL1,
189 DCLK_VOP_DIV_SHIFT = 0,
190 DCLK_VOP_DIV_MASK = 0xff,
191
Massimo Pegorer2d7b0d02023-08-03 13:08:12 +0200[diff] [blame^]192 /* CRU_CLKSEL_CON10 */
193 /* CRU_CLKSEL_CON13 */
194 /* CRU_CLKSEL_CON16 */
195 /* CRU_CLKSEL_CON19 */
196 /* CRU_CLKSEL_CON22 */
197 CLK_UART_PLL_SEL_SHIFT = 13,
198 CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
199 CLK_UART_PLL_SEL_DPLL = 0,
200 CLK_UART_PLL_SEL_VPLL0,
201 CLK_UART_PLL_SEL_VPLL1,
202 CLK_UART_PLL_SEL_480M,
203 CLK_UART_PLL_SEL_24M,
204 CLK_UART_DIV_CON_SHIFT = 0,
205 CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
206
Andy Yanb5e16302019-11-14 11:21:12 +0800[diff] [blame]207 /* CRU_CLK_SEL25_CON */
208 /* CRU_CLK_SEL26_CON */
209 /* CRU_CLK_SEL27_CON */
210 /* CRU_CLK_SEL28_CON */
211 CLK_I2C_PLL_SEL_SHIFT = 14,
212 CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
213 CLK_I2C_PLL_SEL_DPLL = 0,
214 CLK_I2C_PLL_SEL_VPLL0,
215 CLK_I2C_PLL_SEL_24M,
216 CLK_I2C_DIV_CON_SHIFT = 0,
217 CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
218
219 /* CRU_CLK_SEL29_CON */
220 CLK_PWM_PLL_SEL_SHIFT = 14,
221 CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
222 CLK_PWM_PLL_SEL_DPLL = 0,
223 CLK_PWM_PLL_SEL_VPLL0,
224 CLK_PWM_PLL_SEL_24M,
225 CLK_PWM_DIV_CON_SHIFT = 0,
226 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
227
228 /* CRU_CLK_SEL30_CON */
229 /* CRU_CLK_SEL31_CON */
230 /* CRU_CLK_SEL32_CON */
231 CLK_SPI_PLL_SEL_SHIFT = 14,
232 CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
233 CLK_SPI_PLL_SEL_DPLL = 0,
234 CLK_SPI_PLL_SEL_VPLL0,
235 CLK_SPI_PLL_SEL_24M,
236 CLK_SPI_DIV_CON_SHIFT = 0,
237 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
238
239 /* CRU_CLK_SEL34_CON */
240 CLK_SARADC_DIV_CON_SHIFT = 0,
241 CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
242
243 /* CRU_CLK_SEL36_CON */
244 PERI_PLL_SEL_SHIFT = 6,
245 PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
246 PERI_PLL_DPLL = 0,
247 PERI_PLL_VPLL0,
248 PERI_PLL_VPLL1,
249 PERI_ACLK_DIV_SHIFT = 0,
250 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
251
252 /* CRU_CLK_SEL37_CON */
253 PERI_PCLK_DIV_SHIFT = 8,
254 PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
255 PERI_HCLK_DIV_SHIFT = 0,
256 PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
257
258 /* CRU_CLKSEL41_CON */
259 EMMC_CLK_SEL_SHIFT = 15,
260 EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
261 EMMC_CLK_SEL_EMMC = 0,
262 EMMC_CLK_SEL_EMMC_DIV50,
263 EMMC_PLL_SHIFT = 8,
264 EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
265 EMMC_SEL_DPLL = 0,
266 EMMC_SEL_VPLL0,
267 EMMC_SEL_VPLL1,
268 EMMC_SEL_24M,
269 EMMC_DIV_SHIFT = 0,
270 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
271
272 /* CRU_CLKSEL43_CON */
273 MAC_CLK_SPEED_SEL_SHIFT = 15,
274 MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
275 MAC_CLK_SPEED_SEL_10M = 0,
276 MAC_CLK_SPEED_SEL_100M,
277 MAC_CLK_SOURCE_SEL_SHIFT = 14,
278 MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
279 MAC_CLK_SOURCE_SEL_INTERNAL = 0,
280 MAC_CLK_SOURCE_SEL_EXTERNAL,
281 MAC_PLL_SHIFT = 6,
282 MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
283 MAC_SEL_DPLL = 0,
284 MAC_SEL_VPLL0,
285 MAC_SEL_VPLL1,
286 MAC_DIV_SHIFT = 0,
287 MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
288
289 /* CRU_CLK_SEL45_CON */
290 AUDIO_PCLK_DIV_SHIFT = 8,
291 AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
292 AUDIO_PLL_SEL_SHIFT = 6,
293 AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
294 AUDIO_PLL_VPLL0 = 0,
295 AUDIO_PLL_VPLL1,
296 AUDIO_PLL_24M,
297 AUDIO_HCLK_DIV_SHIFT = 0,
298 AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
299};
300
301check_member(rk3308_cru, emmc_con[1], 0x494);
302
303#endif