clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
index 86c906b..84b63e4 100644
--- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -189,6 +189,21 @@
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
+ /* CRU_CLKSEL_CON10 */
+ /* CRU_CLKSEL_CON13 */
+ /* CRU_CLKSEL_CON16 */
+ /* CRU_CLKSEL_CON19 */
+ /* CRU_CLKSEL_CON22 */
+ CLK_UART_PLL_SEL_SHIFT = 13,
+ CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
+ CLK_UART_PLL_SEL_DPLL = 0,
+ CLK_UART_PLL_SEL_VPLL0,
+ CLK_UART_PLL_SEL_VPLL1,
+ CLK_UART_PLL_SEL_480M,
+ CLK_UART_PLL_SEL_24M,
+ CLK_UART_DIV_CON_SHIFT = 0,
+ CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
+
/* CRU_CLK_SEL25_CON */
/* CRU_CLK_SEL26_CON */
/* CRU_CLK_SEL27_CON */