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git01.mediatek.com / filogic / uboot / b0d9163a1b390eee27369f3d8cbc3857fbd4ab90 / . / arch / arm / include / asm / arch-exynos / clock.h
blob: 9b56b4e51bf09d1b8c8783f8d4d201fc4650e682 [file] [log] [blame]
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]1/*
2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
22#ifndef __ASM_ARM_ARCH_CLOCK_H_
23#define __ASM_ARM_ARCH_CLOCK_H_
24
25#ifndef __ASSEMBLY__
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]26struct exynos4_clock {
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]27 unsigned char res1[0x4200];
28 unsigned int src_leftbus;
29 unsigned char res2[0x1fc];
30 unsigned int mux_stat_leftbus;
31 unsigned char res4[0xfc];
32 unsigned int div_leftbus;
33 unsigned char res5[0xfc];
34 unsigned int div_stat_leftbus;
35 unsigned char res6[0x1fc];
36 unsigned int gate_ip_leftbus;
37 unsigned char res7[0x1fc];
38 unsigned int clkout_leftbus;
39 unsigned int clkout_leftbus_div_stat;
40 unsigned char res8[0x37f8];
41 unsigned int src_rightbus;
42 unsigned char res9[0x1fc];
43 unsigned int mux_stat_rightbus;
44 unsigned char res10[0xfc];
45 unsigned int div_rightbus;
46 unsigned char res11[0xfc];
47 unsigned int div_stat_rightbus;
48 unsigned char res12[0x1fc];
49 unsigned int gate_ip_rightbus;
50 unsigned char res13[0x1fc];
51 unsigned int clkout_rightbus;
52 unsigned int clkout_rightbus_div_stat;
53 unsigned char res14[0x3608];
54 unsigned int epll_lock;
55 unsigned char res15[0xc];
56 unsigned int vpll_lock;
57 unsigned char res16[0xec];
58 unsigned int epll_con0;
59 unsigned int epll_con1;
60 unsigned char res17[0x8];
61 unsigned int vpll_con0;
62 unsigned int vpll_con1;
63 unsigned char res18[0xe8];
64 unsigned int src_top0;
65 unsigned int src_top1;
66 unsigned char res19[0x8];
67 unsigned int src_cam;
68 unsigned int src_tv;
69 unsigned int src_mfc;
70 unsigned int src_g3d;
71 unsigned int src_image;
72 unsigned int src_lcd0;
73 unsigned int src_lcd1;
74 unsigned int src_maudio;
75 unsigned int src_fsys;
76 unsigned char res20[0xc];
77 unsigned int src_peril0;
78 unsigned int src_peril1;
79 unsigned char res21[0xb8];
80 unsigned int src_mask_top;
81 unsigned char res22[0xc];
82 unsigned int src_mask_cam;
83 unsigned int src_mask_tv;
84 unsigned char res23[0xc];
85 unsigned int src_mask_lcd0;
86 unsigned int src_mask_lcd1;
87 unsigned int src_mask_maudio;
88 unsigned int src_mask_fsys;
89 unsigned char res24[0xc];
90 unsigned int src_mask_peril0;
91 unsigned int src_mask_peril1;
92 unsigned char res25[0xb8];
93 unsigned int mux_stat_top;
94 unsigned char res26[0x14];
95 unsigned int mux_stat_mfc;
96 unsigned int mux_stat_g3d;
97 unsigned int mux_stat_image;
98 unsigned char res27[0xdc];
99 unsigned int div_top;
100 unsigned char res28[0xc];
101 unsigned int div_cam;
102 unsigned int div_tv;
103 unsigned int div_mfc;
104 unsigned int div_g3d;
105 unsigned int div_image;
106 unsigned int div_lcd0;
107 unsigned int div_lcd1;
108 unsigned int div_maudio;
109 unsigned int div_fsys0;
110 unsigned int div_fsys1;
111 unsigned int div_fsys2;
112 unsigned int div_fsys3;
113 unsigned int div_peril0;
114 unsigned int div_peril1;
115 unsigned int div_peril2;
116 unsigned int div_peril3;
117 unsigned int div_peril4;
118 unsigned int div_peril5;
119 unsigned char res29[0x18];
120 unsigned int div2_ratio;
121 unsigned char res30[0x8c];
122 unsigned int div_stat_top;
123 unsigned char res31[0xc];
124 unsigned int div_stat_cam;
125 unsigned int div_stat_tv;
126 unsigned int div_stat_mfc;
127 unsigned int div_stat_g3d;
128 unsigned int div_stat_image;
129 unsigned int div_stat_lcd0;
130 unsigned int div_stat_lcd1;
131 unsigned int div_stat_maudio;
132 unsigned int div_stat_fsys0;
133 unsigned int div_stat_fsys1;
134 unsigned int div_stat_fsys2;
135 unsigned int div_stat_fsys3;
136 unsigned int div_stat_peril0;
137 unsigned int div_stat_peril1;
138 unsigned int div_stat_peril2;
139 unsigned int div_stat_peril3;
140 unsigned int div_stat_peril4;
141 unsigned int div_stat_peril5;
142 unsigned char res32[0x18];
143 unsigned int div2_stat;
144 unsigned char res33[0x29c];
145 unsigned int gate_ip_cam;
146 unsigned int gate_ip_tv;
147 unsigned int gate_ip_mfc;
148 unsigned int gate_ip_g3d;
149 unsigned int gate_ip_image;
150 unsigned int gate_ip_lcd0;
151 unsigned int gate_ip_lcd1;
152 unsigned char res34[0x4];
153 unsigned int gate_ip_fsys;
154 unsigned char res35[0x8];
155 unsigned int gate_ip_gps;
156 unsigned int gate_ip_peril;
157 unsigned char res36[0xc];
158 unsigned int gate_ip_perir;
159 unsigned char res37[0xc];
160 unsigned int gate_block;
161 unsigned char res38[0x8c];
162 unsigned int clkout_cmu_top;
163 unsigned int clkout_cmu_top_div_stat;
164 unsigned char res39[0x37f8];
165 unsigned int src_dmc;
166 unsigned char res40[0xfc];
167 unsigned int src_mask_dmc;
168 unsigned char res41[0xfc];
169 unsigned int mux_stat_dmc;
170 unsigned char res42[0xfc];
171 unsigned int div_dmc0;
172 unsigned int div_dmc1;
173 unsigned char res43[0xf8];
174 unsigned int div_stat_dmc0;
175 unsigned int div_stat_dmc1;
176 unsigned char res44[0x2f8];
177 unsigned int gate_ip_dmc;
178 unsigned char res45[0xfc];
179 unsigned int clkout_cmu_dmc;
180 unsigned int clkout_cmu_dmc_div_stat;
181 unsigned char res46[0x5f8];
182 unsigned int dcgidx_map0;
183 unsigned int dcgidx_map1;
184 unsigned int dcgidx_map2;
185 unsigned char res47[0x14];
186 unsigned int dcgperf_map0;
187 unsigned int dcgperf_map1;
188 unsigned char res48[0x18];
189 unsigned int dvcidx_map;
190 unsigned char res49[0x1c];
191 unsigned int freq_cpu;
192 unsigned int freq_dpm;
193 unsigned char res50[0x18];
194 unsigned int dvsemclk_en;
195 unsigned int maxperf;
196 unsigned char res51[0x2f78];
197 unsigned int apll_lock;
198 unsigned char res52[0x4];
199 unsigned int mpll_lock;
200 unsigned char res53[0xf4];
201 unsigned int apll_con0;
202 unsigned int apll_con1;
203 unsigned int mpll_con0;
204 unsigned int mpll_con1;
205 unsigned char res54[0xf0];
206 unsigned int src_cpu;
207 unsigned char res55[0x1fc];
208 unsigned int mux_stat_cpu;
209 unsigned char res56[0xfc];
210 unsigned int div_cpu0;
211 unsigned int div_cpu1;
212 unsigned char res57[0xf8];
213 unsigned int div_stat_cpu0;
214 unsigned int div_stat_cpu1;
215 unsigned char res58[0x3f8];
216 unsigned int clkout_cmu_cpu;
217 unsigned int clkout_cmu_cpu_div_stat;
218 unsigned char res59[0x5f8];
219 unsigned int armclk_stopctrl;
220 unsigned int atclk_stopctrl;
221 unsigned char res60[0x8];
222 unsigned int parityfail_status;
223 unsigned int parityfail_clear;
224 unsigned char res61[0xe8];
225 unsigned int apll_con0_l8;
226 unsigned int apll_con0_l7;
227 unsigned int apll_con0_l6;
228 unsigned int apll_con0_l5;
229 unsigned int apll_con0_l4;
230 unsigned int apll_con0_l3;
231 unsigned int apll_con0_l2;
232 unsigned int apll_con0_l1;
233 unsigned int iem_control;
234 unsigned char res62[0xdc];
235 unsigned int apll_con1_l8;
236 unsigned int apll_con1_l7;
237 unsigned int apll_con1_l6;
238 unsigned int apll_con1_l5;
239 unsigned int apll_con1_l4;
240 unsigned int apll_con1_l3;
241 unsigned int apll_con1_l2;
242 unsigned int apll_con1_l1;
243 unsigned char res63[0xe0];
244 unsigned int div_iem_l8;
245 unsigned int div_iem_l7;
246 unsigned int div_iem_l6;
247 unsigned int div_iem_l5;
248 unsigned int div_iem_l4;
249 unsigned int div_iem_l3;
250 unsigned int div_iem_l2;
251 unsigned int div_iem_l1;
252};
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]253
Chander Kashyap8625f102012-12-25 20:13:40 +0000[diff] [blame]254struct exynos4x12_clock {
255 unsigned char res1[0x4200];
256 unsigned int src_leftbus;
257 unsigned char res2[0x1fc];
258 unsigned int mux_stat_leftbus;
259 unsigned char res3[0xfc];
260 unsigned int div_leftbus;
261 unsigned char res4[0xfc];
262 unsigned int div_stat_leftbus;
263 unsigned char res5[0x1fc];
264 unsigned int gate_ip_leftbus;
265 unsigned char res6[0x12c];
266 unsigned int gate_ip_image;
267 unsigned char res7[0xcc];
268 unsigned int clkout_leftbus;
269 unsigned int clkout_leftbus_div_stat;
270 unsigned char res8[0x37f8];
271 unsigned int src_rightbus;
272 unsigned char res9[0x1fc];
273 unsigned int mux_stat_rightbus;
274 unsigned char res10[0xfc];
275 unsigned int div_rightbus;
276 unsigned char res11[0xfc];
277 unsigned int div_stat_rightbus;
278 unsigned char res12[0x1fc];
279 unsigned int gate_ip_rightbus;
280 unsigned char res13[0x15c];
281 unsigned int gate_ip_perir;
282 unsigned char res14[0x9c];
283 unsigned int clkout_rightbus;
284 unsigned int clkout_rightbus_div_stat;
285 unsigned char res15[0x3608];
286 unsigned int epll_lock;
287 unsigned char res16[0xc];
288 unsigned int vpll_lock;
289 unsigned char res17[0xec];
290 unsigned int epll_con0;
291 unsigned int epll_con1;
292 unsigned int epll_con2;
293 unsigned char res18[0x4];
294 unsigned int vpll_con0;
295 unsigned int vpll_con1;
296 unsigned int vpll_con2;
297 unsigned char res19[0xe4];
298 unsigned int src_top0;
299 unsigned int src_top1;
300 unsigned char res20[0x8];
301 unsigned int src_cam;
302 unsigned int src_tv;
303 unsigned int src_mfc;
304 unsigned int src_g3d;
305 unsigned char res21[0x4];
306 unsigned int src_lcd;
307 unsigned int src_isp;
308 unsigned int src_maudio;
309 unsigned int src_fsys;
310 unsigned char res22[0xc];
311 unsigned int src_peril0;
312 unsigned int src_peril1;
313 unsigned int src_cam1;
314 unsigned char res23[0xb4];
315 unsigned int src_mask_top;
316 unsigned char res24[0xc];
317 unsigned int src_mask_cam;
318 unsigned int src_mask_tv;
319 unsigned char res25[0xc];
320 unsigned int src_mask_lcd;
321 unsigned int src_mask_isp;
322 unsigned int src_mask_maudio;
323 unsigned int src_mask_fsys;
324 unsigned char res26[0xc];
325 unsigned int src_mask_peril0;
326 unsigned int src_mask_peril1;
327 unsigned char res27[0xb8];
328 unsigned int mux_stat_top0;
329 unsigned int mux_stat_top1;
330 unsigned char res28[0x10];
331 unsigned int mux_stat_mfc;
332 unsigned int mux_stat_g3d;
333 unsigned char res29[0x28];
334 unsigned int mux_stat_cam1;
335 unsigned char res30[0xb4];
336 unsigned int div_top;
337 unsigned char res31[0xc];
338 unsigned int div_cam;
339 unsigned int div_tv;
340 unsigned int div_mfc;
341 unsigned int div_g3d;
342 unsigned char res32[0x4];
343 unsigned int div_lcd;
344 unsigned int div_isp;
345 unsigned int div_maudio;
346 unsigned int div_fsys0;
347 unsigned int div_fsys1;
348 unsigned int div_fsys2;
349 unsigned int div_fsys3;
350 unsigned int div_peril0;
351 unsigned int div_peril1;
352 unsigned int div_peril2;
353 unsigned int div_peril3;
354 unsigned int div_peril4;
355 unsigned int div_peril5;
356 unsigned int div_cam1;
357 unsigned char res33[0x14];
358 unsigned int div2_ratio;
359 unsigned char res34[0x8c];
360 unsigned int div_stat_top;
361 unsigned char res35[0xc];
362 unsigned int div_stat_cam;
363 unsigned int div_stat_tv;
364 unsigned int div_stat_mfc;
365 unsigned int div_stat_g3d;
366 unsigned char res36[0x4];
367 unsigned int div_stat_lcd;
368 unsigned int div_stat_isp;
369 unsigned int div_stat_maudio;
370 unsigned int div_stat_fsys0;
371 unsigned int div_stat_fsys1;
372 unsigned int div_stat_fsys2;
373 unsigned int div_stat_fsys3;
374 unsigned int div_stat_peril0;
375 unsigned int div_stat_peril1;
376 unsigned int div_stat_peril2;
377 unsigned int div_stat_peril3;
378 unsigned int div_stat_peril4;
379 unsigned int div_stat_peril5;
380 unsigned int div_stat_cam1;
381 unsigned char res37[0x14];
382 unsigned int div2_stat;
383 unsigned char res38[0x29c];
384 unsigned int gate_ip_cam;
385 unsigned int gate_ip_tv;
386 unsigned int gate_ip_mfc;
387 unsigned int gate_ip_g3d;
388 unsigned char res39[0x4];
389 unsigned int gate_ip_lcd;
390 unsigned int gate_ip_isp;
391 unsigned char res40[0x4];
392 unsigned int gate_ip_fsys;
393 unsigned char res41[0x8];
394 unsigned int gate_ip_gps;
395 unsigned int gate_ip_peril;
396 unsigned char res42[0xc];
397 unsigned char res43[0x4];
398 unsigned char res44[0xc];
399 unsigned int gate_block;
400 unsigned char res45[0x8c];
401 unsigned int clkout_cmu_top;
402 unsigned int clkout_cmu_top_div_stat;
403 unsigned char res46[0x3600];
404 unsigned int mpll_lock;
405 unsigned char res47[0xfc];
406 unsigned int mpll_con0;
407 unsigned int mpll_con1;
408 unsigned char res48[0xf0];
409 unsigned int src_dmc;
410 unsigned char res49[0xfc];
411 unsigned int src_mask_dmc;
412 unsigned char res50[0xfc];
413 unsigned int mux_stat_dmc;
414 unsigned char res51[0xfc];
415 unsigned int div_dmc0;
416 unsigned int div_dmc1;
417 unsigned char res52[0xf8];
418 unsigned int div_stat_dmc0;
419 unsigned int div_stat_dmc1;
420 unsigned char res53[0xf8];
421 unsigned int gate_bus_dmc0;
422 unsigned int gate_bus_dmc1;
423 unsigned char res54[0x1f8];
424 unsigned int gate_ip_dmc0;
425 unsigned int gate_ip_dmc1;
426 unsigned char res55[0xf8];
427 unsigned int clkout_cmu_dmc;
428 unsigned int clkout_cmu_dmc_div_stat;
429 unsigned char res56[0x5f8];
430 unsigned int dcgidx_map0;
431 unsigned int dcgidx_map1;
432 unsigned int dcgidx_map2;
433 unsigned char res57[0x14];
434 unsigned int dcgperf_map0;
435 unsigned int dcgperf_map1;
436 unsigned char res58[0x18];
437 unsigned int dvcidx_map;
438 unsigned char res59[0x1c];
439 unsigned int freq_cpu;
440 unsigned int freq_dpm;
441 unsigned char res60[0x18];
442 unsigned int dvsemclk_en;
443 unsigned int maxperf;
444 unsigned char res61[0x8];
445 unsigned int dmc_freq_ctrl;
446 unsigned int dmc_pause_ctrl;
447 unsigned int dddrphy_lock_ctrl;
448 unsigned int c2c_state;
449 unsigned char res62[0x2f60];
450 unsigned int apll_lock;
451 unsigned char res63[0x8];
452 unsigned char res64[0xf4];
453 unsigned int apll_con0;
454 unsigned int apll_con1;
455 unsigned char res65[0xf8];
456 unsigned int src_cpu;
457 unsigned char res66[0x1fc];
458 unsigned int mux_stat_cpu;
459 unsigned char res67[0xfc];
460 unsigned int div_cpu0;
461 unsigned int div_cpu1;
462 unsigned char res68[0xf8];
463 unsigned int div_stat_cpu0;
464 unsigned int div_stat_cpu1;
465 unsigned char res69[0x2f8];
466 unsigned int clk_gate_ip_cpu;
467 unsigned char res70[0xfc];
468 unsigned int clkout_cmu_cpu;
469 unsigned int clkout_cmu_cpu_div_stat;
470 unsigned char res71[0x5f8];
471 unsigned int armclk_stopctrl;
472 unsigned int atclk_stopctrl;
473 unsigned char res72[0x10];
474 unsigned char res73[0x8];
475 unsigned int pwr_ctrl;
476 unsigned int pwr_ctrl2;
477 unsigned char res74[0xd8];
478 unsigned int apll_con0_l8;
479 unsigned int apll_con0_l7;
480 unsigned int apll_con0_l6;
481 unsigned int apll_con0_l5;
482 unsigned int apll_con0_l4;
483 unsigned int apll_con0_l3;
484 unsigned int apll_con0_l2;
485 unsigned int apll_con0_l1;
486 unsigned int iem_control;
487 unsigned char res75[0xdc];
488 unsigned int apll_con1_l8;
489 unsigned int apll_con1_l7;
490 unsigned int apll_con1_l6;
491 unsigned int apll_con1_l5;
492 unsigned int apll_con1_l4;
493 unsigned int apll_con1_l3;
494 unsigned int apll_con1_l2;
495 unsigned int apll_con1_l1;
496 unsigned char res76[0xe0];
497 unsigned int div_iem_l8;
498 unsigned int div_iem_l7;
499 unsigned int div_iem_l6;
500 unsigned int div_iem_l5;
501 unsigned int div_iem_l4;
502 unsigned int div_iem_l3;
503 unsigned int div_iem_l2;
504 unsigned int div_iem_l1;
505 unsigned char res77[0xe0];
506 unsigned int l2_status;
507 unsigned char res78[0xc];
508 unsigned int cpu_status;
509 unsigned char res79[0xc];
510 unsigned int ptm_status;
511 unsigned char res80[0x2edc];
512 unsigned int div_isp0;
513 unsigned int div_isp1;
514 unsigned char res81[0xf8];
515 unsigned int div_stat_isp0;
516 unsigned int div_stat_isp1;
517 unsigned char res82[0x3f8];
518 unsigned int gate_ip_isp0;
519 unsigned int gate_ip_isp1;
520 unsigned char res83[0x1f8];
521 unsigned int clkout_cmu_isp;
522 unsigned int clkout_cmu_ispd_div_stat;
523 unsigned char res84[0xf8];
524 unsigned int cmu_isp_spar0;
525 unsigned int cmu_isp_spar1;
526 unsigned int cmu_isp_spar2;
527 unsigned int cmu_isp_spar3;
528};
529
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]530struct exynos5_clock {
531 unsigned int apll_lock;
532 unsigned char res1[0xfc];
533 unsigned int apll_con0;
534 unsigned int apll_con1;
535 unsigned char res2[0xf8];
536 unsigned int src_cpu;
537 unsigned char res3[0x1fc];
538 unsigned int mux_stat_cpu;
539 unsigned char res4[0xfc];
540 unsigned int div_cpu0;
541 unsigned int div_cpu1;
542 unsigned char res5[0xf8];
543 unsigned int div_stat_cpu0;
544 unsigned int div_stat_cpu1;
545 unsigned char res6[0x1f8];
546 unsigned int gate_sclk_cpu;
547 unsigned char res7[0x1fc];
548 unsigned int clkout_cmu_cpu;
549 unsigned int clkout_cmu_cpu_div_stat;
550 unsigned char res8[0x5f8];
551 unsigned int armclk_stopctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]552 unsigned char res9[0x0c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]553 unsigned int parityfail_status;
554 unsigned int parityfail_clear;
555 unsigned char res10[0x8];
556 unsigned int pwr_ctrl;
557 unsigned int pwr_ctr2;
558 unsigned char res11[0xd8];
559 unsigned int apll_con0_l8;
560 unsigned int apll_con0_l7;
561 unsigned int apll_con0_l6;
562 unsigned int apll_con0_l5;
563 unsigned int apll_con0_l4;
564 unsigned int apll_con0_l3;
565 unsigned int apll_con0_l2;
566 unsigned int apll_con0_l1;
567 unsigned int iem_control;
568 unsigned char res12[0xdc];
569 unsigned int apll_con1_l8;
570 unsigned int apll_con1_l7;
571 unsigned int apll_con1_l6;
572 unsigned int apll_con1_l5;
573 unsigned int apll_con1_l4;
574 unsigned int apll_con1_l3;
575 unsigned int apll_con1_l2;
576 unsigned int apll_con1_l1;
577 unsigned char res13[0xe0];
578 unsigned int div_iem_l8;
579 unsigned int div_iem_l7;
580 unsigned int div_iem_l6;
581 unsigned int div_iem_l5;
582 unsigned int div_iem_l4;
583 unsigned int div_iem_l3;
584 unsigned int div_iem_l2;
585 unsigned int div_iem_l1;
586 unsigned char res14[0x2ce0];
587 unsigned int mpll_lock;
588 unsigned char res15[0xfc];
589 unsigned int mpll_con0;
590 unsigned int mpll_con1;
591 unsigned char res16[0xf8];
592 unsigned int src_core0;
593 unsigned int src_core1;
594 unsigned char res17[0xf8];
595 unsigned int src_mask_core;
596 unsigned char res18[0x100];
597 unsigned int mux_stat_core1;
598 unsigned char res19[0xf8];
599 unsigned int div_core0;
600 unsigned int div_core1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]601 unsigned int div_sysrgt;
602 unsigned char res20[0xf4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]603 unsigned int div_stat_core0;
604 unsigned int div_stat_core1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]605 unsigned int div_stat_sysrgt;
606 unsigned char res21[0x2f4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]607 unsigned int gate_ip_core;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]608 unsigned int gate_ip_sysrgt;
609 unsigned char res22[0x8];
610 unsigned int c2c_monitor;
611 unsigned char res23[0xec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]612 unsigned int clkout_cmu_core;
613 unsigned int clkout_cmu_core_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]614 unsigned char res24[0x5f8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]615 unsigned int dcgidx_map0;
616 unsigned int dcgidx_map1;
617 unsigned int dcgidx_map2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]618 unsigned char res25[0x14];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]619 unsigned int dcgperf_map0;
620 unsigned int dcgperf_map1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]621 unsigned char res26[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]622 unsigned int dvcidx_map;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]623 unsigned char res27[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]624 unsigned int freq_cpu;
625 unsigned int freq_dpm;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]626 unsigned char res28[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]627 unsigned int dvsemclk_en;
628 unsigned int maxperf;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]629 unsigned char res29[0xf78];
630 unsigned int c2c_config;
631 unsigned char res30[0x24fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]632 unsigned int div_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]633 unsigned char res31[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]634 unsigned int div_stat_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]635 unsigned char res32[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]636 unsigned int gate_ip_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]637 unsigned char res33[0xfc];
638 unsigned int div_syslft;
639 unsigned char res34[0xc];
640 unsigned int div_stat_syslft;
641 unsigned char res35[0x1c];
642 unsigned int gate_ip_syslft;
643 unsigned char res36[0xcc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]644 unsigned int clkout_cmu_acp;
645 unsigned int clkout_cmu_acp_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]646 unsigned char res37[0x8];
647 unsigned int ufmc_config;
648 unsigned char res38[0x38ec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]649 unsigned int div_isp0;
650 unsigned int div_isp1;
651 unsigned int div_isp2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]652 unsigned char res39[0xf4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]653 unsigned int div_stat_isp0;
654 unsigned int div_stat_isp1;
655 unsigned int div_stat_isp2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]656 unsigned char res40[0x3f4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]657 unsigned int gate_ip_isp0;
658 unsigned int gate_ip_isp1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]659 unsigned char res41[0xf8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]660 unsigned int gate_sclk_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]661 unsigned char res42[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]662 unsigned int mcuisp_pwr_ctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]663 unsigned char res43[0xec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]664 unsigned int clkout_cmu_isp;
665 unsigned int clkout_cmu_isp_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]666 unsigned char res44[0x3618];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]667 unsigned int cpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]668 unsigned char res45[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]669 unsigned int epll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]670 unsigned char res46[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]671 unsigned int vpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]672 unsigned char res47[0xc];
673 unsigned int gpll_lock;
674 unsigned char res48[0xcc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]675 unsigned int cpll_con0;
676 unsigned int cpll_con1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]677 unsigned char res49[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]678 unsigned int epll_con0;
679 unsigned int epll_con1;
680 unsigned int epll_con2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]681 unsigned char res50[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]682 unsigned int vpll_con0;
683 unsigned int vpll_con1;
684 unsigned int vpll_con2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]685 unsigned char res51[0x4];
686 unsigned int gpll_con0;
687 unsigned int gpll_con1;
688 unsigned char res52[0xb8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]689 unsigned int src_top0;
690 unsigned int src_top1;
691 unsigned int src_top2;
692 unsigned int src_top3;
693 unsigned int src_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]694 unsigned char res53[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]695 unsigned int src_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]696 unsigned char res54[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]697 unsigned int src_mau;
698 unsigned int src_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]699 unsigned int src_gen;
700 unsigned char res55[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]701 unsigned int src_peric0;
702 unsigned int src_peric1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]703 unsigned char res56[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]704 unsigned int sclk_src_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]705 unsigned char res57[0x9c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]706 unsigned int src_mask_top;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]707 unsigned char res58[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]708 unsigned int src_mask_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]709 unsigned char res59[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]710 unsigned int src_mask_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]711 unsigned char res60[0x4];
712 unsigned int src_mask_mau;
713 unsigned char res61[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]714 unsigned int src_mask_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]715 unsigned int src_mask_gen;
716 unsigned char res62[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]717 unsigned int src_mask_peric0;
718 unsigned int src_mask_peric1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]719 unsigned char res63[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]720 unsigned int src_mask_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]721 unsigned char res67[0x9c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]722 unsigned int mux_stat_top0;
723 unsigned int mux_stat_top1;
724 unsigned int mux_stat_top2;
725 unsigned int mux_stat_top3;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]726 unsigned char res68[0xf0];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]727 unsigned int div_top0;
728 unsigned int div_top1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]729 unsigned char res69[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]730 unsigned int div_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]731 unsigned char res70[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]732 unsigned int div_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]733 unsigned char res71[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]734 unsigned int div_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]735 unsigned char res72[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]736 unsigned int div_mau;
737 unsigned int div_fsys0;
738 unsigned int div_fsys1;
739 unsigned int div_fsys2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]740 unsigned char res73[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]741 unsigned int div_peric0;
742 unsigned int div_peric1;
743 unsigned int div_peric2;
744 unsigned int div_peric3;
745 unsigned int div_peric4;
746 unsigned int div_peric5;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]747 unsigned char res74[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]748 unsigned int sclk_div_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]749 unsigned char res75[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]750 unsigned int div2_ratio0;
751 unsigned int div2_ratio1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]752 unsigned char res76[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]753 unsigned int div4_ratio;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]754 unsigned char res77[0x6c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]755 unsigned int div_stat_top0;
756 unsigned int div_stat_top1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]757 unsigned char res78[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]758 unsigned int div_stat_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]759 unsigned char res79[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]760 unsigned int div_stat_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]761 unsigned char res80[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]762 unsigned int div_stat_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]763 unsigned char res81[0x4];
764 unsigned int div_stat_mau;
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]765 unsigned int div_stat_fsys0;
766 unsigned int div_stat_fsys1;
767 unsigned int div_stat_fsys2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]768 unsigned char res82[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]769 unsigned int div_stat_peric0;
770 unsigned int div_stat_peric1;
771 unsigned int div_stat_peric2;
772 unsigned int div_stat_peric3;
773 unsigned int div_stat_peric4;
774 unsigned int div_stat_peric5;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]775 unsigned char res83[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]776 unsigned int sclk_div_stat_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]777 unsigned char res84[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]778 unsigned int div2_stat0;
779 unsigned int div2_stat1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]780 unsigned char res85[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]781 unsigned int div4_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]782 unsigned char res86[0x184];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]783 unsigned int gate_top_sclk_disp1;
784 unsigned int gate_top_sclk_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]785 unsigned char res87[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]786 unsigned int gate_top_sclk_mau;
787 unsigned int gate_top_sclk_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]788 unsigned char res88[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]789 unsigned int gate_top_sclk_peric;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]790 unsigned char res89[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]791 unsigned int gate_top_sclk_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]792 unsigned char res90[0xac];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]793 unsigned int gate_ip_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]794 unsigned char res91[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]795 unsigned int gate_ip_disp1;
796 unsigned int gate_ip_mfc;
797 unsigned int gate_ip_g3d;
798 unsigned int gate_ip_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]799 unsigned char res92[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]800 unsigned int gate_ip_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]801 unsigned char res93[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]802 unsigned int gate_ip_peric;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]803 unsigned char res94[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]804 unsigned int gate_ip_peris;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]805 unsigned char res95[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]806 unsigned int gate_block;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]807 unsigned char res96[0x1c];
808 unsigned int mcuiop_pwr_ctrl;
809 unsigned char res97[0x5c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]810 unsigned int clkout_cmu_top;
811 unsigned int clkout_cmu_top_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]812 unsigned char res98[0x37f8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]813 unsigned int src_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]814 unsigned char res99[0x1fc];
815 unsigned int mux_stat_lex;
816 unsigned char res100[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]817 unsigned int div_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]818 unsigned char res101[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]819 unsigned int div_stat_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]820 unsigned char res102[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]821 unsigned int gate_ip_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]822 unsigned char res103[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]823 unsigned int clkout_cmu_lex;
824 unsigned int clkout_cmu_lex_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]825 unsigned char res104[0x3af8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]826 unsigned int div_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]827 unsigned char res105[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]828 unsigned int div_stat_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]829 unsigned char res106[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]830 unsigned int gate_ip_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]831 unsigned char res107[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]832 unsigned int clkout_cmu_r0x;
833 unsigned int clkout_cmu_r0x_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]834 unsigned char res108[0x3af8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]835 unsigned int div_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]836 unsigned char res109[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]837 unsigned int div_stat_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]838 unsigned char res110[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]839 unsigned int gate_ip_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]840 unsigned char res111[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]841 unsigned int clkout_cmu_r1x;
842 unsigned int clkout_cmu_r1x_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]843 unsigned char res112[0x3608];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]844 unsigned int bpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]845 unsigned char res113[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]846 unsigned int bpll_con0;
847 unsigned int bpll_con1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]848 unsigned char res114[0xe8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]849 unsigned int src_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]850 unsigned char res115[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]851 unsigned int mux_stat_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]852 unsigned char res116[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]853 unsigned int div_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]854 unsigned char res117[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]855 unsigned int div_stat_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]856 unsigned char res118[0x2fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]857 unsigned int gate_ip_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]858 unsigned char res119[0x10];
859 unsigned int dmc_freq_ctrl;
860 unsigned char res120[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]861 unsigned int drex2_pause;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]862 unsigned char res121[0xe0];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]863 unsigned int clkout_cmu_cdrex;
864 unsigned int clkout_cmu_cdrex_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]865 unsigned char res122[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]866 unsigned int lpddr3phy_ctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]867 unsigned int lpddr3phy_con0;
868 unsigned int lpddr3phy_con1;
869 unsigned int lpddr3phy_con2;
870 unsigned int lpddr3phy_con3;
871 unsigned int pll_div2_sel;
872 unsigned char res123[0xf5d8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]873};
Rajeshwari Shinde392a73a2012-10-25 19:49:29 +0000[diff] [blame]874
875/* structure for epll configuration used in audio clock configuration */
876struct set_epll_con_val {
877 unsigned int freq_out; /* frequency out */
878 unsigned int en_lock_det; /* enable lock detect */
879 unsigned int m_div; /* m divider value */
880 unsigned int p_div; /* p divider value */
881 unsigned int s_div; /* s divider value */
882 unsigned int k_dsm; /* k value of delta signal modulator */
883};
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]884#endif
Rajeshwari Shinde7b9afce2012-07-03 20:02:57 +0000[diff] [blame]885
886#define MPLL_FOUT_SEL_SHIFT 4
Rajeshwari Shinde392a73a2012-10-25 19:49:29 +0000[diff] [blame]887#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
888#define TIMEOUT_EPLL_LOCK 1000
889
890#define AUDIO_0_RATIO_MASK 0x0f
891#define AUDIO_1_RATIO_MASK 0x0f
892
893#define AUDIO1_SEL_MASK 0xf
894#define CLK_SRC_SCLK_EPLL 0x7
895
896/* CON0 bit-fields */
897#define EPLL_CON0_MDIV_MASK 0x1ff
898#define EPLL_CON0_PDIV_MASK 0x3f
899#define EPLL_CON0_SDIV_MASK 0x7
900#define EPLL_CON0_MDIV_SHIFT 16
901#define EPLL_CON0_PDIV_SHIFT 8
902#define EPLL_CON0_SDIV_SHIFT 0
903#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
904#define EPLL_CON0_LOCK_DET_EN_MASK 1
905
Rajeshwari Shinde7b9afce2012-07-03 20:02:57 +0000[diff] [blame]906#define MPLL_FOUT_SEL_MASK 0x1
Rajeshwari Shinde84112862012-07-03 20:02:58 +0000[diff] [blame]907#define BPLL_FOUT_SEL_SHIFT 0
908#define BPLL_FOUT_SEL_MASK 0x1
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]909#endif