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git01.mediatek.com / filogic / uboot / 392a73a3b5ec4bab597f4d70b559acc9523a25ee / . / arch / arm / include / asm / arch-exynos / clock.h
blob: ff6781aae45a41e616f81e5d5816f32a66e57ec2 [file] [log] [blame]
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]1/*
2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
22#ifndef __ASM_ARM_ARCH_CLOCK_H_
23#define __ASM_ARM_ARCH_CLOCK_H_
24
25#ifndef __ASSEMBLY__
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]26struct exynos4_clock {
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]27 unsigned char res1[0x4200];
28 unsigned int src_leftbus;
29 unsigned char res2[0x1fc];
30 unsigned int mux_stat_leftbus;
31 unsigned char res4[0xfc];
32 unsigned int div_leftbus;
33 unsigned char res5[0xfc];
34 unsigned int div_stat_leftbus;
35 unsigned char res6[0x1fc];
36 unsigned int gate_ip_leftbus;
37 unsigned char res7[0x1fc];
38 unsigned int clkout_leftbus;
39 unsigned int clkout_leftbus_div_stat;
40 unsigned char res8[0x37f8];
41 unsigned int src_rightbus;
42 unsigned char res9[0x1fc];
43 unsigned int mux_stat_rightbus;
44 unsigned char res10[0xfc];
45 unsigned int div_rightbus;
46 unsigned char res11[0xfc];
47 unsigned int div_stat_rightbus;
48 unsigned char res12[0x1fc];
49 unsigned int gate_ip_rightbus;
50 unsigned char res13[0x1fc];
51 unsigned int clkout_rightbus;
52 unsigned int clkout_rightbus_div_stat;
53 unsigned char res14[0x3608];
54 unsigned int epll_lock;
55 unsigned char res15[0xc];
56 unsigned int vpll_lock;
57 unsigned char res16[0xec];
58 unsigned int epll_con0;
59 unsigned int epll_con1;
60 unsigned char res17[0x8];
61 unsigned int vpll_con0;
62 unsigned int vpll_con1;
63 unsigned char res18[0xe8];
64 unsigned int src_top0;
65 unsigned int src_top1;
66 unsigned char res19[0x8];
67 unsigned int src_cam;
68 unsigned int src_tv;
69 unsigned int src_mfc;
70 unsigned int src_g3d;
71 unsigned int src_image;
72 unsigned int src_lcd0;
73 unsigned int src_lcd1;
74 unsigned int src_maudio;
75 unsigned int src_fsys;
76 unsigned char res20[0xc];
77 unsigned int src_peril0;
78 unsigned int src_peril1;
79 unsigned char res21[0xb8];
80 unsigned int src_mask_top;
81 unsigned char res22[0xc];
82 unsigned int src_mask_cam;
83 unsigned int src_mask_tv;
84 unsigned char res23[0xc];
85 unsigned int src_mask_lcd0;
86 unsigned int src_mask_lcd1;
87 unsigned int src_mask_maudio;
88 unsigned int src_mask_fsys;
89 unsigned char res24[0xc];
90 unsigned int src_mask_peril0;
91 unsigned int src_mask_peril1;
92 unsigned char res25[0xb8];
93 unsigned int mux_stat_top;
94 unsigned char res26[0x14];
95 unsigned int mux_stat_mfc;
96 unsigned int mux_stat_g3d;
97 unsigned int mux_stat_image;
98 unsigned char res27[0xdc];
99 unsigned int div_top;
100 unsigned char res28[0xc];
101 unsigned int div_cam;
102 unsigned int div_tv;
103 unsigned int div_mfc;
104 unsigned int div_g3d;
105 unsigned int div_image;
106 unsigned int div_lcd0;
107 unsigned int div_lcd1;
108 unsigned int div_maudio;
109 unsigned int div_fsys0;
110 unsigned int div_fsys1;
111 unsigned int div_fsys2;
112 unsigned int div_fsys3;
113 unsigned int div_peril0;
114 unsigned int div_peril1;
115 unsigned int div_peril2;
116 unsigned int div_peril3;
117 unsigned int div_peril4;
118 unsigned int div_peril5;
119 unsigned char res29[0x18];
120 unsigned int div2_ratio;
121 unsigned char res30[0x8c];
122 unsigned int div_stat_top;
123 unsigned char res31[0xc];
124 unsigned int div_stat_cam;
125 unsigned int div_stat_tv;
126 unsigned int div_stat_mfc;
127 unsigned int div_stat_g3d;
128 unsigned int div_stat_image;
129 unsigned int div_stat_lcd0;
130 unsigned int div_stat_lcd1;
131 unsigned int div_stat_maudio;
132 unsigned int div_stat_fsys0;
133 unsigned int div_stat_fsys1;
134 unsigned int div_stat_fsys2;
135 unsigned int div_stat_fsys3;
136 unsigned int div_stat_peril0;
137 unsigned int div_stat_peril1;
138 unsigned int div_stat_peril2;
139 unsigned int div_stat_peril3;
140 unsigned int div_stat_peril4;
141 unsigned int div_stat_peril5;
142 unsigned char res32[0x18];
143 unsigned int div2_stat;
144 unsigned char res33[0x29c];
145 unsigned int gate_ip_cam;
146 unsigned int gate_ip_tv;
147 unsigned int gate_ip_mfc;
148 unsigned int gate_ip_g3d;
149 unsigned int gate_ip_image;
150 unsigned int gate_ip_lcd0;
151 unsigned int gate_ip_lcd1;
152 unsigned char res34[0x4];
153 unsigned int gate_ip_fsys;
154 unsigned char res35[0x8];
155 unsigned int gate_ip_gps;
156 unsigned int gate_ip_peril;
157 unsigned char res36[0xc];
158 unsigned int gate_ip_perir;
159 unsigned char res37[0xc];
160 unsigned int gate_block;
161 unsigned char res38[0x8c];
162 unsigned int clkout_cmu_top;
163 unsigned int clkout_cmu_top_div_stat;
164 unsigned char res39[0x37f8];
165 unsigned int src_dmc;
166 unsigned char res40[0xfc];
167 unsigned int src_mask_dmc;
168 unsigned char res41[0xfc];
169 unsigned int mux_stat_dmc;
170 unsigned char res42[0xfc];
171 unsigned int div_dmc0;
172 unsigned int div_dmc1;
173 unsigned char res43[0xf8];
174 unsigned int div_stat_dmc0;
175 unsigned int div_stat_dmc1;
176 unsigned char res44[0x2f8];
177 unsigned int gate_ip_dmc;
178 unsigned char res45[0xfc];
179 unsigned int clkout_cmu_dmc;
180 unsigned int clkout_cmu_dmc_div_stat;
181 unsigned char res46[0x5f8];
182 unsigned int dcgidx_map0;
183 unsigned int dcgidx_map1;
184 unsigned int dcgidx_map2;
185 unsigned char res47[0x14];
186 unsigned int dcgperf_map0;
187 unsigned int dcgperf_map1;
188 unsigned char res48[0x18];
189 unsigned int dvcidx_map;
190 unsigned char res49[0x1c];
191 unsigned int freq_cpu;
192 unsigned int freq_dpm;
193 unsigned char res50[0x18];
194 unsigned int dvsemclk_en;
195 unsigned int maxperf;
196 unsigned char res51[0x2f78];
197 unsigned int apll_lock;
198 unsigned char res52[0x4];
199 unsigned int mpll_lock;
200 unsigned char res53[0xf4];
201 unsigned int apll_con0;
202 unsigned int apll_con1;
203 unsigned int mpll_con0;
204 unsigned int mpll_con1;
205 unsigned char res54[0xf0];
206 unsigned int src_cpu;
207 unsigned char res55[0x1fc];
208 unsigned int mux_stat_cpu;
209 unsigned char res56[0xfc];
210 unsigned int div_cpu0;
211 unsigned int div_cpu1;
212 unsigned char res57[0xf8];
213 unsigned int div_stat_cpu0;
214 unsigned int div_stat_cpu1;
215 unsigned char res58[0x3f8];
216 unsigned int clkout_cmu_cpu;
217 unsigned int clkout_cmu_cpu_div_stat;
218 unsigned char res59[0x5f8];
219 unsigned int armclk_stopctrl;
220 unsigned int atclk_stopctrl;
221 unsigned char res60[0x8];
222 unsigned int parityfail_status;
223 unsigned int parityfail_clear;
224 unsigned char res61[0xe8];
225 unsigned int apll_con0_l8;
226 unsigned int apll_con0_l7;
227 unsigned int apll_con0_l6;
228 unsigned int apll_con0_l5;
229 unsigned int apll_con0_l4;
230 unsigned int apll_con0_l3;
231 unsigned int apll_con0_l2;
232 unsigned int apll_con0_l1;
233 unsigned int iem_control;
234 unsigned char res62[0xdc];
235 unsigned int apll_con1_l8;
236 unsigned int apll_con1_l7;
237 unsigned int apll_con1_l6;
238 unsigned int apll_con1_l5;
239 unsigned int apll_con1_l4;
240 unsigned int apll_con1_l3;
241 unsigned int apll_con1_l2;
242 unsigned int apll_con1_l1;
243 unsigned char res63[0xe0];
244 unsigned int div_iem_l8;
245 unsigned int div_iem_l7;
246 unsigned int div_iem_l6;
247 unsigned int div_iem_l5;
248 unsigned int div_iem_l4;
249 unsigned int div_iem_l3;
250 unsigned int div_iem_l2;
251 unsigned int div_iem_l1;
252};
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]253
254struct exynos5_clock {
255 unsigned int apll_lock;
256 unsigned char res1[0xfc];
257 unsigned int apll_con0;
258 unsigned int apll_con1;
259 unsigned char res2[0xf8];
260 unsigned int src_cpu;
261 unsigned char res3[0x1fc];
262 unsigned int mux_stat_cpu;
263 unsigned char res4[0xfc];
264 unsigned int div_cpu0;
265 unsigned int div_cpu1;
266 unsigned char res5[0xf8];
267 unsigned int div_stat_cpu0;
268 unsigned int div_stat_cpu1;
269 unsigned char res6[0x1f8];
270 unsigned int gate_sclk_cpu;
271 unsigned char res7[0x1fc];
272 unsigned int clkout_cmu_cpu;
273 unsigned int clkout_cmu_cpu_div_stat;
274 unsigned char res8[0x5f8];
275 unsigned int armclk_stopctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]276 unsigned char res9[0x0c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]277 unsigned int parityfail_status;
278 unsigned int parityfail_clear;
279 unsigned char res10[0x8];
280 unsigned int pwr_ctrl;
281 unsigned int pwr_ctr2;
282 unsigned char res11[0xd8];
283 unsigned int apll_con0_l8;
284 unsigned int apll_con0_l7;
285 unsigned int apll_con0_l6;
286 unsigned int apll_con0_l5;
287 unsigned int apll_con0_l4;
288 unsigned int apll_con0_l3;
289 unsigned int apll_con0_l2;
290 unsigned int apll_con0_l1;
291 unsigned int iem_control;
292 unsigned char res12[0xdc];
293 unsigned int apll_con1_l8;
294 unsigned int apll_con1_l7;
295 unsigned int apll_con1_l6;
296 unsigned int apll_con1_l5;
297 unsigned int apll_con1_l4;
298 unsigned int apll_con1_l3;
299 unsigned int apll_con1_l2;
300 unsigned int apll_con1_l1;
301 unsigned char res13[0xe0];
302 unsigned int div_iem_l8;
303 unsigned int div_iem_l7;
304 unsigned int div_iem_l6;
305 unsigned int div_iem_l5;
306 unsigned int div_iem_l4;
307 unsigned int div_iem_l3;
308 unsigned int div_iem_l2;
309 unsigned int div_iem_l1;
310 unsigned char res14[0x2ce0];
311 unsigned int mpll_lock;
312 unsigned char res15[0xfc];
313 unsigned int mpll_con0;
314 unsigned int mpll_con1;
315 unsigned char res16[0xf8];
316 unsigned int src_core0;
317 unsigned int src_core1;
318 unsigned char res17[0xf8];
319 unsigned int src_mask_core;
320 unsigned char res18[0x100];
321 unsigned int mux_stat_core1;
322 unsigned char res19[0xf8];
323 unsigned int div_core0;
324 unsigned int div_core1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]325 unsigned int div_sysrgt;
326 unsigned char res20[0xf4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]327 unsigned int div_stat_core0;
328 unsigned int div_stat_core1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]329 unsigned int div_stat_sysrgt;
330 unsigned char res21[0x2f4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]331 unsigned int gate_ip_core;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]332 unsigned int gate_ip_sysrgt;
333 unsigned char res22[0x8];
334 unsigned int c2c_monitor;
335 unsigned char res23[0xec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]336 unsigned int clkout_cmu_core;
337 unsigned int clkout_cmu_core_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]338 unsigned char res24[0x5f8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]339 unsigned int dcgidx_map0;
340 unsigned int dcgidx_map1;
341 unsigned int dcgidx_map2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]342 unsigned char res25[0x14];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]343 unsigned int dcgperf_map0;
344 unsigned int dcgperf_map1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]345 unsigned char res26[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]346 unsigned int dvcidx_map;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]347 unsigned char res27[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]348 unsigned int freq_cpu;
349 unsigned int freq_dpm;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]350 unsigned char res28[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]351 unsigned int dvsemclk_en;
352 unsigned int maxperf;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]353 unsigned char res29[0xf78];
354 unsigned int c2c_config;
355 unsigned char res30[0x24fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]356 unsigned int div_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]357 unsigned char res31[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]358 unsigned int div_stat_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]359 unsigned char res32[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]360 unsigned int gate_ip_acp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]361 unsigned char res33[0xfc];
362 unsigned int div_syslft;
363 unsigned char res34[0xc];
364 unsigned int div_stat_syslft;
365 unsigned char res35[0x1c];
366 unsigned int gate_ip_syslft;
367 unsigned char res36[0xcc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]368 unsigned int clkout_cmu_acp;
369 unsigned int clkout_cmu_acp_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]370 unsigned char res37[0x8];
371 unsigned int ufmc_config;
372 unsigned char res38[0x38ec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]373 unsigned int div_isp0;
374 unsigned int div_isp1;
375 unsigned int div_isp2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]376 unsigned char res39[0xf4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]377 unsigned int div_stat_isp0;
378 unsigned int div_stat_isp1;
379 unsigned int div_stat_isp2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]380 unsigned char res40[0x3f4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]381 unsigned int gate_ip_isp0;
382 unsigned int gate_ip_isp1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]383 unsigned char res41[0xf8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]384 unsigned int gate_sclk_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]385 unsigned char res42[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]386 unsigned int mcuisp_pwr_ctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]387 unsigned char res43[0xec];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]388 unsigned int clkout_cmu_isp;
389 unsigned int clkout_cmu_isp_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]390 unsigned char res44[0x3618];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]391 unsigned int cpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]392 unsigned char res45[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]393 unsigned int epll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]394 unsigned char res46[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]395 unsigned int vpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]396 unsigned char res47[0xc];
397 unsigned int gpll_lock;
398 unsigned char res48[0xcc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]399 unsigned int cpll_con0;
400 unsigned int cpll_con1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]401 unsigned char res49[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]402 unsigned int epll_con0;
403 unsigned int epll_con1;
404 unsigned int epll_con2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]405 unsigned char res50[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]406 unsigned int vpll_con0;
407 unsigned int vpll_con1;
408 unsigned int vpll_con2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]409 unsigned char res51[0x4];
410 unsigned int gpll_con0;
411 unsigned int gpll_con1;
412 unsigned char res52[0xb8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]413 unsigned int src_top0;
414 unsigned int src_top1;
415 unsigned int src_top2;
416 unsigned int src_top3;
417 unsigned int src_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]418 unsigned char res53[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]419 unsigned int src_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]420 unsigned char res54[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]421 unsigned int src_mau;
422 unsigned int src_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]423 unsigned int src_gen;
424 unsigned char res55[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]425 unsigned int src_peric0;
426 unsigned int src_peric1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]427 unsigned char res56[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]428 unsigned int sclk_src_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]429 unsigned char res57[0x9c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]430 unsigned int src_mask_top;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]431 unsigned char res58[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]432 unsigned int src_mask_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]433 unsigned char res59[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]434 unsigned int src_mask_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]435 unsigned char res60[0x4];
436 unsigned int src_mask_mau;
437 unsigned char res61[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]438 unsigned int src_mask_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]439 unsigned int src_mask_gen;
440 unsigned char res62[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]441 unsigned int src_mask_peric0;
442 unsigned int src_mask_peric1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]443 unsigned char res63[0x18];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]444 unsigned int src_mask_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]445 unsigned char res67[0x9c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]446 unsigned int mux_stat_top0;
447 unsigned int mux_stat_top1;
448 unsigned int mux_stat_top2;
449 unsigned int mux_stat_top3;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]450 unsigned char res68[0xf0];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]451 unsigned int div_top0;
452 unsigned int div_top1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]453 unsigned char res69[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]454 unsigned int div_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]455 unsigned char res70[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]456 unsigned int div_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]457 unsigned char res71[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]458 unsigned int div_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]459 unsigned char res72[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]460 unsigned int div_mau;
461 unsigned int div_fsys0;
462 unsigned int div_fsys1;
463 unsigned int div_fsys2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]464 unsigned char res73[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]465 unsigned int div_peric0;
466 unsigned int div_peric1;
467 unsigned int div_peric2;
468 unsigned int div_peric3;
469 unsigned int div_peric4;
470 unsigned int div_peric5;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]471 unsigned char res74[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]472 unsigned int sclk_div_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]473 unsigned char res75[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]474 unsigned int div2_ratio0;
475 unsigned int div2_ratio1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]476 unsigned char res76[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]477 unsigned int div4_ratio;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]478 unsigned char res77[0x6c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]479 unsigned int div_stat_top0;
480 unsigned int div_stat_top1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]481 unsigned char res78[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]482 unsigned int div_stat_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]483 unsigned char res79[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]484 unsigned int div_stat_disp1_0;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]485 unsigned char res80[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]486 unsigned int div_stat_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]487 unsigned char res81[0x4];
488 unsigned int div_stat_mau;
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]489 unsigned int div_stat_fsys0;
490 unsigned int div_stat_fsys1;
491 unsigned int div_stat_fsys2;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]492 unsigned char res82[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]493 unsigned int div_stat_peric0;
494 unsigned int div_stat_peric1;
495 unsigned int div_stat_peric2;
496 unsigned int div_stat_peric3;
497 unsigned int div_stat_peric4;
498 unsigned int div_stat_peric5;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]499 unsigned char res83[0x10];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]500 unsigned int sclk_div_stat_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]501 unsigned char res84[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]502 unsigned int div2_stat0;
503 unsigned int div2_stat1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]504 unsigned char res85[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]505 unsigned int div4_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]506 unsigned char res86[0x184];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]507 unsigned int gate_top_sclk_disp1;
508 unsigned int gate_top_sclk_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]509 unsigned char res87[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]510 unsigned int gate_top_sclk_mau;
511 unsigned int gate_top_sclk_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]512 unsigned char res88[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]513 unsigned int gate_top_sclk_peric;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]514 unsigned char res89[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]515 unsigned int gate_top_sclk_isp;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]516 unsigned char res90[0xac];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]517 unsigned int gate_ip_gscl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]518 unsigned char res91[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]519 unsigned int gate_ip_disp1;
520 unsigned int gate_ip_mfc;
521 unsigned int gate_ip_g3d;
522 unsigned int gate_ip_gen;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]523 unsigned char res92[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]524 unsigned int gate_ip_fsys;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]525 unsigned char res93[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]526 unsigned int gate_ip_peric;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]527 unsigned char res94[0xc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]528 unsigned int gate_ip_peris;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]529 unsigned char res95[0x1c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]530 unsigned int gate_block;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]531 unsigned char res96[0x1c];
532 unsigned int mcuiop_pwr_ctrl;
533 unsigned char res97[0x5c];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]534 unsigned int clkout_cmu_top;
535 unsigned int clkout_cmu_top_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]536 unsigned char res98[0x37f8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]537 unsigned int src_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]538 unsigned char res99[0x1fc];
539 unsigned int mux_stat_lex;
540 unsigned char res100[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]541 unsigned int div_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]542 unsigned char res101[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]543 unsigned int div_stat_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]544 unsigned char res102[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]545 unsigned int gate_ip_lex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]546 unsigned char res103[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]547 unsigned int clkout_cmu_lex;
548 unsigned int clkout_cmu_lex_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]549 unsigned char res104[0x3af8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]550 unsigned int div_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]551 unsigned char res105[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]552 unsigned int div_stat_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]553 unsigned char res106[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]554 unsigned int gate_ip_r0x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]555 unsigned char res107[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]556 unsigned int clkout_cmu_r0x;
557 unsigned int clkout_cmu_r0x_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]558 unsigned char res108[0x3af8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]559 unsigned int div_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]560 unsigned char res109[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]561 unsigned int div_stat_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]562 unsigned char res110[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]563 unsigned int gate_ip_r1x;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]564 unsigned char res111[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]565 unsigned int clkout_cmu_r1x;
566 unsigned int clkout_cmu_r1x_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]567 unsigned char res112[0x3608];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]568 unsigned int bpll_lock;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]569 unsigned char res113[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]570 unsigned int bpll_con0;
571 unsigned int bpll_con1;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]572 unsigned char res114[0xe8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]573 unsigned int src_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]574 unsigned char res115[0x1fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]575 unsigned int mux_stat_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]576 unsigned char res116[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]577 unsigned int div_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]578 unsigned char res117[0xfc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]579 unsigned int div_stat_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]580 unsigned char res118[0x2fc];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]581 unsigned int gate_ip_cdrex;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]582 unsigned char res119[0x10];
583 unsigned int dmc_freq_ctrl;
584 unsigned char res120[0x4];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]585 unsigned int drex2_pause;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]586 unsigned char res121[0xe0];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]587 unsigned int clkout_cmu_cdrex;
588 unsigned int clkout_cmu_cdrex_div_stat;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]589 unsigned char res122[0x8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]590 unsigned int lpddr3phy_ctrl;
Rajeshwari Shindec8232672012-07-03 20:02:54 +0000[diff] [blame]591 unsigned int lpddr3phy_con0;
592 unsigned int lpddr3phy_con1;
593 unsigned int lpddr3phy_con2;
594 unsigned int lpddr3phy_con3;
595 unsigned int pll_div2_sel;
596 unsigned char res123[0xf5d8];
Chander Kashyap34076a02012-02-05 23:01:46 +0000[diff] [blame]597};
Rajeshwari Shinde392a73a2012-10-25 19:49:29 +0000[diff] [blame^]598
599/* structure for epll configuration used in audio clock configuration */
600struct set_epll_con_val {
601 unsigned int freq_out; /* frequency out */
602 unsigned int en_lock_det; /* enable lock detect */
603 unsigned int m_div; /* m divider value */
604 unsigned int p_div; /* p divider value */
605 unsigned int s_div; /* s divider value */
606 unsigned int k_dsm; /* k value of delta signal modulator */
607};
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]608#endif
Rajeshwari Shinde7b9afce2012-07-03 20:02:57 +0000[diff] [blame]609
610#define MPLL_FOUT_SEL_SHIFT 4
Rajeshwari Shinde392a73a2012-10-25 19:49:29 +0000[diff] [blame^]611#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
612#define TIMEOUT_EPLL_LOCK 1000
613
614#define AUDIO_0_RATIO_MASK 0x0f
615#define AUDIO_1_RATIO_MASK 0x0f
616
617#define AUDIO1_SEL_MASK 0xf
618#define CLK_SRC_SCLK_EPLL 0x7
619
620/* CON0 bit-fields */
621#define EPLL_CON0_MDIV_MASK 0x1ff
622#define EPLL_CON0_PDIV_MASK 0x3f
623#define EPLL_CON0_SDIV_MASK 0x7
624#define EPLL_CON0_MDIV_SHIFT 16
625#define EPLL_CON0_PDIV_SHIFT 8
626#define EPLL_CON0_SDIV_SHIFT 0
627#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
628#define EPLL_CON0_LOCK_DET_EN_MASK 1
629
Rajeshwari Shinde7b9afce2012-07-03 20:02:57 +0000[diff] [blame]630#define MPLL_FOUT_SEL_MASK 0x1
Rajeshwari Shinde84112862012-07-03 20:02:58 +0000[diff] [blame]631#define BPLL_FOUT_SEL_SHIFT 0
632#define BPLL_FOUT_SEL_MASK 0x1
Minkyu Kangb1b24682011-01-24 15:22:23 +0900[diff] [blame]633#endif