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git01.mediatek.com / filogic / uboot / ac73f47476abd12c12830c464a096d0313e82d11 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: 377143d391834a67ab1989a93221f109e13fc452 [file] [log] [blame]
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]7 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]23#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]24
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]25#define CPU_ALL_GP(fn, sfx) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]26 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]29 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]30 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]34 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]35 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]38
39#define CPU_ALL_NOGP(fn) \
40 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
59 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
77 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
79 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
80 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
81 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
82
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]83/*
84 * F_() : just information
85 * FM() : macro for FN_xxx / xxx_MARK
86 */
87
88/* GPSR0 */
89#define GPSR0_15 F_(D15, IP7_11_8)
90#define GPSR0_14 F_(D14, IP7_7_4)
91#define GPSR0_13 F_(D13, IP7_3_0)
92#define GPSR0_12 F_(D12, IP6_31_28)
93#define GPSR0_11 F_(D11, IP6_27_24)
94#define GPSR0_10 F_(D10, IP6_23_20)
95#define GPSR0_9 F_(D9, IP6_19_16)
96#define GPSR0_8 F_(D8, IP6_15_12)
97#define GPSR0_7 F_(D7, IP6_11_8)
98#define GPSR0_6 F_(D6, IP6_7_4)
99#define GPSR0_5 F_(D5, IP6_3_0)
100#define GPSR0_4 F_(D4, IP5_31_28)
101#define GPSR0_3 F_(D3, IP5_27_24)
102#define GPSR0_2 F_(D2, IP5_23_20)
103#define GPSR0_1 F_(D1, IP5_19_16)
104#define GPSR0_0 F_(D0, IP5_15_12)
105
106/* GPSR1 */
107#define GPSR1_28 FM(CLKOUT)
108#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
109#define GPSR1_26 F_(WE1_N, IP5_7_4)
110#define GPSR1_25 F_(WE0_N, IP5_3_0)
111#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
112#define GPSR1_23 F_(RD_N, IP4_27_24)
113#define GPSR1_22 F_(BS_N, IP4_23_20)
114#define GPSR1_21 F_(CS1_N, IP4_19_16)
115#define GPSR1_20 F_(CS0_N, IP4_15_12)
116#define GPSR1_19 F_(A19, IP4_11_8)
117#define GPSR1_18 F_(A18, IP4_7_4)
118#define GPSR1_17 F_(A17, IP4_3_0)
119#define GPSR1_16 F_(A16, IP3_31_28)
120#define GPSR1_15 F_(A15, IP3_27_24)
121#define GPSR1_14 F_(A14, IP3_23_20)
122#define GPSR1_13 F_(A13, IP3_19_16)
123#define GPSR1_12 F_(A12, IP3_15_12)
124#define GPSR1_11 F_(A11, IP3_11_8)
125#define GPSR1_10 F_(A10, IP3_7_4)
126#define GPSR1_9 F_(A9, IP3_3_0)
127#define GPSR1_8 F_(A8, IP2_31_28)
128#define GPSR1_7 F_(A7, IP2_27_24)
129#define GPSR1_6 F_(A6, IP2_23_20)
130#define GPSR1_5 F_(A5, IP2_19_16)
131#define GPSR1_4 F_(A4, IP2_15_12)
132#define GPSR1_3 F_(A3, IP2_11_8)
133#define GPSR1_2 F_(A2, IP2_7_4)
134#define GPSR1_1 F_(A1, IP2_3_0)
135#define GPSR1_0 F_(A0, IP1_31_28)
136
137/* GPSR2 */
138#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
139#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
140#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
141#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
142#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
143#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
144#define GPSR2_8 F_(PWM2_A, IP1_27_24)
145#define GPSR2_7 F_(PWM1_A, IP1_23_20)
146#define GPSR2_6 F_(PWM0, IP1_19_16)
147#define GPSR2_5 F_(IRQ5, IP1_15_12)
148#define GPSR2_4 F_(IRQ4, IP1_11_8)
149#define GPSR2_3 F_(IRQ3, IP1_7_4)
150#define GPSR2_2 F_(IRQ2, IP1_3_0)
151#define GPSR2_1 F_(IRQ1, IP0_31_28)
152#define GPSR2_0 F_(IRQ0, IP0_27_24)
153
154/* GPSR3 */
155#define GPSR3_15 F_(SD1_WP, IP11_23_20)
156#define GPSR3_14 F_(SD1_CD, IP11_19_16)
157#define GPSR3_13 F_(SD0_WP, IP11_15_12)
158#define GPSR3_12 F_(SD0_CD, IP11_11_8)
159#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
160#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
161#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
162#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
163#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
164#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
165#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
166#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
167#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
168#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
169#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
170#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
171
172/* GPSR4 */
173#define GPSR4_17 F_(SD3_DS, IP11_7_4)
174#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
175#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
176#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
177#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
178#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
179#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
180#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
181#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
182#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
183#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
184#define GPSR4_6 F_(SD2_DS, IP9_27_24)
185#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
186#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
187#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
188#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
189#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
190#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
191
192/* GPSR5 */
193#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
194#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
195#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
196#define GPSR5_22 FM(MSIOF0_RXD)
197#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
198#define GPSR5_20 FM(MSIOF0_TXD)
199#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
200#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
201#define GPSR5_17 FM(MSIOF0_SCK)
202#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
203#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
204#define GPSR5_14 F_(HTX0, IP13_19_16)
205#define GPSR5_13 F_(HRX0, IP13_15_12)
206#define GPSR5_12 F_(HSCK0, IP13_11_8)
207#define GPSR5_11 F_(RX2_A, IP13_7_4)
208#define GPSR5_10 F_(TX2_A, IP13_3_0)
209#define GPSR5_9 F_(SCK2, IP12_31_28)
210#define GPSR5_8 F_(RTS1_N, IP12_27_24)
211#define GPSR5_7 F_(CTS1_N, IP12_23_20)
212#define GPSR5_6 F_(TX1_A, IP12_19_16)
213#define GPSR5_5 F_(RX1_A, IP12_15_12)
214#define GPSR5_4 F_(RTS0_N, IP12_11_8)
215#define GPSR5_3 F_(CTS0_N, IP12_7_4)
216#define GPSR5_2 F_(TX0, IP12_3_0)
217#define GPSR5_1 F_(RX0, IP11_31_28)
218#define GPSR5_0 F_(SCK0, IP11_27_24)
219
220/* GPSR6 */
221#define GPSR6_31 F_(GP6_31, IP18_7_4)
222#define GPSR6_30 F_(GP6_30, IP18_3_0)
223#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
224#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
225#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
226#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
227#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
228#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
229#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
230#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
231#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
232#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
233#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
234#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
235#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
236#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
237#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
238#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
239#define GPSR6_13 FM(SSI_SDATA5)
240#define GPSR6_12 FM(SSI_WS5)
241#define GPSR6_11 FM(SSI_SCK5)
242#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
243#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
244#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
245#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
246#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
247#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
248#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
249#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
250#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
251#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
252#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
253
254/* GPSR7 */
255#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]256#define GPSR7_2 FM(GP7_02)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]257#define GPSR7_1 FM(AVS2)
258#define GPSR7_0 FM(AVS1)
259
260
261/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
262#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289
290/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
291#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320
321/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
322#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356
357/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
358#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
379#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386
387/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
388#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]405#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]406#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
408#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
409#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
410#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
411#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
412#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
414#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
415
416#define PINMUX_GPSR \
417\
418 GPSR6_31 \
419 GPSR6_30 \
420 GPSR6_29 \
421 GPSR1_28 GPSR6_28 \
422 GPSR1_27 GPSR6_27 \
423 GPSR1_26 GPSR6_26 \
424 GPSR1_25 GPSR5_25 GPSR6_25 \
425 GPSR1_24 GPSR5_24 GPSR6_24 \
426 GPSR1_23 GPSR5_23 GPSR6_23 \
427 GPSR1_22 GPSR5_22 GPSR6_22 \
428 GPSR1_21 GPSR5_21 GPSR6_21 \
429 GPSR1_20 GPSR5_20 GPSR6_20 \
430 GPSR1_19 GPSR5_19 GPSR6_19 \
431 GPSR1_18 GPSR5_18 GPSR6_18 \
432 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
433 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
434GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
435GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
436GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
437GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
438GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
439GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
440GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
441GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
442GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
443GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
444GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
445GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
446GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
447GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
448GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
449GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
450
451#define PINMUX_IPSR \
452\
453FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
454FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
455FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
456FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
457FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
458FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
459FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
460FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
461\
462FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
463FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
464FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
465FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
466FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
467FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
468FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
469FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
470\
471FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
472FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
473FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
474FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
475FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
476FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
477FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
478FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
479\
480FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
481FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
482FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
483FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
484FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
485FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
486FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
487FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
488\
489FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
490FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
491FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
492FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
493FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
494FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
495FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
496FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
497
498/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
499#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
501#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
502#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
503#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
504#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
505#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
506#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
507#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
508#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
509#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
510#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
511#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
512#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
513#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
514#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
515#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]516#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]517
518/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
519#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
520#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
522#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
523#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
524#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
525#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
526#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
527#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
528#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
529#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
530#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
531#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
532#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
533#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
534#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
535#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
536#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
537#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
538#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
539#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
540#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
541
542/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
543#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
544#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
545#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
546#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
547#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
548#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]549#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]550#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
551#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
552#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]553#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
554#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]555#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
556
557#define PINMUX_MOD_SELS \
558\
559MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
560 MOD_SEL2_30 \
561 MOD_SEL1_29_28_27 MOD_SEL2_29 \
562MOD_SEL0_28_27 MOD_SEL2_28_27 \
563MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
564 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
565MOD_SEL0_23 MOD_SEL1_23_22_21 \
566MOD_SEL0_22 MOD_SEL2_22 \
567MOD_SEL0_21 MOD_SEL2_21 \
568MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
569MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
570MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
571 MOD_SEL2_17 \
572MOD_SEL0_16 MOD_SEL1_16 \
573 MOD_SEL1_15_14 \
574MOD_SEL0_14_13 \
575 MOD_SEL1_13 \
576MOD_SEL0_12 MOD_SEL1_12 \
577MOD_SEL0_11 MOD_SEL1_11 \
578MOD_SEL0_10 MOD_SEL1_10 \
579MOD_SEL0_9_8 MOD_SEL1_9 \
580MOD_SEL0_7_6 \
581 MOD_SEL1_6 \
582MOD_SEL0_5 MOD_SEL1_5 \
583MOD_SEL0_4_3 MOD_SEL1_4 \
584 MOD_SEL1_3 \
585 MOD_SEL1_2 \
586 MOD_SEL1_1 \
587 MOD_SEL1_0 MOD_SEL2_0
588
589/*
590 * These pins are not able to be muxed but have other properties
591 * that can be set, such as drive-strength or pull-up/pull-down enable.
592 */
593#define PINMUX_STATIC \
594 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
595 FM(QSPI0_IO2) FM(QSPI0_IO3) \
596 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
597 FM(QSPI1_IO2) FM(QSPI1_IO3) \
598 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
599 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
600 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
601 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
602 FM(PRESETOUT) \
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]603 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]604 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
605
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]606#define PINMUX_PHYS \
607 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
608
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]609enum {
610 PINMUX_RESERVED = 0,
611
612 PINMUX_DATA_BEGIN,
613 GP_ALL(DATA),
614 PINMUX_DATA_END,
615
616#define F_(x, y)
617#define FM(x) FN_##x,
618 PINMUX_FUNCTION_BEGIN,
619 GP_ALL(FN),
620 PINMUX_GPSR
621 PINMUX_IPSR
622 PINMUX_MOD_SELS
623 PINMUX_FUNCTION_END,
624#undef F_
625#undef FM
626
627#define F_(x, y)
628#define FM(x) x##_MARK,
629 PINMUX_MARK_BEGIN,
630 PINMUX_GPSR
631 PINMUX_IPSR
632 PINMUX_MOD_SELS
633 PINMUX_STATIC
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]634 PINMUX_PHYS
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]635 PINMUX_MARK_END,
636#undef F_
637#undef FM
638};
639
640static const u16 pinmux_data[] = {
641 PINMUX_DATA_GP_ALL(),
642
643 PINMUX_SINGLE(AVS1),
644 PINMUX_SINGLE(AVS2),
645 PINMUX_SINGLE(CLKOUT),
646 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]647 PINMUX_SINGLE(GP7_02),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]648 PINMUX_SINGLE(MSIOF0_RXD),
649 PINMUX_SINGLE(MSIOF0_SCK),
650 PINMUX_SINGLE(MSIOF0_TXD),
651 PINMUX_SINGLE(SSI_SCK5),
652 PINMUX_SINGLE(SSI_SDATA5),
653 PINMUX_SINGLE(SSI_WS5),
654
655 /* IPSR0 */
656 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
657 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
658
659 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
660 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
661 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
662
663 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
664 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
665 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
666
667 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
668 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
669 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
670 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
671
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
673 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
674 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]675 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]676
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
678 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
679 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]680 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]681
682 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
683 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
684 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
685 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
687 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
688 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
689
690 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
691 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
692 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
693 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
695 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
696 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
697
698 /* IPSR1 */
699 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
700 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
701 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
702 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
703 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
704 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
705
706 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
707 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
708 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
709 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
710 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
711 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
712
713 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
714 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
715 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
716 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
717 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
718 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
719
720 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
721 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
722 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
723 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
724 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
725 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
726 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
727
728 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
729 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
730 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
731 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
732
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
735 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
736 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
737 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]738
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
740 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
741 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
742 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]743
744 PINMUX_IPSR_GPSR(IP1_31_28, A0),
745 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
746 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
747 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
748 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
749 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
750
751 /* IPSR2 */
752 PINMUX_IPSR_GPSR(IP2_3_0, A1),
753 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
754 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
755 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
756 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
757 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
758
759 PINMUX_IPSR_GPSR(IP2_7_4, A2),
760 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
761 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
762 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
763 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
764 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
765
766 PINMUX_IPSR_GPSR(IP2_11_8, A3),
767 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
768 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
769 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
770 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
771 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
772
773 PINMUX_IPSR_GPSR(IP2_15_12, A4),
774 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
775 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
776 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
777 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
778 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
779
780 PINMUX_IPSR_GPSR(IP2_19_16, A5),
781 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
782 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
783 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
785 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
786 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
787
788 PINMUX_IPSR_GPSR(IP2_23_20, A6),
789 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
790 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
792 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
793 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
794 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
795
796 PINMUX_IPSR_GPSR(IP2_27_24, A7),
797 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
798 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
800 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
801 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
802 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
803
804 PINMUX_IPSR_GPSR(IP2_31_28, A8),
805 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
807 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
808 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
809 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
810 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
811
812 /* IPSR3 */
813 PINMUX_IPSR_GPSR(IP3_3_0, A9),
814 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
817
818 PINMUX_IPSR_GPSR(IP3_7_4, A10),
819 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
820 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
821 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
822
823 PINMUX_IPSR_GPSR(IP3_11_8, A11),
824 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
825 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
826 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
827 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
828 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
829 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
830 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
831 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
832
833 PINMUX_IPSR_GPSR(IP3_15_12, A12),
834 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
835 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
836 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
837 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
838 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
839
840 PINMUX_IPSR_GPSR(IP3_19_16, A13),
841 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
842 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
843 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
844 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
845 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
846
847 PINMUX_IPSR_GPSR(IP3_23_20, A14),
848 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
849 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
850 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
851 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
852 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
853
854 PINMUX_IPSR_GPSR(IP3_27_24, A15),
855 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
856 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
857 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
858 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
859 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
860
861 PINMUX_IPSR_GPSR(IP3_31_28, A16),
862 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
863 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
864 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
865
866 /* IPSR4 */
867 PINMUX_IPSR_GPSR(IP4_3_0, A17),
868 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
869 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
870 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
871
872 PINMUX_IPSR_GPSR(IP4_7_4, A18),
873 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
874 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
875 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
876
877 PINMUX_IPSR_GPSR(IP4_11_8, A19),
878 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
879 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
880 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
881
882 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
883 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
884
885 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
886 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
887 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
888
889 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
890 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
891 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
893 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
894 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
895 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
896 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
897
898 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
899 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
900 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
902 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
903 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
904
905 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
906 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
908 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
909 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
910 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
911
912 /* IPSR5 */
913 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
914 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
915 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
916 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
917 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
918 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
919 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
920
921 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
922 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
923 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
924 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
925 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
926 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
927 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
928 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
929
930 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
931 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
932 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
933 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
934
935 PINMUX_IPSR_GPSR(IP5_15_12, D0),
936 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
937 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
938 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
939 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
940
941 PINMUX_IPSR_GPSR(IP5_19_16, D1),
942 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
943 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
944 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
945 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
946
947 PINMUX_IPSR_GPSR(IP5_23_20, D2),
948 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
950 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
951
952 PINMUX_IPSR_GPSR(IP5_27_24, D3),
953 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
954 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
955 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
956
957 PINMUX_IPSR_GPSR(IP5_31_28, D4),
958 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
959 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
960 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
961
962 /* IPSR6 */
963 PINMUX_IPSR_GPSR(IP6_3_0, D5),
964 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
965 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
966 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
967
968 PINMUX_IPSR_GPSR(IP6_7_4, D6),
969 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
970 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
971 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
972
973 PINMUX_IPSR_GPSR(IP6_11_8, D7),
974 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
975 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
976 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
977
978 PINMUX_IPSR_GPSR(IP6_15_12, D8),
979 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
980 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
981 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
982 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
983 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
984
985 PINMUX_IPSR_GPSR(IP6_19_16, D9),
986 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
987 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
988 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
989 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
990
991 PINMUX_IPSR_GPSR(IP6_23_20, D10),
992 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
993 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
995 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
996 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
997 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
998
999 PINMUX_IPSR_GPSR(IP6_27_24, D11),
1000 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
1001 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1003 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1004 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1005 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1006
1007 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1008 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1009 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1010 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1011 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1012 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1013
1014 /* IPSR7 */
1015 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1016 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1017 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1018 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1019 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1020 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1021
1022 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1023 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1024 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1025 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1026 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1027 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1028 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1029
1030 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1031 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1032 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1033 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1034 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1035 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1036 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1037
1038 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1039 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1041
1042 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1043 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1044 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1045
1046 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1047 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1048 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1049 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1050
1051 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1052 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1053 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1054 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1055
1056 /* IPSR8 */
1057 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1058 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1059 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1060 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1061
1062 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1063 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1064 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1065 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1066
1067 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1068 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1069 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1070
1071 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1072 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1073 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1074 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1075 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1076
1077 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1078 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1079 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1080 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1081 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1082 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1083
1084 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1085 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1086 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1087 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1088 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1089 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1090
1091 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1092 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1093 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1094 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1095 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1096 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1097
1098 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1099 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1100 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1101 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1102 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1103 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1104
1105 /* IPSR9 */
1106 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1107 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1108
1109 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1110 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1111
1112 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1113 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1114
1115 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1116 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1117
1118 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1119 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1120
1121 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1122 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1123
1124 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1125 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1126 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1127
1128 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1129 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1130
1131 /* IPSR10 */
1132 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1133 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1134
1135 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1136 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1137
1138 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1139 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1140
1141 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1142 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1143
1144 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1145 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1146
1147 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1148 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1149 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1150
1151 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1152 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1153 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1154
1155 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1156 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1157 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1158
1159 /* IPSR11 */
1160 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1161 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1162 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1163
1164 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1165 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1166
1167 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1170 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1171
1172 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1173 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1174 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1175
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1176 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1177 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1178 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1179 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1180
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1181 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1182 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1183 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1184 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1185
1186 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1187 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1188 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1189 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1190 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1191 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1192 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1194 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1195 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1196
1197 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1198 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1199 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1200 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1201 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1202
1203 /* IPSR12 */
1204 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1205 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1206 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1207 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1208 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1209
1210 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1211 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1212 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1213 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1214 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1215 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1216 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1217 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1218
1219 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1220 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1221 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1222 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1223 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1224 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1225 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1226 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1227
1228 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1229 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1231 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1232 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1233
1234 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1235 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1236 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1237 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1238 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1239
1240 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1241 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1242 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1243 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1244 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1245 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1246 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1247
1248 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1249 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1250 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1251 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1252 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1253 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1254 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1255
1256 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1257 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1258 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1259 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1260 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1261 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1262 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1263
1264 /* IPSR13 */
1265 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1267 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1268 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1269 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1270 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1271
1272 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1274 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1275 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1276 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1277 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1278
1279 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1280 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1281 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1282 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1283 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1284 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1286 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1287
1288 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1289 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1291 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1292 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1293 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1294
1295 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1296 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1298 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1299 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1300 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1301
1302 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1303 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1304 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1306 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1307 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1308 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1309 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1310
1311 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1312 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1313 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1314 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1315 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1316 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1317 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1318
1319 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1320 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1321 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1322 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1323
1324 /* IPSR14 */
1325 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1326 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1327 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1328 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1329 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1330 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1331 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1332 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1333
1334 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1335 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1336 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1337 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1338 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1339 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1340 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1341 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1342
1343 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1344 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1345 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1346
1347 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1348 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1349 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1350 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1351
1352 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1353 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1354 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1355
1356 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1357 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1358
1359 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1360 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1361
1362 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1363 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1364
1365 /* IPSR15 */
1366 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1367
1368 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1369 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1370
1371 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1372 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1373 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1374
1375 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1376 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1377 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1378 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1379
1380 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1381 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1384 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1385 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1386 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1387
1388 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1389 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1392 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1393 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1394 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1395
1396 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1397 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1400 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1401 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1402 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1403
1404 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1405 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1408 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1409 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1410 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1411
1412 /* IPSR16 */
1413 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1414 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1415
1416 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1417 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1418
1419 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1420 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1421 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1422
1423 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1424 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1425 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1426 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1428 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1429 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1430
1431 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1432 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1433 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1434 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1436 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1437 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1438
1439 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1440 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1441 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1442 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1444 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1445 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1446 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1447
1448 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1449 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1450 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1452 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1453 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1454 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1455
1456 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1458 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1459 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1460 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1461 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1462 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1463 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1464
1465 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1466 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1467
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1468 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1469 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1470 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1472 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1473
1474 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1475 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1476 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1477 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1478 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1479 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1480 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1481
1482 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1483 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1484 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1485 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1486 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1487 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1488
1489 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1490 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1491 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1492 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1495 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1497 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1498
1499 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1500 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1501 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1502 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1503 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1504 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1505 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1506 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1507 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1508
1509 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1510 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1511 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1512 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1513 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1514 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1515 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1516 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1517 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1518 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1519 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1520
1521 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1522 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1523 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1524 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1525 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1526 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1527 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1528 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1529 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1530
1531 /* IPSR18 */
1532 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1533 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1534 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1535 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1536 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1537 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1538 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1539 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1540 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1541
1542 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1543 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1544 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1545 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1546 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1547 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1548 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1549 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1550 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1551
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1552/*
1553 * Static pins can not be muxed between different functions but
1554 * still need mark entries in the pinmux list. Add each static
1555 * pin to the list without an associated function. The sh-pfc
1556 * core will do the right thing and skip trying to mux the pin
1557 * while still applying configuration to it.
1558 */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1559#define FM(x) PINMUX_DATA(x##_MARK, 0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1560 PINMUX_STATIC
1561#undef FM
1562};
1563
1564/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1565 * Pins not associated with a GPIO port.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1566 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1567enum {
1568 GP_ASSIGN_LAST(),
1569 NOGP_ALL(),
1570};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1571
1572static const struct sh_pfc_pin pinmux_pins[] = {
1573 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1574 PINMUX_NOGP_ALL(),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1575};
1576
1577/* - AUDIO CLOCK ------------------------------------------------------------ */
1578static const unsigned int audio_clk_a_a_pins[] = {
1579 /* CLK A */
1580 RCAR_GP_PIN(6, 22),
1581};
1582static const unsigned int audio_clk_a_a_mux[] = {
1583 AUDIO_CLKA_A_MARK,
1584};
1585static const unsigned int audio_clk_a_b_pins[] = {
1586 /* CLK A */
1587 RCAR_GP_PIN(5, 4),
1588};
1589static const unsigned int audio_clk_a_b_mux[] = {
1590 AUDIO_CLKA_B_MARK,
1591};
1592static const unsigned int audio_clk_a_c_pins[] = {
1593 /* CLK A */
1594 RCAR_GP_PIN(5, 19),
1595};
1596static const unsigned int audio_clk_a_c_mux[] = {
1597 AUDIO_CLKA_C_MARK,
1598};
1599static const unsigned int audio_clk_b_a_pins[] = {
1600 /* CLK B */
1601 RCAR_GP_PIN(5, 12),
1602};
1603static const unsigned int audio_clk_b_a_mux[] = {
1604 AUDIO_CLKB_A_MARK,
1605};
1606static const unsigned int audio_clk_b_b_pins[] = {
1607 /* CLK B */
1608 RCAR_GP_PIN(6, 23),
1609};
1610static const unsigned int audio_clk_b_b_mux[] = {
1611 AUDIO_CLKB_B_MARK,
1612};
1613static const unsigned int audio_clk_c_a_pins[] = {
1614 /* CLK C */
1615 RCAR_GP_PIN(5, 21),
1616};
1617static const unsigned int audio_clk_c_a_mux[] = {
1618 AUDIO_CLKC_A_MARK,
1619};
1620static const unsigned int audio_clk_c_b_pins[] = {
1621 /* CLK C */
1622 RCAR_GP_PIN(5, 0),
1623};
1624static const unsigned int audio_clk_c_b_mux[] = {
1625 AUDIO_CLKC_B_MARK,
1626};
1627static const unsigned int audio_clkout_a_pins[] = {
1628 /* CLKOUT */
1629 RCAR_GP_PIN(5, 18),
1630};
1631static const unsigned int audio_clkout_a_mux[] = {
1632 AUDIO_CLKOUT_A_MARK,
1633};
1634static const unsigned int audio_clkout_b_pins[] = {
1635 /* CLKOUT */
1636 RCAR_GP_PIN(6, 28),
1637};
1638static const unsigned int audio_clkout_b_mux[] = {
1639 AUDIO_CLKOUT_B_MARK,
1640};
1641static const unsigned int audio_clkout_c_pins[] = {
1642 /* CLKOUT */
1643 RCAR_GP_PIN(5, 3),
1644};
1645static const unsigned int audio_clkout_c_mux[] = {
1646 AUDIO_CLKOUT_C_MARK,
1647};
1648static const unsigned int audio_clkout_d_pins[] = {
1649 /* CLKOUT */
1650 RCAR_GP_PIN(5, 21),
1651};
1652static const unsigned int audio_clkout_d_mux[] = {
1653 AUDIO_CLKOUT_D_MARK,
1654};
1655static const unsigned int audio_clkout1_a_pins[] = {
1656 /* CLKOUT1 */
1657 RCAR_GP_PIN(5, 15),
1658};
1659static const unsigned int audio_clkout1_a_mux[] = {
1660 AUDIO_CLKOUT1_A_MARK,
1661};
1662static const unsigned int audio_clkout1_b_pins[] = {
1663 /* CLKOUT1 */
1664 RCAR_GP_PIN(6, 29),
1665};
1666static const unsigned int audio_clkout1_b_mux[] = {
1667 AUDIO_CLKOUT1_B_MARK,
1668};
1669static const unsigned int audio_clkout2_a_pins[] = {
1670 /* CLKOUT2 */
1671 RCAR_GP_PIN(5, 16),
1672};
1673static const unsigned int audio_clkout2_a_mux[] = {
1674 AUDIO_CLKOUT2_A_MARK,
1675};
1676static const unsigned int audio_clkout2_b_pins[] = {
1677 /* CLKOUT2 */
1678 RCAR_GP_PIN(6, 30),
1679};
1680static const unsigned int audio_clkout2_b_mux[] = {
1681 AUDIO_CLKOUT2_B_MARK,
1682};
1683
1684static const unsigned int audio_clkout3_a_pins[] = {
1685 /* CLKOUT3 */
1686 RCAR_GP_PIN(5, 19),
1687};
1688static const unsigned int audio_clkout3_a_mux[] = {
1689 AUDIO_CLKOUT3_A_MARK,
1690};
1691static const unsigned int audio_clkout3_b_pins[] = {
1692 /* CLKOUT3 */
1693 RCAR_GP_PIN(6, 31),
1694};
1695static const unsigned int audio_clkout3_b_mux[] = {
1696 AUDIO_CLKOUT3_B_MARK,
1697};
1698
1699/* - EtherAVB --------------------------------------------------------------- */
1700static const unsigned int avb_link_pins[] = {
1701 /* AVB_LINK */
1702 RCAR_GP_PIN(2, 12),
1703};
1704static const unsigned int avb_link_mux[] = {
1705 AVB_LINK_MARK,
1706};
1707static const unsigned int avb_magic_pins[] = {
1708 /* AVB_MAGIC_ */
1709 RCAR_GP_PIN(2, 10),
1710};
1711static const unsigned int avb_magic_mux[] = {
1712 AVB_MAGIC_MARK,
1713};
1714static const unsigned int avb_phy_int_pins[] = {
1715 /* AVB_PHY_INT */
1716 RCAR_GP_PIN(2, 11),
1717};
1718static const unsigned int avb_phy_int_mux[] = {
1719 AVB_PHY_INT_MARK,
1720};
1721static const unsigned int avb_mdio_pins[] = {
1722 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1723 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1724};
1725static const unsigned int avb_mdio_mux[] = {
1726 AVB_MDC_MARK, AVB_MDIO_MARK,
1727};
1728static const unsigned int avb_mii_pins[] = {
1729 /*
1730 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1731 * AVB_TD1, AVB_TD2, AVB_TD3,
1732 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1733 * AVB_RD1, AVB_RD2, AVB_RD3,
1734 * AVB_TXCREFCLK
1735 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1736 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1737 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1738 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1739 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1740 PIN_AVB_TXCREFCLK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1741};
1742static const unsigned int avb_mii_mux[] = {
1743 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1744 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1745 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1746 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1747 AVB_TXCREFCLK_MARK,
1748};
1749static const unsigned int avb_avtp_pps_pins[] = {
1750 /* AVB_AVTP_PPS */
1751 RCAR_GP_PIN(2, 6),
1752};
1753static const unsigned int avb_avtp_pps_mux[] = {
1754 AVB_AVTP_PPS_MARK,
1755};
1756static const unsigned int avb_avtp_match_a_pins[] = {
1757 /* AVB_AVTP_MATCH_A */
1758 RCAR_GP_PIN(2, 13),
1759};
1760static const unsigned int avb_avtp_match_a_mux[] = {
1761 AVB_AVTP_MATCH_A_MARK,
1762};
1763static const unsigned int avb_avtp_capture_a_pins[] = {
1764 /* AVB_AVTP_CAPTURE_A */
1765 RCAR_GP_PIN(2, 14),
1766};
1767static const unsigned int avb_avtp_capture_a_mux[] = {
1768 AVB_AVTP_CAPTURE_A_MARK,
1769};
1770static const unsigned int avb_avtp_match_b_pins[] = {
1771 /* AVB_AVTP_MATCH_B */
1772 RCAR_GP_PIN(1, 8),
1773};
1774static const unsigned int avb_avtp_match_b_mux[] = {
1775 AVB_AVTP_MATCH_B_MARK,
1776};
1777static const unsigned int avb_avtp_capture_b_pins[] = {
1778 /* AVB_AVTP_CAPTURE_B */
1779 RCAR_GP_PIN(1, 11),
1780};
1781static const unsigned int avb_avtp_capture_b_mux[] = {
1782 AVB_AVTP_CAPTURE_B_MARK,
1783};
1784
1785/* - CAN ------------------------------------------------------------------ */
1786static const unsigned int can0_data_a_pins[] = {
1787 /* TX, RX */
1788 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1789};
1790
1791static const unsigned int can0_data_a_mux[] = {
1792 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1793};
1794
1795static const unsigned int can0_data_b_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1798};
1799
1800static const unsigned int can0_data_b_mux[] = {
1801 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1802};
1803
1804static const unsigned int can1_data_pins[] = {
1805 /* TX, RX */
1806 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1807};
1808
1809static const unsigned int can1_data_mux[] = {
1810 CAN1_TX_MARK, CAN1_RX_MARK,
1811};
1812
1813/* - CAN Clock -------------------------------------------------------------- */
1814static const unsigned int can_clk_pins[] = {
1815 /* CLK */
1816 RCAR_GP_PIN(1, 25),
1817};
1818
1819static const unsigned int can_clk_mux[] = {
1820 CAN_CLK_MARK,
1821};
1822
1823/* - CAN FD --------------------------------------------------------------- */
1824static const unsigned int canfd0_data_a_pins[] = {
1825 /* TX, RX */
1826 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1827};
1828
1829static const unsigned int canfd0_data_a_mux[] = {
1830 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1831};
1832
1833static const unsigned int canfd0_data_b_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1836};
1837
1838static const unsigned int canfd0_data_b_mux[] = {
1839 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1840};
1841
1842static const unsigned int canfd1_data_pins[] = {
1843 /* TX, RX */
1844 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1845};
1846
1847static const unsigned int canfd1_data_mux[] = {
1848 CANFD1_TX_MARK, CANFD1_RX_MARK,
1849};
1850
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]1851#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1852/* - DRIF0 --------------------------------------------------------------- */
1853static const unsigned int drif0_ctrl_a_pins[] = {
1854 /* CLK, SYNC */
1855 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1856};
1857
1858static const unsigned int drif0_ctrl_a_mux[] = {
1859 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1860};
1861
1862static const unsigned int drif0_data0_a_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(6, 10),
1865};
1866
1867static const unsigned int drif0_data0_a_mux[] = {
1868 RIF0_D0_A_MARK,
1869};
1870
1871static const unsigned int drif0_data1_a_pins[] = {
1872 /* D1 */
1873 RCAR_GP_PIN(6, 7),
1874};
1875
1876static const unsigned int drif0_data1_a_mux[] = {
1877 RIF0_D1_A_MARK,
1878};
1879
1880static const unsigned int drif0_ctrl_b_pins[] = {
1881 /* CLK, SYNC */
1882 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1883};
1884
1885static const unsigned int drif0_ctrl_b_mux[] = {
1886 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1887};
1888
1889static const unsigned int drif0_data0_b_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 1),
1892};
1893
1894static const unsigned int drif0_data0_b_mux[] = {
1895 RIF0_D0_B_MARK,
1896};
1897
1898static const unsigned int drif0_data1_b_pins[] = {
1899 /* D1 */
1900 RCAR_GP_PIN(5, 2),
1901};
1902
1903static const unsigned int drif0_data1_b_mux[] = {
1904 RIF0_D1_B_MARK,
1905};
1906
1907static const unsigned int drif0_ctrl_c_pins[] = {
1908 /* CLK, SYNC */
1909 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1910};
1911
1912static const unsigned int drif0_ctrl_c_mux[] = {
1913 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1914};
1915
1916static const unsigned int drif0_data0_c_pins[] = {
1917 /* D0 */
1918 RCAR_GP_PIN(5, 13),
1919};
1920
1921static const unsigned int drif0_data0_c_mux[] = {
1922 RIF0_D0_C_MARK,
1923};
1924
1925static const unsigned int drif0_data1_c_pins[] = {
1926 /* D1 */
1927 RCAR_GP_PIN(5, 14),
1928};
1929
1930static const unsigned int drif0_data1_c_mux[] = {
1931 RIF0_D1_C_MARK,
1932};
1933
1934/* - DRIF1 --------------------------------------------------------------- */
1935static const unsigned int drif1_ctrl_a_pins[] = {
1936 /* CLK, SYNC */
1937 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1938};
1939
1940static const unsigned int drif1_ctrl_a_mux[] = {
1941 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1942};
1943
1944static const unsigned int drif1_data0_a_pins[] = {
1945 /* D0 */
1946 RCAR_GP_PIN(6, 19),
1947};
1948
1949static const unsigned int drif1_data0_a_mux[] = {
1950 RIF1_D0_A_MARK,
1951};
1952
1953static const unsigned int drif1_data1_a_pins[] = {
1954 /* D1 */
1955 RCAR_GP_PIN(6, 20),
1956};
1957
1958static const unsigned int drif1_data1_a_mux[] = {
1959 RIF1_D1_A_MARK,
1960};
1961
1962static const unsigned int drif1_ctrl_b_pins[] = {
1963 /* CLK, SYNC */
1964 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1965};
1966
1967static const unsigned int drif1_ctrl_b_mux[] = {
1968 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1969};
1970
1971static const unsigned int drif1_data0_b_pins[] = {
1972 /* D0 */
1973 RCAR_GP_PIN(5, 7),
1974};
1975
1976static const unsigned int drif1_data0_b_mux[] = {
1977 RIF1_D0_B_MARK,
1978};
1979
1980static const unsigned int drif1_data1_b_pins[] = {
1981 /* D1 */
1982 RCAR_GP_PIN(5, 8),
1983};
1984
1985static const unsigned int drif1_data1_b_mux[] = {
1986 RIF1_D1_B_MARK,
1987};
1988
1989static const unsigned int drif1_ctrl_c_pins[] = {
1990 /* CLK, SYNC */
1991 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1992};
1993
1994static const unsigned int drif1_ctrl_c_mux[] = {
1995 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1996};
1997
1998static const unsigned int drif1_data0_c_pins[] = {
1999 /* D0 */
2000 RCAR_GP_PIN(5, 6),
2001};
2002
2003static const unsigned int drif1_data0_c_mux[] = {
2004 RIF1_D0_C_MARK,
2005};
2006
2007static const unsigned int drif1_data1_c_pins[] = {
2008 /* D1 */
2009 RCAR_GP_PIN(5, 10),
2010};
2011
2012static const unsigned int drif1_data1_c_mux[] = {
2013 RIF1_D1_C_MARK,
2014};
2015
2016/* - DRIF2 --------------------------------------------------------------- */
2017static const unsigned int drif2_ctrl_a_pins[] = {
2018 /* CLK, SYNC */
2019 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2020};
2021
2022static const unsigned int drif2_ctrl_a_mux[] = {
2023 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2024};
2025
2026static const unsigned int drif2_data0_a_pins[] = {
2027 /* D0 */
2028 RCAR_GP_PIN(6, 7),
2029};
2030
2031static const unsigned int drif2_data0_a_mux[] = {
2032 RIF2_D0_A_MARK,
2033};
2034
2035static const unsigned int drif2_data1_a_pins[] = {
2036 /* D1 */
2037 RCAR_GP_PIN(6, 10),
2038};
2039
2040static const unsigned int drif2_data1_a_mux[] = {
2041 RIF2_D1_A_MARK,
2042};
2043
2044static const unsigned int drif2_ctrl_b_pins[] = {
2045 /* CLK, SYNC */
2046 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2047};
2048
2049static const unsigned int drif2_ctrl_b_mux[] = {
2050 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2051};
2052
2053static const unsigned int drif2_data0_b_pins[] = {
2054 /* D0 */
2055 RCAR_GP_PIN(6, 30),
2056};
2057
2058static const unsigned int drif2_data0_b_mux[] = {
2059 RIF2_D0_B_MARK,
2060};
2061
2062static const unsigned int drif2_data1_b_pins[] = {
2063 /* D1 */
2064 RCAR_GP_PIN(6, 31),
2065};
2066
2067static const unsigned int drif2_data1_b_mux[] = {
2068 RIF2_D1_B_MARK,
2069};
2070
2071/* - DRIF3 --------------------------------------------------------------- */
2072static const unsigned int drif3_ctrl_a_pins[] = {
2073 /* CLK, SYNC */
2074 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2075};
2076
2077static const unsigned int drif3_ctrl_a_mux[] = {
2078 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2079};
2080
2081static const unsigned int drif3_data0_a_pins[] = {
2082 /* D0 */
2083 RCAR_GP_PIN(6, 19),
2084};
2085
2086static const unsigned int drif3_data0_a_mux[] = {
2087 RIF3_D0_A_MARK,
2088};
2089
2090static const unsigned int drif3_data1_a_pins[] = {
2091 /* D1 */
2092 RCAR_GP_PIN(6, 20),
2093};
2094
2095static const unsigned int drif3_data1_a_mux[] = {
2096 RIF3_D1_A_MARK,
2097};
2098
2099static const unsigned int drif3_ctrl_b_pins[] = {
2100 /* CLK, SYNC */
2101 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2102};
2103
2104static const unsigned int drif3_ctrl_b_mux[] = {
2105 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2106};
2107
2108static const unsigned int drif3_data0_b_pins[] = {
2109 /* D0 */
2110 RCAR_GP_PIN(6, 28),
2111};
2112
2113static const unsigned int drif3_data0_b_mux[] = {
2114 RIF3_D0_B_MARK,
2115};
2116
2117static const unsigned int drif3_data1_b_pins[] = {
2118 /* D1 */
2119 RCAR_GP_PIN(6, 29),
2120};
2121
2122static const unsigned int drif3_data1_b_mux[] = {
2123 RIF3_D1_B_MARK,
2124};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]2125#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2126
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2127/* - DU --------------------------------------------------------------------- */
2128static const unsigned int du_rgb666_pins[] = {
2129 /* R[7:2], G[7:2], B[7:2] */
2130 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2131 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2132 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2133 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2134 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2135 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2136};
2137
2138static const unsigned int du_rgb666_mux[] = {
2139 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2140 DU_DR3_MARK, DU_DR2_MARK,
2141 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2142 DU_DG3_MARK, DU_DG2_MARK,
2143 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2144 DU_DB3_MARK, DU_DB2_MARK,
2145};
2146
2147static const unsigned int du_rgb888_pins[] = {
2148 /* R[7:0], G[7:0], B[7:0] */
2149 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2150 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2151 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2152 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2153 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2154 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2155 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2156 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2157 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2158};
2159
2160static const unsigned int du_rgb888_mux[] = {
2161 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2162 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2163 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2164 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2165 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2166 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2167};
2168
2169static const unsigned int du_clk_out_0_pins[] = {
2170 /* CLKOUT */
2171 RCAR_GP_PIN(1, 27),
2172};
2173
2174static const unsigned int du_clk_out_0_mux[] = {
2175 DU_DOTCLKOUT0_MARK
2176};
2177
2178static const unsigned int du_clk_out_1_pins[] = {
2179 /* CLKOUT */
2180 RCAR_GP_PIN(2, 3),
2181};
2182
2183static const unsigned int du_clk_out_1_mux[] = {
2184 DU_DOTCLKOUT1_MARK
2185};
2186
2187static const unsigned int du_sync_pins[] = {
2188 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2189 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2190};
2191
2192static const unsigned int du_sync_mux[] = {
2193 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2194};
2195
2196static const unsigned int du_oddf_pins[] = {
2197 /* EXDISP/EXODDF/EXCDE */
2198 RCAR_GP_PIN(2, 2),
2199};
2200
2201static const unsigned int du_oddf_mux[] = {
2202 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2203};
2204
2205static const unsigned int du_cde_pins[] = {
2206 /* CDE */
2207 RCAR_GP_PIN(2, 0),
2208};
2209
2210static const unsigned int du_cde_mux[] = {
2211 DU_CDE_MARK,
2212};
2213
2214static const unsigned int du_disp_pins[] = {
2215 /* DISP */
2216 RCAR_GP_PIN(2, 1),
2217};
2218
2219static const unsigned int du_disp_mux[] = {
2220 DU_DISP_MARK,
2221};
2222
2223/* - HSCIF0 ----------------------------------------------------------------- */
2224static const unsigned int hscif0_data_pins[] = {
2225 /* RX, TX */
2226 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2227};
2228
2229static const unsigned int hscif0_data_mux[] = {
2230 HRX0_MARK, HTX0_MARK,
2231};
2232
2233static const unsigned int hscif0_clk_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(5, 12),
2236};
2237
2238static const unsigned int hscif0_clk_mux[] = {
2239 HSCK0_MARK,
2240};
2241
2242static const unsigned int hscif0_ctrl_pins[] = {
2243 /* RTS, CTS */
2244 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2245};
2246
2247static const unsigned int hscif0_ctrl_mux[] = {
2248 HRTS0_N_MARK, HCTS0_N_MARK,
2249};
2250
2251/* - HSCIF1 ----------------------------------------------------------------- */
2252static const unsigned int hscif1_data_a_pins[] = {
2253 /* RX, TX */
2254 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2255};
2256
2257static const unsigned int hscif1_data_a_mux[] = {
2258 HRX1_A_MARK, HTX1_A_MARK,
2259};
2260
2261static const unsigned int hscif1_clk_a_pins[] = {
2262 /* SCK */
2263 RCAR_GP_PIN(6, 21),
2264};
2265
2266static const unsigned int hscif1_clk_a_mux[] = {
2267 HSCK1_A_MARK,
2268};
2269
2270static const unsigned int hscif1_ctrl_a_pins[] = {
2271 /* RTS, CTS */
2272 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2273};
2274
2275static const unsigned int hscif1_ctrl_a_mux[] = {
2276 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2277};
2278
2279static const unsigned int hscif1_data_b_pins[] = {
2280 /* RX, TX */
2281 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2282};
2283
2284static const unsigned int hscif1_data_b_mux[] = {
2285 HRX1_B_MARK, HTX1_B_MARK,
2286};
2287
2288static const unsigned int hscif1_clk_b_pins[] = {
2289 /* SCK */
2290 RCAR_GP_PIN(5, 0),
2291};
2292
2293static const unsigned int hscif1_clk_b_mux[] = {
2294 HSCK1_B_MARK,
2295};
2296
2297static const unsigned int hscif1_ctrl_b_pins[] = {
2298 /* RTS, CTS */
2299 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2300};
2301
2302static const unsigned int hscif1_ctrl_b_mux[] = {
2303 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2304};
2305
2306/* - HSCIF2 ----------------------------------------------------------------- */
2307static const unsigned int hscif2_data_a_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2310};
2311
2312static const unsigned int hscif2_data_a_mux[] = {
2313 HRX2_A_MARK, HTX2_A_MARK,
2314};
2315
2316static const unsigned int hscif2_clk_a_pins[] = {
2317 /* SCK */
2318 RCAR_GP_PIN(6, 10),
2319};
2320
2321static const unsigned int hscif2_clk_a_mux[] = {
2322 HSCK2_A_MARK,
2323};
2324
2325static const unsigned int hscif2_ctrl_a_pins[] = {
2326 /* RTS, CTS */
2327 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2328};
2329
2330static const unsigned int hscif2_ctrl_a_mux[] = {
2331 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2332};
2333
2334static const unsigned int hscif2_data_b_pins[] = {
2335 /* RX, TX */
2336 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2337};
2338
2339static const unsigned int hscif2_data_b_mux[] = {
2340 HRX2_B_MARK, HTX2_B_MARK,
2341};
2342
2343static const unsigned int hscif2_clk_b_pins[] = {
2344 /* SCK */
2345 RCAR_GP_PIN(6, 21),
2346};
2347
2348static const unsigned int hscif2_clk_b_mux[] = {
2349 HSCK2_B_MARK,
2350};
2351
2352static const unsigned int hscif2_ctrl_b_pins[] = {
2353 /* RTS, CTS */
2354 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2355};
2356
2357static const unsigned int hscif2_ctrl_b_mux[] = {
2358 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2359};
2360
2361static const unsigned int hscif2_data_c_pins[] = {
2362 /* RX, TX */
2363 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2364};
2365
2366static const unsigned int hscif2_data_c_mux[] = {
2367 HRX2_C_MARK, HTX2_C_MARK,
2368};
2369
2370static const unsigned int hscif2_clk_c_pins[] = {
2371 /* SCK */
2372 RCAR_GP_PIN(6, 24),
2373};
2374
2375static const unsigned int hscif2_clk_c_mux[] = {
2376 HSCK2_C_MARK,
2377};
2378
2379static const unsigned int hscif2_ctrl_c_pins[] = {
2380 /* RTS, CTS */
2381 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2382};
2383
2384static const unsigned int hscif2_ctrl_c_mux[] = {
2385 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2386};
2387
2388/* - HSCIF3 ----------------------------------------------------------------- */
2389static const unsigned int hscif3_data_a_pins[] = {
2390 /* RX, TX */
2391 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2392};
2393
2394static const unsigned int hscif3_data_a_mux[] = {
2395 HRX3_A_MARK, HTX3_A_MARK,
2396};
2397
2398static const unsigned int hscif3_clk_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(1, 22),
2401};
2402
2403static const unsigned int hscif3_clk_mux[] = {
2404 HSCK3_MARK,
2405};
2406
2407static const unsigned int hscif3_ctrl_pins[] = {
2408 /* RTS, CTS */
2409 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2410};
2411
2412static const unsigned int hscif3_ctrl_mux[] = {
2413 HRTS3_N_MARK, HCTS3_N_MARK,
2414};
2415
2416static const unsigned int hscif3_data_b_pins[] = {
2417 /* RX, TX */
2418 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2419};
2420
2421static const unsigned int hscif3_data_b_mux[] = {
2422 HRX3_B_MARK, HTX3_B_MARK,
2423};
2424
2425static const unsigned int hscif3_data_c_pins[] = {
2426 /* RX, TX */
2427 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2428};
2429
2430static const unsigned int hscif3_data_c_mux[] = {
2431 HRX3_C_MARK, HTX3_C_MARK,
2432};
2433
2434static const unsigned int hscif3_data_d_pins[] = {
2435 /* RX, TX */
2436 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2437};
2438
2439static const unsigned int hscif3_data_d_mux[] = {
2440 HRX3_D_MARK, HTX3_D_MARK,
2441};
2442
2443/* - HSCIF4 ----------------------------------------------------------------- */
2444static const unsigned int hscif4_data_a_pins[] = {
2445 /* RX, TX */
2446 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2447};
2448
2449static const unsigned int hscif4_data_a_mux[] = {
2450 HRX4_A_MARK, HTX4_A_MARK,
2451};
2452
2453static const unsigned int hscif4_clk_pins[] = {
2454 /* SCK */
2455 RCAR_GP_PIN(1, 11),
2456};
2457
2458static const unsigned int hscif4_clk_mux[] = {
2459 HSCK4_MARK,
2460};
2461
2462static const unsigned int hscif4_ctrl_pins[] = {
2463 /* RTS, CTS */
2464 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2465};
2466
2467static const unsigned int hscif4_ctrl_mux[] = {
2468 HRTS4_N_MARK, HCTS4_N_MARK,
2469};
2470
2471static const unsigned int hscif4_data_b_pins[] = {
2472 /* RX, TX */
2473 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2474};
2475
2476static const unsigned int hscif4_data_b_mux[] = {
2477 HRX4_B_MARK, HTX4_B_MARK,
2478};
2479
2480/* - I2C -------------------------------------------------------------------- */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2481static const unsigned int i2c0_pins[] = {
2482 /* SCL, SDA */
2483 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2484};
2485
2486static const unsigned int i2c0_mux[] = {
2487 SCL0_MARK, SDA0_MARK,
2488};
2489
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2490static const unsigned int i2c1_a_pins[] = {
2491 /* SDA, SCL */
2492 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2493};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2494
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2495static const unsigned int i2c1_a_mux[] = {
2496 SDA1_A_MARK, SCL1_A_MARK,
2497};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2498
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2499static const unsigned int i2c1_b_pins[] = {
2500 /* SDA, SCL */
2501 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2502};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2503
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2504static const unsigned int i2c1_b_mux[] = {
2505 SDA1_B_MARK, SCL1_B_MARK,
2506};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2507
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2508static const unsigned int i2c2_a_pins[] = {
2509 /* SDA, SCL */
2510 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2511};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2512
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2513static const unsigned int i2c2_a_mux[] = {
2514 SDA2_A_MARK, SCL2_A_MARK,
2515};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2516
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2517static const unsigned int i2c2_b_pins[] = {
2518 /* SDA, SCL */
2519 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2520};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2521
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2522static const unsigned int i2c2_b_mux[] = {
2523 SDA2_B_MARK, SCL2_B_MARK,
2524};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2525
2526static const unsigned int i2c3_pins[] = {
2527 /* SCL, SDA */
2528 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2529};
2530
2531static const unsigned int i2c3_mux[] = {
2532 SCL3_MARK, SDA3_MARK,
2533};
2534
2535static const unsigned int i2c5_pins[] = {
2536 /* SCL, SDA */
2537 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2538};
2539
2540static const unsigned int i2c5_mux[] = {
2541 SCL5_MARK, SDA5_MARK,
2542};
2543
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2544static const unsigned int i2c6_a_pins[] = {
2545 /* SDA, SCL */
2546 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2547};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2548
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2549static const unsigned int i2c6_a_mux[] = {
2550 SDA6_A_MARK, SCL6_A_MARK,
2551};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2552
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2553static const unsigned int i2c6_b_pins[] = {
2554 /* SDA, SCL */
2555 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2556};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2557
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2558static const unsigned int i2c6_b_mux[] = {
2559 SDA6_B_MARK, SCL6_B_MARK,
2560};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2561
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2562static const unsigned int i2c6_c_pins[] = {
2563 /* SDA, SCL */
2564 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2565};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2566
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2567static const unsigned int i2c6_c_mux[] = {
2568 SDA6_C_MARK, SCL6_C_MARK,
2569};
2570
2571/* - INTC-EX ---------------------------------------------------------------- */
2572static const unsigned int intc_ex_irq0_pins[] = {
2573 /* IRQ0 */
2574 RCAR_GP_PIN(2, 0),
2575};
2576static const unsigned int intc_ex_irq0_mux[] = {
2577 IRQ0_MARK,
2578};
2579static const unsigned int intc_ex_irq1_pins[] = {
2580 /* IRQ1 */
2581 RCAR_GP_PIN(2, 1),
2582};
2583static const unsigned int intc_ex_irq1_mux[] = {
2584 IRQ1_MARK,
2585};
2586static const unsigned int intc_ex_irq2_pins[] = {
2587 /* IRQ2 */
2588 RCAR_GP_PIN(2, 2),
2589};
2590static const unsigned int intc_ex_irq2_mux[] = {
2591 IRQ2_MARK,
2592};
2593static const unsigned int intc_ex_irq3_pins[] = {
2594 /* IRQ3 */
2595 RCAR_GP_PIN(2, 3),
2596};
2597static const unsigned int intc_ex_irq3_mux[] = {
2598 IRQ3_MARK,
2599};
2600static const unsigned int intc_ex_irq4_pins[] = {
2601 /* IRQ4 */
2602 RCAR_GP_PIN(2, 4),
2603};
2604static const unsigned int intc_ex_irq4_mux[] = {
2605 IRQ4_MARK,
2606};
2607static const unsigned int intc_ex_irq5_pins[] = {
2608 /* IRQ5 */
2609 RCAR_GP_PIN(2, 5),
2610};
2611static const unsigned int intc_ex_irq5_mux[] = {
2612 IRQ5_MARK,
2613};
2614
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]2615#ifdef CONFIG_PINCTRL_PFC_R8A77965
2616/* - MLB+ ------------------------------------------------------------------- */
2617static const unsigned int mlb_3pin_pins[] = {
2618 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2619};
2620static const unsigned int mlb_3pin_mux[] = {
2621 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2622};
2623#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
2624
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2625/* - MSIOF0 ----------------------------------------------------------------- */
2626static const unsigned int msiof0_clk_pins[] = {
2627 /* SCK */
2628 RCAR_GP_PIN(5, 17),
2629};
2630static const unsigned int msiof0_clk_mux[] = {
2631 MSIOF0_SCK_MARK,
2632};
2633static const unsigned int msiof0_sync_pins[] = {
2634 /* SYNC */
2635 RCAR_GP_PIN(5, 18),
2636};
2637static const unsigned int msiof0_sync_mux[] = {
2638 MSIOF0_SYNC_MARK,
2639};
2640static const unsigned int msiof0_ss1_pins[] = {
2641 /* SS1 */
2642 RCAR_GP_PIN(5, 19),
2643};
2644static const unsigned int msiof0_ss1_mux[] = {
2645 MSIOF0_SS1_MARK,
2646};
2647static const unsigned int msiof0_ss2_pins[] = {
2648 /* SS2 */
2649 RCAR_GP_PIN(5, 21),
2650};
2651static const unsigned int msiof0_ss2_mux[] = {
2652 MSIOF0_SS2_MARK,
2653};
2654static const unsigned int msiof0_txd_pins[] = {
2655 /* TXD */
2656 RCAR_GP_PIN(5, 20),
2657};
2658static const unsigned int msiof0_txd_mux[] = {
2659 MSIOF0_TXD_MARK,
2660};
2661static const unsigned int msiof0_rxd_pins[] = {
2662 /* RXD */
2663 RCAR_GP_PIN(5, 22),
2664};
2665static const unsigned int msiof0_rxd_mux[] = {
2666 MSIOF0_RXD_MARK,
2667};
2668/* - MSIOF1 ----------------------------------------------------------------- */
2669static const unsigned int msiof1_clk_a_pins[] = {
2670 /* SCK */
2671 RCAR_GP_PIN(6, 8),
2672};
2673static const unsigned int msiof1_clk_a_mux[] = {
2674 MSIOF1_SCK_A_MARK,
2675};
2676static const unsigned int msiof1_sync_a_pins[] = {
2677 /* SYNC */
2678 RCAR_GP_PIN(6, 9),
2679};
2680static const unsigned int msiof1_sync_a_mux[] = {
2681 MSIOF1_SYNC_A_MARK,
2682};
2683static const unsigned int msiof1_ss1_a_pins[] = {
2684 /* SS1 */
2685 RCAR_GP_PIN(6, 5),
2686};
2687static const unsigned int msiof1_ss1_a_mux[] = {
2688 MSIOF1_SS1_A_MARK,
2689};
2690static const unsigned int msiof1_ss2_a_pins[] = {
2691 /* SS2 */
2692 RCAR_GP_PIN(6, 6),
2693};
2694static const unsigned int msiof1_ss2_a_mux[] = {
2695 MSIOF1_SS2_A_MARK,
2696};
2697static const unsigned int msiof1_txd_a_pins[] = {
2698 /* TXD */
2699 RCAR_GP_PIN(6, 7),
2700};
2701static const unsigned int msiof1_txd_a_mux[] = {
2702 MSIOF1_TXD_A_MARK,
2703};
2704static const unsigned int msiof1_rxd_a_pins[] = {
2705 /* RXD */
2706 RCAR_GP_PIN(6, 10),
2707};
2708static const unsigned int msiof1_rxd_a_mux[] = {
2709 MSIOF1_RXD_A_MARK,
2710};
2711static const unsigned int msiof1_clk_b_pins[] = {
2712 /* SCK */
2713 RCAR_GP_PIN(5, 9),
2714};
2715static const unsigned int msiof1_clk_b_mux[] = {
2716 MSIOF1_SCK_B_MARK,
2717};
2718static const unsigned int msiof1_sync_b_pins[] = {
2719 /* SYNC */
2720 RCAR_GP_PIN(5, 3),
2721};
2722static const unsigned int msiof1_sync_b_mux[] = {
2723 MSIOF1_SYNC_B_MARK,
2724};
2725static const unsigned int msiof1_ss1_b_pins[] = {
2726 /* SS1 */
2727 RCAR_GP_PIN(5, 4),
2728};
2729static const unsigned int msiof1_ss1_b_mux[] = {
2730 MSIOF1_SS1_B_MARK,
2731};
2732static const unsigned int msiof1_ss2_b_pins[] = {
2733 /* SS2 */
2734 RCAR_GP_PIN(5, 0),
2735};
2736static const unsigned int msiof1_ss2_b_mux[] = {
2737 MSIOF1_SS2_B_MARK,
2738};
2739static const unsigned int msiof1_txd_b_pins[] = {
2740 /* TXD */
2741 RCAR_GP_PIN(5, 8),
2742};
2743static const unsigned int msiof1_txd_b_mux[] = {
2744 MSIOF1_TXD_B_MARK,
2745};
2746static const unsigned int msiof1_rxd_b_pins[] = {
2747 /* RXD */
2748 RCAR_GP_PIN(5, 7),
2749};
2750static const unsigned int msiof1_rxd_b_mux[] = {
2751 MSIOF1_RXD_B_MARK,
2752};
2753static const unsigned int msiof1_clk_c_pins[] = {
2754 /* SCK */
2755 RCAR_GP_PIN(6, 17),
2756};
2757static const unsigned int msiof1_clk_c_mux[] = {
2758 MSIOF1_SCK_C_MARK,
2759};
2760static const unsigned int msiof1_sync_c_pins[] = {
2761 /* SYNC */
2762 RCAR_GP_PIN(6, 18),
2763};
2764static const unsigned int msiof1_sync_c_mux[] = {
2765 MSIOF1_SYNC_C_MARK,
2766};
2767static const unsigned int msiof1_ss1_c_pins[] = {
2768 /* SS1 */
2769 RCAR_GP_PIN(6, 21),
2770};
2771static const unsigned int msiof1_ss1_c_mux[] = {
2772 MSIOF1_SS1_C_MARK,
2773};
2774static const unsigned int msiof1_ss2_c_pins[] = {
2775 /* SS2 */
2776 RCAR_GP_PIN(6, 27),
2777};
2778static const unsigned int msiof1_ss2_c_mux[] = {
2779 MSIOF1_SS2_C_MARK,
2780};
2781static const unsigned int msiof1_txd_c_pins[] = {
2782 /* TXD */
2783 RCAR_GP_PIN(6, 20),
2784};
2785static const unsigned int msiof1_txd_c_mux[] = {
2786 MSIOF1_TXD_C_MARK,
2787};
2788static const unsigned int msiof1_rxd_c_pins[] = {
2789 /* RXD */
2790 RCAR_GP_PIN(6, 19),
2791};
2792static const unsigned int msiof1_rxd_c_mux[] = {
2793 MSIOF1_RXD_C_MARK,
2794};
2795static const unsigned int msiof1_clk_d_pins[] = {
2796 /* SCK */
2797 RCAR_GP_PIN(5, 12),
2798};
2799static const unsigned int msiof1_clk_d_mux[] = {
2800 MSIOF1_SCK_D_MARK,
2801};
2802static const unsigned int msiof1_sync_d_pins[] = {
2803 /* SYNC */
2804 RCAR_GP_PIN(5, 15),
2805};
2806static const unsigned int msiof1_sync_d_mux[] = {
2807 MSIOF1_SYNC_D_MARK,
2808};
2809static const unsigned int msiof1_ss1_d_pins[] = {
2810 /* SS1 */
2811 RCAR_GP_PIN(5, 16),
2812};
2813static const unsigned int msiof1_ss1_d_mux[] = {
2814 MSIOF1_SS1_D_MARK,
2815};
2816static const unsigned int msiof1_ss2_d_pins[] = {
2817 /* SS2 */
2818 RCAR_GP_PIN(5, 21),
2819};
2820static const unsigned int msiof1_ss2_d_mux[] = {
2821 MSIOF1_SS2_D_MARK,
2822};
2823static const unsigned int msiof1_txd_d_pins[] = {
2824 /* TXD */
2825 RCAR_GP_PIN(5, 14),
2826};
2827static const unsigned int msiof1_txd_d_mux[] = {
2828 MSIOF1_TXD_D_MARK,
2829};
2830static const unsigned int msiof1_rxd_d_pins[] = {
2831 /* RXD */
2832 RCAR_GP_PIN(5, 13),
2833};
2834static const unsigned int msiof1_rxd_d_mux[] = {
2835 MSIOF1_RXD_D_MARK,
2836};
2837static const unsigned int msiof1_clk_e_pins[] = {
2838 /* SCK */
2839 RCAR_GP_PIN(3, 0),
2840};
2841static const unsigned int msiof1_clk_e_mux[] = {
2842 MSIOF1_SCK_E_MARK,
2843};
2844static const unsigned int msiof1_sync_e_pins[] = {
2845 /* SYNC */
2846 RCAR_GP_PIN(3, 1),
2847};
2848static const unsigned int msiof1_sync_e_mux[] = {
2849 MSIOF1_SYNC_E_MARK,
2850};
2851static const unsigned int msiof1_ss1_e_pins[] = {
2852 /* SS1 */
2853 RCAR_GP_PIN(3, 4),
2854};
2855static const unsigned int msiof1_ss1_e_mux[] = {
2856 MSIOF1_SS1_E_MARK,
2857};
2858static const unsigned int msiof1_ss2_e_pins[] = {
2859 /* SS2 */
2860 RCAR_GP_PIN(3, 5),
2861};
2862static const unsigned int msiof1_ss2_e_mux[] = {
2863 MSIOF1_SS2_E_MARK,
2864};
2865static const unsigned int msiof1_txd_e_pins[] = {
2866 /* TXD */
2867 RCAR_GP_PIN(3, 3),
2868};
2869static const unsigned int msiof1_txd_e_mux[] = {
2870 MSIOF1_TXD_E_MARK,
2871};
2872static const unsigned int msiof1_rxd_e_pins[] = {
2873 /* RXD */
2874 RCAR_GP_PIN(3, 2),
2875};
2876static const unsigned int msiof1_rxd_e_mux[] = {
2877 MSIOF1_RXD_E_MARK,
2878};
2879static const unsigned int msiof1_clk_f_pins[] = {
2880 /* SCK */
2881 RCAR_GP_PIN(5, 23),
2882};
2883static const unsigned int msiof1_clk_f_mux[] = {
2884 MSIOF1_SCK_F_MARK,
2885};
2886static const unsigned int msiof1_sync_f_pins[] = {
2887 /* SYNC */
2888 RCAR_GP_PIN(5, 24),
2889};
2890static const unsigned int msiof1_sync_f_mux[] = {
2891 MSIOF1_SYNC_F_MARK,
2892};
2893static const unsigned int msiof1_ss1_f_pins[] = {
2894 /* SS1 */
2895 RCAR_GP_PIN(6, 1),
2896};
2897static const unsigned int msiof1_ss1_f_mux[] = {
2898 MSIOF1_SS1_F_MARK,
2899};
2900static const unsigned int msiof1_ss2_f_pins[] = {
2901 /* SS2 */
2902 RCAR_GP_PIN(6, 2),
2903};
2904static const unsigned int msiof1_ss2_f_mux[] = {
2905 MSIOF1_SS2_F_MARK,
2906};
2907static const unsigned int msiof1_txd_f_pins[] = {
2908 /* TXD */
2909 RCAR_GP_PIN(6, 0),
2910};
2911static const unsigned int msiof1_txd_f_mux[] = {
2912 MSIOF1_TXD_F_MARK,
2913};
2914static const unsigned int msiof1_rxd_f_pins[] = {
2915 /* RXD */
2916 RCAR_GP_PIN(5, 25),
2917};
2918static const unsigned int msiof1_rxd_f_mux[] = {
2919 MSIOF1_RXD_F_MARK,
2920};
2921static const unsigned int msiof1_clk_g_pins[] = {
2922 /* SCK */
2923 RCAR_GP_PIN(3, 6),
2924};
2925static const unsigned int msiof1_clk_g_mux[] = {
2926 MSIOF1_SCK_G_MARK,
2927};
2928static const unsigned int msiof1_sync_g_pins[] = {
2929 /* SYNC */
2930 RCAR_GP_PIN(3, 7),
2931};
2932static const unsigned int msiof1_sync_g_mux[] = {
2933 MSIOF1_SYNC_G_MARK,
2934};
2935static const unsigned int msiof1_ss1_g_pins[] = {
2936 /* SS1 */
2937 RCAR_GP_PIN(3, 10),
2938};
2939static const unsigned int msiof1_ss1_g_mux[] = {
2940 MSIOF1_SS1_G_MARK,
2941};
2942static const unsigned int msiof1_ss2_g_pins[] = {
2943 /* SS2 */
2944 RCAR_GP_PIN(3, 11),
2945};
2946static const unsigned int msiof1_ss2_g_mux[] = {
2947 MSIOF1_SS2_G_MARK,
2948};
2949static const unsigned int msiof1_txd_g_pins[] = {
2950 /* TXD */
2951 RCAR_GP_PIN(3, 9),
2952};
2953static const unsigned int msiof1_txd_g_mux[] = {
2954 MSIOF1_TXD_G_MARK,
2955};
2956static const unsigned int msiof1_rxd_g_pins[] = {
2957 /* RXD */
2958 RCAR_GP_PIN(3, 8),
2959};
2960static const unsigned int msiof1_rxd_g_mux[] = {
2961 MSIOF1_RXD_G_MARK,
2962};
2963/* - MSIOF2 ----------------------------------------------------------------- */
2964static const unsigned int msiof2_clk_a_pins[] = {
2965 /* SCK */
2966 RCAR_GP_PIN(1, 9),
2967};
2968static const unsigned int msiof2_clk_a_mux[] = {
2969 MSIOF2_SCK_A_MARK,
2970};
2971static const unsigned int msiof2_sync_a_pins[] = {
2972 /* SYNC */
2973 RCAR_GP_PIN(1, 8),
2974};
2975static const unsigned int msiof2_sync_a_mux[] = {
2976 MSIOF2_SYNC_A_MARK,
2977};
2978static const unsigned int msiof2_ss1_a_pins[] = {
2979 /* SS1 */
2980 RCAR_GP_PIN(1, 6),
2981};
2982static const unsigned int msiof2_ss1_a_mux[] = {
2983 MSIOF2_SS1_A_MARK,
2984};
2985static const unsigned int msiof2_ss2_a_pins[] = {
2986 /* SS2 */
2987 RCAR_GP_PIN(1, 7),
2988};
2989static const unsigned int msiof2_ss2_a_mux[] = {
2990 MSIOF2_SS2_A_MARK,
2991};
2992static const unsigned int msiof2_txd_a_pins[] = {
2993 /* TXD */
2994 RCAR_GP_PIN(1, 11),
2995};
2996static const unsigned int msiof2_txd_a_mux[] = {
2997 MSIOF2_TXD_A_MARK,
2998};
2999static const unsigned int msiof2_rxd_a_pins[] = {
3000 /* RXD */
3001 RCAR_GP_PIN(1, 10),
3002};
3003static const unsigned int msiof2_rxd_a_mux[] = {
3004 MSIOF2_RXD_A_MARK,
3005};
3006static const unsigned int msiof2_clk_b_pins[] = {
3007 /* SCK */
3008 RCAR_GP_PIN(0, 4),
3009};
3010static const unsigned int msiof2_clk_b_mux[] = {
3011 MSIOF2_SCK_B_MARK,
3012};
3013static const unsigned int msiof2_sync_b_pins[] = {
3014 /* SYNC */
3015 RCAR_GP_PIN(0, 5),
3016};
3017static const unsigned int msiof2_sync_b_mux[] = {
3018 MSIOF2_SYNC_B_MARK,
3019};
3020static const unsigned int msiof2_ss1_b_pins[] = {
3021 /* SS1 */
3022 RCAR_GP_PIN(0, 0),
3023};
3024static const unsigned int msiof2_ss1_b_mux[] = {
3025 MSIOF2_SS1_B_MARK,
3026};
3027static const unsigned int msiof2_ss2_b_pins[] = {
3028 /* SS2 */
3029 RCAR_GP_PIN(0, 1),
3030};
3031static const unsigned int msiof2_ss2_b_mux[] = {
3032 MSIOF2_SS2_B_MARK,
3033};
3034static const unsigned int msiof2_txd_b_pins[] = {
3035 /* TXD */
3036 RCAR_GP_PIN(0, 7),
3037};
3038static const unsigned int msiof2_txd_b_mux[] = {
3039 MSIOF2_TXD_B_MARK,
3040};
3041static const unsigned int msiof2_rxd_b_pins[] = {
3042 /* RXD */
3043 RCAR_GP_PIN(0, 6),
3044};
3045static const unsigned int msiof2_rxd_b_mux[] = {
3046 MSIOF2_RXD_B_MARK,
3047};
3048static const unsigned int msiof2_clk_c_pins[] = {
3049 /* SCK */
3050 RCAR_GP_PIN(2, 12),
3051};
3052static const unsigned int msiof2_clk_c_mux[] = {
3053 MSIOF2_SCK_C_MARK,
3054};
3055static const unsigned int msiof2_sync_c_pins[] = {
3056 /* SYNC */
3057 RCAR_GP_PIN(2, 11),
3058};
3059static const unsigned int msiof2_sync_c_mux[] = {
3060 MSIOF2_SYNC_C_MARK,
3061};
3062static const unsigned int msiof2_ss1_c_pins[] = {
3063 /* SS1 */
3064 RCAR_GP_PIN(2, 10),
3065};
3066static const unsigned int msiof2_ss1_c_mux[] = {
3067 MSIOF2_SS1_C_MARK,
3068};
3069static const unsigned int msiof2_ss2_c_pins[] = {
3070 /* SS2 */
3071 RCAR_GP_PIN(2, 9),
3072};
3073static const unsigned int msiof2_ss2_c_mux[] = {
3074 MSIOF2_SS2_C_MARK,
3075};
3076static const unsigned int msiof2_txd_c_pins[] = {
3077 /* TXD */
3078 RCAR_GP_PIN(2, 14),
3079};
3080static const unsigned int msiof2_txd_c_mux[] = {
3081 MSIOF2_TXD_C_MARK,
3082};
3083static const unsigned int msiof2_rxd_c_pins[] = {
3084 /* RXD */
3085 RCAR_GP_PIN(2, 13),
3086};
3087static const unsigned int msiof2_rxd_c_mux[] = {
3088 MSIOF2_RXD_C_MARK,
3089};
3090static const unsigned int msiof2_clk_d_pins[] = {
3091 /* SCK */
3092 RCAR_GP_PIN(0, 8),
3093};
3094static const unsigned int msiof2_clk_d_mux[] = {
3095 MSIOF2_SCK_D_MARK,
3096};
3097static const unsigned int msiof2_sync_d_pins[] = {
3098 /* SYNC */
3099 RCAR_GP_PIN(0, 9),
3100};
3101static const unsigned int msiof2_sync_d_mux[] = {
3102 MSIOF2_SYNC_D_MARK,
3103};
3104static const unsigned int msiof2_ss1_d_pins[] = {
3105 /* SS1 */
3106 RCAR_GP_PIN(0, 12),
3107};
3108static const unsigned int msiof2_ss1_d_mux[] = {
3109 MSIOF2_SS1_D_MARK,
3110};
3111static const unsigned int msiof2_ss2_d_pins[] = {
3112 /* SS2 */
3113 RCAR_GP_PIN(0, 13),
3114};
3115static const unsigned int msiof2_ss2_d_mux[] = {
3116 MSIOF2_SS2_D_MARK,
3117};
3118static const unsigned int msiof2_txd_d_pins[] = {
3119 /* TXD */
3120 RCAR_GP_PIN(0, 11),
3121};
3122static const unsigned int msiof2_txd_d_mux[] = {
3123 MSIOF2_TXD_D_MARK,
3124};
3125static const unsigned int msiof2_rxd_d_pins[] = {
3126 /* RXD */
3127 RCAR_GP_PIN(0, 10),
3128};
3129static const unsigned int msiof2_rxd_d_mux[] = {
3130 MSIOF2_RXD_D_MARK,
3131};
3132/* - MSIOF3 ----------------------------------------------------------------- */
3133static const unsigned int msiof3_clk_a_pins[] = {
3134 /* SCK */
3135 RCAR_GP_PIN(0, 0),
3136};
3137static const unsigned int msiof3_clk_a_mux[] = {
3138 MSIOF3_SCK_A_MARK,
3139};
3140static const unsigned int msiof3_sync_a_pins[] = {
3141 /* SYNC */
3142 RCAR_GP_PIN(0, 1),
3143};
3144static const unsigned int msiof3_sync_a_mux[] = {
3145 MSIOF3_SYNC_A_MARK,
3146};
3147static const unsigned int msiof3_ss1_a_pins[] = {
3148 /* SS1 */
3149 RCAR_GP_PIN(0, 14),
3150};
3151static const unsigned int msiof3_ss1_a_mux[] = {
3152 MSIOF3_SS1_A_MARK,
3153};
3154static const unsigned int msiof3_ss2_a_pins[] = {
3155 /* SS2 */
3156 RCAR_GP_PIN(0, 15),
3157};
3158static const unsigned int msiof3_ss2_a_mux[] = {
3159 MSIOF3_SS2_A_MARK,
3160};
3161static const unsigned int msiof3_txd_a_pins[] = {
3162 /* TXD */
3163 RCAR_GP_PIN(0, 3),
3164};
3165static const unsigned int msiof3_txd_a_mux[] = {
3166 MSIOF3_TXD_A_MARK,
3167};
3168static const unsigned int msiof3_rxd_a_pins[] = {
3169 /* RXD */
3170 RCAR_GP_PIN(0, 2),
3171};
3172static const unsigned int msiof3_rxd_a_mux[] = {
3173 MSIOF3_RXD_A_MARK,
3174};
3175static const unsigned int msiof3_clk_b_pins[] = {
3176 /* SCK */
3177 RCAR_GP_PIN(1, 2),
3178};
3179static const unsigned int msiof3_clk_b_mux[] = {
3180 MSIOF3_SCK_B_MARK,
3181};
3182static const unsigned int msiof3_sync_b_pins[] = {
3183 /* SYNC */
3184 RCAR_GP_PIN(1, 0),
3185};
3186static const unsigned int msiof3_sync_b_mux[] = {
3187 MSIOF3_SYNC_B_MARK,
3188};
3189static const unsigned int msiof3_ss1_b_pins[] = {
3190 /* SS1 */
3191 RCAR_GP_PIN(1, 4),
3192};
3193static const unsigned int msiof3_ss1_b_mux[] = {
3194 MSIOF3_SS1_B_MARK,
3195};
3196static const unsigned int msiof3_ss2_b_pins[] = {
3197 /* SS2 */
3198 RCAR_GP_PIN(1, 5),
3199};
3200static const unsigned int msiof3_ss2_b_mux[] = {
3201 MSIOF3_SS2_B_MARK,
3202};
3203static const unsigned int msiof3_txd_b_pins[] = {
3204 /* TXD */
3205 RCAR_GP_PIN(1, 1),
3206};
3207static const unsigned int msiof3_txd_b_mux[] = {
3208 MSIOF3_TXD_B_MARK,
3209};
3210static const unsigned int msiof3_rxd_b_pins[] = {
3211 /* RXD */
3212 RCAR_GP_PIN(1, 3),
3213};
3214static const unsigned int msiof3_rxd_b_mux[] = {
3215 MSIOF3_RXD_B_MARK,
3216};
3217static const unsigned int msiof3_clk_c_pins[] = {
3218 /* SCK */
3219 RCAR_GP_PIN(1, 12),
3220};
3221static const unsigned int msiof3_clk_c_mux[] = {
3222 MSIOF3_SCK_C_MARK,
3223};
3224static const unsigned int msiof3_sync_c_pins[] = {
3225 /* SYNC */
3226 RCAR_GP_PIN(1, 13),
3227};
3228static const unsigned int msiof3_sync_c_mux[] = {
3229 MSIOF3_SYNC_C_MARK,
3230};
3231static const unsigned int msiof3_txd_c_pins[] = {
3232 /* TXD */
3233 RCAR_GP_PIN(1, 15),
3234};
3235static const unsigned int msiof3_txd_c_mux[] = {
3236 MSIOF3_TXD_C_MARK,
3237};
3238static const unsigned int msiof3_rxd_c_pins[] = {
3239 /* RXD */
3240 RCAR_GP_PIN(1, 14),
3241};
3242static const unsigned int msiof3_rxd_c_mux[] = {
3243 MSIOF3_RXD_C_MARK,
3244};
3245static const unsigned int msiof3_clk_d_pins[] = {
3246 /* SCK */
3247 RCAR_GP_PIN(1, 22),
3248};
3249static const unsigned int msiof3_clk_d_mux[] = {
3250 MSIOF3_SCK_D_MARK,
3251};
3252static const unsigned int msiof3_sync_d_pins[] = {
3253 /* SYNC */
3254 RCAR_GP_PIN(1, 23),
3255};
3256static const unsigned int msiof3_sync_d_mux[] = {
3257 MSIOF3_SYNC_D_MARK,
3258};
3259static const unsigned int msiof3_ss1_d_pins[] = {
3260 /* SS1 */
3261 RCAR_GP_PIN(1, 26),
3262};
3263static const unsigned int msiof3_ss1_d_mux[] = {
3264 MSIOF3_SS1_D_MARK,
3265};
3266static const unsigned int msiof3_txd_d_pins[] = {
3267 /* TXD */
3268 RCAR_GP_PIN(1, 25),
3269};
3270static const unsigned int msiof3_txd_d_mux[] = {
3271 MSIOF3_TXD_D_MARK,
3272};
3273static const unsigned int msiof3_rxd_d_pins[] = {
3274 /* RXD */
3275 RCAR_GP_PIN(1, 24),
3276};
3277static const unsigned int msiof3_rxd_d_mux[] = {
3278 MSIOF3_RXD_D_MARK,
3279};
3280static const unsigned int msiof3_clk_e_pins[] = {
3281 /* SCK */
3282 RCAR_GP_PIN(2, 3),
3283};
3284static const unsigned int msiof3_clk_e_mux[] = {
3285 MSIOF3_SCK_E_MARK,
3286};
3287static const unsigned int msiof3_sync_e_pins[] = {
3288 /* SYNC */
3289 RCAR_GP_PIN(2, 2),
3290};
3291static const unsigned int msiof3_sync_e_mux[] = {
3292 MSIOF3_SYNC_E_MARK,
3293};
3294static const unsigned int msiof3_ss1_e_pins[] = {
3295 /* SS1 */
3296 RCAR_GP_PIN(2, 1),
3297};
3298static const unsigned int msiof3_ss1_e_mux[] = {
3299 MSIOF3_SS1_E_MARK,
3300};
3301static const unsigned int msiof3_ss2_e_pins[] = {
3302 /* SS2 */
3303 RCAR_GP_PIN(2, 0),
3304};
3305static const unsigned int msiof3_ss2_e_mux[] = {
3306 MSIOF3_SS2_E_MARK,
3307};
3308static const unsigned int msiof3_txd_e_pins[] = {
3309 /* TXD */
3310 RCAR_GP_PIN(2, 5),
3311};
3312static const unsigned int msiof3_txd_e_mux[] = {
3313 MSIOF3_TXD_E_MARK,
3314};
3315static const unsigned int msiof3_rxd_e_pins[] = {
3316 /* RXD */
3317 RCAR_GP_PIN(2, 4),
3318};
3319static const unsigned int msiof3_rxd_e_mux[] = {
3320 MSIOF3_RXD_E_MARK,
3321};
3322
3323/* - PWM0 --------------------------------------------------------------------*/
3324static const unsigned int pwm0_pins[] = {
3325 /* PWM */
3326 RCAR_GP_PIN(2, 6),
3327};
3328static const unsigned int pwm0_mux[] = {
3329 PWM0_MARK,
3330};
3331/* - PWM1 --------------------------------------------------------------------*/
3332static const unsigned int pwm1_a_pins[] = {
3333 /* PWM */
3334 RCAR_GP_PIN(2, 7),
3335};
3336static const unsigned int pwm1_a_mux[] = {
3337 PWM1_A_MARK,
3338};
3339static const unsigned int pwm1_b_pins[] = {
3340 /* PWM */
3341 RCAR_GP_PIN(1, 8),
3342};
3343static const unsigned int pwm1_b_mux[] = {
3344 PWM1_B_MARK,
3345};
3346/* - PWM2 --------------------------------------------------------------------*/
3347static const unsigned int pwm2_a_pins[] = {
3348 /* PWM */
3349 RCAR_GP_PIN(2, 8),
3350};
3351static const unsigned int pwm2_a_mux[] = {
3352 PWM2_A_MARK,
3353};
3354static const unsigned int pwm2_b_pins[] = {
3355 /* PWM */
3356 RCAR_GP_PIN(1, 11),
3357};
3358static const unsigned int pwm2_b_mux[] = {
3359 PWM2_B_MARK,
3360};
3361/* - PWM3 --------------------------------------------------------------------*/
3362static const unsigned int pwm3_a_pins[] = {
3363 /* PWM */
3364 RCAR_GP_PIN(1, 0),
3365};
3366static const unsigned int pwm3_a_mux[] = {
3367 PWM3_A_MARK,
3368};
3369static const unsigned int pwm3_b_pins[] = {
3370 /* PWM */
3371 RCAR_GP_PIN(2, 2),
3372};
3373static const unsigned int pwm3_b_mux[] = {
3374 PWM3_B_MARK,
3375};
3376/* - PWM4 --------------------------------------------------------------------*/
3377static const unsigned int pwm4_a_pins[] = {
3378 /* PWM */
3379 RCAR_GP_PIN(1, 1),
3380};
3381static const unsigned int pwm4_a_mux[] = {
3382 PWM4_A_MARK,
3383};
3384static const unsigned int pwm4_b_pins[] = {
3385 /* PWM */
3386 RCAR_GP_PIN(2, 3),
3387};
3388static const unsigned int pwm4_b_mux[] = {
3389 PWM4_B_MARK,
3390};
3391/* - PWM5 --------------------------------------------------------------------*/
3392static const unsigned int pwm5_a_pins[] = {
3393 /* PWM */
3394 RCAR_GP_PIN(1, 2),
3395};
3396static const unsigned int pwm5_a_mux[] = {
3397 PWM5_A_MARK,
3398};
3399static const unsigned int pwm5_b_pins[] = {
3400 /* PWM */
3401 RCAR_GP_PIN(2, 4),
3402};
3403static const unsigned int pwm5_b_mux[] = {
3404 PWM5_B_MARK,
3405};
3406/* - PWM6 --------------------------------------------------------------------*/
3407static const unsigned int pwm6_a_pins[] = {
3408 /* PWM */
3409 RCAR_GP_PIN(1, 3),
3410};
3411static const unsigned int pwm6_a_mux[] = {
3412 PWM6_A_MARK,
3413};
3414static const unsigned int pwm6_b_pins[] = {
3415 /* PWM */
3416 RCAR_GP_PIN(2, 5),
3417};
3418static const unsigned int pwm6_b_mux[] = {
3419 PWM6_B_MARK,
3420};
3421
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3422/* - QSPI0 ------------------------------------------------------------------ */
3423static const unsigned int qspi0_ctrl_pins[] = {
3424 /* QSPI0_SPCLK, QSPI0_SSL */
3425 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3426};
3427static const unsigned int qspi0_ctrl_mux[] = {
3428 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3429};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3430static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3431 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3432 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3433 /* QSPI0_IO2, QSPI0_IO3 */
3434 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3435};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3436static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3437 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3438 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3439};
3440/* - QSPI1 ------------------------------------------------------------------ */
3441static const unsigned int qspi1_ctrl_pins[] = {
3442 /* QSPI1_SPCLK, QSPI1_SSL */
3443 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3444};
3445static const unsigned int qspi1_ctrl_mux[] = {
3446 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3447};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3448static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3449 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3450 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3451 /* QSPI1_IO2, QSPI1_IO3 */
3452 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3453};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3454static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3455 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3456 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3457};
3458
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3459/* - SATA --------------------------------------------------------------------*/
3460static const unsigned int sata0_devslp_a_pins[] = {
3461 /* DEVSLP */
3462 RCAR_GP_PIN(6, 16),
3463};
3464
3465static const unsigned int sata0_devslp_a_mux[] = {
3466 SATA_DEVSLP_A_MARK,
3467};
3468
3469static const unsigned int sata0_devslp_b_pins[] = {
3470 /* DEVSLP */
3471 RCAR_GP_PIN(4, 6),
3472};
3473
3474static const unsigned int sata0_devslp_b_mux[] = {
3475 SATA_DEVSLP_B_MARK,
3476};
3477
3478/* - SCIF0 ------------------------------------------------------------------ */
3479static const unsigned int scif0_data_pins[] = {
3480 /* RX, TX */
3481 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3482};
3483static const unsigned int scif0_data_mux[] = {
3484 RX0_MARK, TX0_MARK,
3485};
3486static const unsigned int scif0_clk_pins[] = {
3487 /* SCK */
3488 RCAR_GP_PIN(5, 0),
3489};
3490static const unsigned int scif0_clk_mux[] = {
3491 SCK0_MARK,
3492};
3493static const unsigned int scif0_ctrl_pins[] = {
3494 /* RTS, CTS */
3495 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3496};
3497static const unsigned int scif0_ctrl_mux[] = {
3498 RTS0_N_MARK, CTS0_N_MARK,
3499};
3500/* - SCIF1 ------------------------------------------------------------------ */
3501static const unsigned int scif1_data_a_pins[] = {
3502 /* RX, TX */
3503 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3504};
3505static const unsigned int scif1_data_a_mux[] = {
3506 RX1_A_MARK, TX1_A_MARK,
3507};
3508static const unsigned int scif1_clk_pins[] = {
3509 /* SCK */
3510 RCAR_GP_PIN(6, 21),
3511};
3512static const unsigned int scif1_clk_mux[] = {
3513 SCK1_MARK,
3514};
3515static const unsigned int scif1_ctrl_pins[] = {
3516 /* RTS, CTS */
3517 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3518};
3519static const unsigned int scif1_ctrl_mux[] = {
3520 RTS1_N_MARK, CTS1_N_MARK,
3521};
3522static const unsigned int scif1_data_b_pins[] = {
3523 /* RX, TX */
3524 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3525};
3526static const unsigned int scif1_data_b_mux[] = {
3527 RX1_B_MARK, TX1_B_MARK,
3528};
3529/* - SCIF2 ------------------------------------------------------------------ */
3530static const unsigned int scif2_data_a_pins[] = {
3531 /* RX, TX */
3532 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3533};
3534static const unsigned int scif2_data_a_mux[] = {
3535 RX2_A_MARK, TX2_A_MARK,
3536};
3537static const unsigned int scif2_clk_pins[] = {
3538 /* SCK */
3539 RCAR_GP_PIN(5, 9),
3540};
3541static const unsigned int scif2_clk_mux[] = {
3542 SCK2_MARK,
3543};
3544static const unsigned int scif2_data_b_pins[] = {
3545 /* RX, TX */
3546 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3547};
3548static const unsigned int scif2_data_b_mux[] = {
3549 RX2_B_MARK, TX2_B_MARK,
3550};
3551/* - SCIF3 ------------------------------------------------------------------ */
3552static const unsigned int scif3_data_a_pins[] = {
3553 /* RX, TX */
3554 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3555};
3556static const unsigned int scif3_data_a_mux[] = {
3557 RX3_A_MARK, TX3_A_MARK,
3558};
3559static const unsigned int scif3_clk_pins[] = {
3560 /* SCK */
3561 RCAR_GP_PIN(1, 22),
3562};
3563static const unsigned int scif3_clk_mux[] = {
3564 SCK3_MARK,
3565};
3566static const unsigned int scif3_ctrl_pins[] = {
3567 /* RTS, CTS */
3568 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3569};
3570static const unsigned int scif3_ctrl_mux[] = {
3571 RTS3_N_MARK, CTS3_N_MARK,
3572};
3573static const unsigned int scif3_data_b_pins[] = {
3574 /* RX, TX */
3575 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3576};
3577static const unsigned int scif3_data_b_mux[] = {
3578 RX3_B_MARK, TX3_B_MARK,
3579};
3580/* - SCIF4 ------------------------------------------------------------------ */
3581static const unsigned int scif4_data_a_pins[] = {
3582 /* RX, TX */
3583 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3584};
3585static const unsigned int scif4_data_a_mux[] = {
3586 RX4_A_MARK, TX4_A_MARK,
3587};
3588static const unsigned int scif4_clk_a_pins[] = {
3589 /* SCK */
3590 RCAR_GP_PIN(2, 10),
3591};
3592static const unsigned int scif4_clk_a_mux[] = {
3593 SCK4_A_MARK,
3594};
3595static const unsigned int scif4_ctrl_a_pins[] = {
3596 /* RTS, CTS */
3597 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3598};
3599static const unsigned int scif4_ctrl_a_mux[] = {
3600 RTS4_N_A_MARK, CTS4_N_A_MARK,
3601};
3602static const unsigned int scif4_data_b_pins[] = {
3603 /* RX, TX */
3604 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3605};
3606static const unsigned int scif4_data_b_mux[] = {
3607 RX4_B_MARK, TX4_B_MARK,
3608};
3609static const unsigned int scif4_clk_b_pins[] = {
3610 /* SCK */
3611 RCAR_GP_PIN(1, 5),
3612};
3613static const unsigned int scif4_clk_b_mux[] = {
3614 SCK4_B_MARK,
3615};
3616static const unsigned int scif4_ctrl_b_pins[] = {
3617 /* RTS, CTS */
3618 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3619};
3620static const unsigned int scif4_ctrl_b_mux[] = {
3621 RTS4_N_B_MARK, CTS4_N_B_MARK,
3622};
3623static const unsigned int scif4_data_c_pins[] = {
3624 /* RX, TX */
3625 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3626};
3627static const unsigned int scif4_data_c_mux[] = {
3628 RX4_C_MARK, TX4_C_MARK,
3629};
3630static const unsigned int scif4_clk_c_pins[] = {
3631 /* SCK */
3632 RCAR_GP_PIN(0, 8),
3633};
3634static const unsigned int scif4_clk_c_mux[] = {
3635 SCK4_C_MARK,
3636};
3637static const unsigned int scif4_ctrl_c_pins[] = {
3638 /* RTS, CTS */
3639 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3640};
3641static const unsigned int scif4_ctrl_c_mux[] = {
3642 RTS4_N_C_MARK, CTS4_N_C_MARK,
3643};
3644/* - SCIF5 ------------------------------------------------------------------ */
3645static const unsigned int scif5_data_a_pins[] = {
3646 /* RX, TX */
3647 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3648};
3649static const unsigned int scif5_data_a_mux[] = {
3650 RX5_A_MARK, TX5_A_MARK,
3651};
3652static const unsigned int scif5_clk_a_pins[] = {
3653 /* SCK */
3654 RCAR_GP_PIN(6, 21),
3655};
3656static const unsigned int scif5_clk_a_mux[] = {
3657 SCK5_A_MARK,
3658};
3659static const unsigned int scif5_data_b_pins[] = {
3660 /* RX, TX */
3661 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3662};
3663static const unsigned int scif5_data_b_mux[] = {
3664 RX5_B_MARK, TX5_B_MARK,
3665};
3666static const unsigned int scif5_clk_b_pins[] = {
3667 /* SCK */
3668 RCAR_GP_PIN(5, 0),
3669};
3670static const unsigned int scif5_clk_b_mux[] = {
3671 SCK5_B_MARK,
3672};
3673/* - SCIF Clock ------------------------------------------------------------- */
3674static const unsigned int scif_clk_a_pins[] = {
3675 /* SCIF_CLK */
3676 RCAR_GP_PIN(6, 23),
3677};
3678static const unsigned int scif_clk_a_mux[] = {
3679 SCIF_CLK_A_MARK,
3680};
3681static const unsigned int scif_clk_b_pins[] = {
3682 /* SCIF_CLK */
3683 RCAR_GP_PIN(5, 9),
3684};
3685static const unsigned int scif_clk_b_mux[] = {
3686 SCIF_CLK_B_MARK,
3687};
3688
3689/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3690static const unsigned int sdhi0_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3691 /* D[0:3] */
3692 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3693 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3694};
3695
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3696static const unsigned int sdhi0_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3697 SD0_DAT0_MARK, SD0_DAT1_MARK,
3698 SD0_DAT2_MARK, SD0_DAT3_MARK,
3699};
3700
3701static const unsigned int sdhi0_ctrl_pins[] = {
3702 /* CLK, CMD */
3703 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3704};
3705
3706static const unsigned int sdhi0_ctrl_mux[] = {
3707 SD0_CLK_MARK, SD0_CMD_MARK,
3708};
3709
3710static const unsigned int sdhi0_cd_pins[] = {
3711 /* CD */
3712 RCAR_GP_PIN(3, 12),
3713};
3714
3715static const unsigned int sdhi0_cd_mux[] = {
3716 SD0_CD_MARK,
3717};
3718
3719static const unsigned int sdhi0_wp_pins[] = {
3720 /* WP */
3721 RCAR_GP_PIN(3, 13),
3722};
3723
3724static const unsigned int sdhi0_wp_mux[] = {
3725 SD0_WP_MARK,
3726};
3727
3728/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3729static const unsigned int sdhi1_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3730 /* D[0:3] */
3731 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3732 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3733};
3734
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3735static const unsigned int sdhi1_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3736 SD1_DAT0_MARK, SD1_DAT1_MARK,
3737 SD1_DAT2_MARK, SD1_DAT3_MARK,
3738};
3739
3740static const unsigned int sdhi1_ctrl_pins[] = {
3741 /* CLK, CMD */
3742 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3743};
3744
3745static const unsigned int sdhi1_ctrl_mux[] = {
3746 SD1_CLK_MARK, SD1_CMD_MARK,
3747};
3748
3749static const unsigned int sdhi1_cd_pins[] = {
3750 /* CD */
3751 RCAR_GP_PIN(3, 14),
3752};
3753
3754static const unsigned int sdhi1_cd_mux[] = {
3755 SD1_CD_MARK,
3756};
3757
3758static const unsigned int sdhi1_wp_pins[] = {
3759 /* WP */
3760 RCAR_GP_PIN(3, 15),
3761};
3762
3763static const unsigned int sdhi1_wp_mux[] = {
3764 SD1_WP_MARK,
3765};
3766
3767/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3768static const unsigned int sdhi2_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3769 /* D[0:7] */
3770 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3771 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3772 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3773 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3774};
3775
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3776static const unsigned int sdhi2_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3777 SD2_DAT0_MARK, SD2_DAT1_MARK,
3778 SD2_DAT2_MARK, SD2_DAT3_MARK,
3779 SD2_DAT4_MARK, SD2_DAT5_MARK,
3780 SD2_DAT6_MARK, SD2_DAT7_MARK,
3781};
3782
3783static const unsigned int sdhi2_ctrl_pins[] = {
3784 /* CLK, CMD */
3785 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3786};
3787
3788static const unsigned int sdhi2_ctrl_mux[] = {
3789 SD2_CLK_MARK, SD2_CMD_MARK,
3790};
3791
3792static const unsigned int sdhi2_cd_a_pins[] = {
3793 /* CD */
3794 RCAR_GP_PIN(4, 13),
3795};
3796
3797static const unsigned int sdhi2_cd_a_mux[] = {
3798 SD2_CD_A_MARK,
3799};
3800
3801static const unsigned int sdhi2_cd_b_pins[] = {
3802 /* CD */
3803 RCAR_GP_PIN(5, 10),
3804};
3805
3806static const unsigned int sdhi2_cd_b_mux[] = {
3807 SD2_CD_B_MARK,
3808};
3809
3810static const unsigned int sdhi2_wp_a_pins[] = {
3811 /* WP */
3812 RCAR_GP_PIN(4, 14),
3813};
3814
3815static const unsigned int sdhi2_wp_a_mux[] = {
3816 SD2_WP_A_MARK,
3817};
3818
3819static const unsigned int sdhi2_wp_b_pins[] = {
3820 /* WP */
3821 RCAR_GP_PIN(5, 11),
3822};
3823
3824static const unsigned int sdhi2_wp_b_mux[] = {
3825 SD2_WP_B_MARK,
3826};
3827
3828static const unsigned int sdhi2_ds_pins[] = {
3829 /* DS */
3830 RCAR_GP_PIN(4, 6),
3831};
3832
3833static const unsigned int sdhi2_ds_mux[] = {
3834 SD2_DS_MARK,
3835};
3836
3837/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3838static const unsigned int sdhi3_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3839 /* D[0:7] */
3840 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3841 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3842 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3843 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3844};
3845
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3846static const unsigned int sdhi3_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3847 SD3_DAT0_MARK, SD3_DAT1_MARK,
3848 SD3_DAT2_MARK, SD3_DAT3_MARK,
3849 SD3_DAT4_MARK, SD3_DAT5_MARK,
3850 SD3_DAT6_MARK, SD3_DAT7_MARK,
3851};
3852
3853static const unsigned int sdhi3_ctrl_pins[] = {
3854 /* CLK, CMD */
3855 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3856};
3857
3858static const unsigned int sdhi3_ctrl_mux[] = {
3859 SD3_CLK_MARK, SD3_CMD_MARK,
3860};
3861
3862static const unsigned int sdhi3_cd_pins[] = {
3863 /* CD */
3864 RCAR_GP_PIN(4, 15),
3865};
3866
3867static const unsigned int sdhi3_cd_mux[] = {
3868 SD3_CD_MARK,
3869};
3870
3871static const unsigned int sdhi3_wp_pins[] = {
3872 /* WP */
3873 RCAR_GP_PIN(4, 16),
3874};
3875
3876static const unsigned int sdhi3_wp_mux[] = {
3877 SD3_WP_MARK,
3878};
3879
3880static const unsigned int sdhi3_ds_pins[] = {
3881 /* DS */
3882 RCAR_GP_PIN(4, 17),
3883};
3884
3885static const unsigned int sdhi3_ds_mux[] = {
3886 SD3_DS_MARK,
3887};
3888
3889/* - SSI -------------------------------------------------------------------- */
3890static const unsigned int ssi0_data_pins[] = {
3891 /* SDATA */
3892 RCAR_GP_PIN(6, 2),
3893};
3894static const unsigned int ssi0_data_mux[] = {
3895 SSI_SDATA0_MARK,
3896};
3897static const unsigned int ssi01239_ctrl_pins[] = {
3898 /* SCK, WS */
3899 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3900};
3901static const unsigned int ssi01239_ctrl_mux[] = {
3902 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3903};
3904static const unsigned int ssi1_data_a_pins[] = {
3905 /* SDATA */
3906 RCAR_GP_PIN(6, 3),
3907};
3908static const unsigned int ssi1_data_a_mux[] = {
3909 SSI_SDATA1_A_MARK,
3910};
3911static const unsigned int ssi1_data_b_pins[] = {
3912 /* SDATA */
3913 RCAR_GP_PIN(5, 12),
3914};
3915static const unsigned int ssi1_data_b_mux[] = {
3916 SSI_SDATA1_B_MARK,
3917};
3918static const unsigned int ssi1_ctrl_a_pins[] = {
3919 /* SCK, WS */
3920 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3921};
3922static const unsigned int ssi1_ctrl_a_mux[] = {
3923 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3924};
3925static const unsigned int ssi1_ctrl_b_pins[] = {
3926 /* SCK, WS */
3927 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3928};
3929static const unsigned int ssi1_ctrl_b_mux[] = {
3930 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3931};
3932static const unsigned int ssi2_data_a_pins[] = {
3933 /* SDATA */
3934 RCAR_GP_PIN(6, 4),
3935};
3936static const unsigned int ssi2_data_a_mux[] = {
3937 SSI_SDATA2_A_MARK,
3938};
3939static const unsigned int ssi2_data_b_pins[] = {
3940 /* SDATA */
3941 RCAR_GP_PIN(5, 13),
3942};
3943static const unsigned int ssi2_data_b_mux[] = {
3944 SSI_SDATA2_B_MARK,
3945};
3946static const unsigned int ssi2_ctrl_a_pins[] = {
3947 /* SCK, WS */
3948 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3949};
3950static const unsigned int ssi2_ctrl_a_mux[] = {
3951 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3952};
3953static const unsigned int ssi2_ctrl_b_pins[] = {
3954 /* SCK, WS */
3955 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3956};
3957static const unsigned int ssi2_ctrl_b_mux[] = {
3958 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3959};
3960static const unsigned int ssi3_data_pins[] = {
3961 /* SDATA */
3962 RCAR_GP_PIN(6, 7),
3963};
3964static const unsigned int ssi3_data_mux[] = {
3965 SSI_SDATA3_MARK,
3966};
3967static const unsigned int ssi349_ctrl_pins[] = {
3968 /* SCK, WS */
3969 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3970};
3971static const unsigned int ssi349_ctrl_mux[] = {
3972 SSI_SCK349_MARK, SSI_WS349_MARK,
3973};
3974static const unsigned int ssi4_data_pins[] = {
3975 /* SDATA */
3976 RCAR_GP_PIN(6, 10),
3977};
3978static const unsigned int ssi4_data_mux[] = {
3979 SSI_SDATA4_MARK,
3980};
3981static const unsigned int ssi4_ctrl_pins[] = {
3982 /* SCK, WS */
3983 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3984};
3985static const unsigned int ssi4_ctrl_mux[] = {
3986 SSI_SCK4_MARK, SSI_WS4_MARK,
3987};
3988static const unsigned int ssi5_data_pins[] = {
3989 /* SDATA */
3990 RCAR_GP_PIN(6, 13),
3991};
3992static const unsigned int ssi5_data_mux[] = {
3993 SSI_SDATA5_MARK,
3994};
3995static const unsigned int ssi5_ctrl_pins[] = {
3996 /* SCK, WS */
3997 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3998};
3999static const unsigned int ssi5_ctrl_mux[] = {
4000 SSI_SCK5_MARK, SSI_WS5_MARK,
4001};
4002static const unsigned int ssi6_data_pins[] = {
4003 /* SDATA */
4004 RCAR_GP_PIN(6, 16),
4005};
4006static const unsigned int ssi6_data_mux[] = {
4007 SSI_SDATA6_MARK,
4008};
4009static const unsigned int ssi6_ctrl_pins[] = {
4010 /* SCK, WS */
4011 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4012};
4013static const unsigned int ssi6_ctrl_mux[] = {
4014 SSI_SCK6_MARK, SSI_WS6_MARK,
4015};
4016static const unsigned int ssi7_data_pins[] = {
4017 /* SDATA */
4018 RCAR_GP_PIN(6, 19),
4019};
4020static const unsigned int ssi7_data_mux[] = {
4021 SSI_SDATA7_MARK,
4022};
4023static const unsigned int ssi78_ctrl_pins[] = {
4024 /* SCK, WS */
4025 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4026};
4027static const unsigned int ssi78_ctrl_mux[] = {
4028 SSI_SCK78_MARK, SSI_WS78_MARK,
4029};
4030static const unsigned int ssi8_data_pins[] = {
4031 /* SDATA */
4032 RCAR_GP_PIN(6, 20),
4033};
4034static const unsigned int ssi8_data_mux[] = {
4035 SSI_SDATA8_MARK,
4036};
4037static const unsigned int ssi9_data_a_pins[] = {
4038 /* SDATA */
4039 RCAR_GP_PIN(6, 21),
4040};
4041static const unsigned int ssi9_data_a_mux[] = {
4042 SSI_SDATA9_A_MARK,
4043};
4044static const unsigned int ssi9_data_b_pins[] = {
4045 /* SDATA */
4046 RCAR_GP_PIN(5, 14),
4047};
4048static const unsigned int ssi9_data_b_mux[] = {
4049 SSI_SDATA9_B_MARK,
4050};
4051static const unsigned int ssi9_ctrl_a_pins[] = {
4052 /* SCK, WS */
4053 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4054};
4055static const unsigned int ssi9_ctrl_a_mux[] = {
4056 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4057};
4058static const unsigned int ssi9_ctrl_b_pins[] = {
4059 /* SCK, WS */
4060 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4061};
4062static const unsigned int ssi9_ctrl_b_mux[] = {
4063 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4064};
4065
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4066/* - TMU -------------------------------------------------------------------- */
4067static const unsigned int tmu_tclk1_a_pins[] = {
4068 /* TCLK */
4069 RCAR_GP_PIN(6, 23),
4070};
4071
4072static const unsigned int tmu_tclk1_a_mux[] = {
4073 TCLK1_A_MARK,
4074};
4075
4076static const unsigned int tmu_tclk1_b_pins[] = {
4077 /* TCLK */
4078 RCAR_GP_PIN(5, 19),
4079};
4080
4081static const unsigned int tmu_tclk1_b_mux[] = {
4082 TCLK1_B_MARK,
4083};
4084
4085static const unsigned int tmu_tclk2_a_pins[] = {
4086 /* TCLK */
4087 RCAR_GP_PIN(6, 19),
4088};
4089
4090static const unsigned int tmu_tclk2_a_mux[] = {
4091 TCLK2_A_MARK,
4092};
4093
4094static const unsigned int tmu_tclk2_b_pins[] = {
4095 /* TCLK */
4096 RCAR_GP_PIN(6, 28),
4097};
4098
4099static const unsigned int tmu_tclk2_b_mux[] = {
4100 TCLK2_B_MARK,
4101};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4102
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4103/* - TPU ------------------------------------------------------------------- */
4104static const unsigned int tpu_to0_pins[] = {
4105 /* TPU0TO0 */
4106 RCAR_GP_PIN(6, 28),
4107};
4108static const unsigned int tpu_to0_mux[] = {
4109 TPU0TO0_MARK,
4110};
4111static const unsigned int tpu_to1_pins[] = {
4112 /* TPU0TO1 */
4113 RCAR_GP_PIN(6, 29),
4114};
4115static const unsigned int tpu_to1_mux[] = {
4116 TPU0TO1_MARK,
4117};
4118static const unsigned int tpu_to2_pins[] = {
4119 /* TPU0TO2 */
4120 RCAR_GP_PIN(6, 30),
4121};
4122static const unsigned int tpu_to2_mux[] = {
4123 TPU0TO2_MARK,
4124};
4125static const unsigned int tpu_to3_pins[] = {
4126 /* TPU0TO3 */
4127 RCAR_GP_PIN(6, 31),
4128};
4129static const unsigned int tpu_to3_mux[] = {
4130 TPU0TO3_MARK,
4131};
4132
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4133/* - USB0 ------------------------------------------------------------------- */
4134static const unsigned int usb0_pins[] = {
4135 /* PWEN, OVC */
4136 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4137};
4138
4139static const unsigned int usb0_mux[] = {
4140 USB0_PWEN_MARK, USB0_OVC_MARK,
4141};
4142
4143/* - USB1 ------------------------------------------------------------------- */
4144static const unsigned int usb1_pins[] = {
4145 /* PWEN, OVC */
4146 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4147};
4148
4149static const unsigned int usb1_mux[] = {
4150 USB1_PWEN_MARK, USB1_OVC_MARK,
4151};
4152
4153/* - USB30 ------------------------------------------------------------------ */
4154static const unsigned int usb30_pins[] = {
4155 /* PWEN, OVC */
4156 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4157};
4158
4159static const unsigned int usb30_mux[] = {
4160 USB30_PWEN_MARK, USB30_OVC_MARK,
4161};
4162
4163/* - VIN4 ------------------------------------------------------------------- */
4164static const unsigned int vin4_data18_a_pins[] = {
4165 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4166 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4167 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4168 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4169 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4170 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4171 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4172 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4173 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4174};
4175
4176static const unsigned int vin4_data18_a_mux[] = {
4177 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4178 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4179 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4180 VI4_DATA10_MARK, VI4_DATA11_MARK,
4181 VI4_DATA12_MARK, VI4_DATA13_MARK,
4182 VI4_DATA14_MARK, VI4_DATA15_MARK,
4183 VI4_DATA18_MARK, VI4_DATA19_MARK,
4184 VI4_DATA20_MARK, VI4_DATA21_MARK,
4185 VI4_DATA22_MARK, VI4_DATA23_MARK,
4186};
4187
4188static const unsigned int vin4_data_a_pins[] = {
4189 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4190 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4191 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4192 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4193 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4194 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4195 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4196 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4197 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4198 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4199 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4200 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4201};
4202
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4203static const unsigned int vin4_data_a_mux[] = {
4204 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4205 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4206 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4207 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4208 VI4_DATA8_MARK, VI4_DATA9_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4209 VI4_DATA10_MARK, VI4_DATA11_MARK,
4210 VI4_DATA12_MARK, VI4_DATA13_MARK,
4211 VI4_DATA14_MARK, VI4_DATA15_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4212 VI4_DATA16_MARK, VI4_DATA17_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4213 VI4_DATA18_MARK, VI4_DATA19_MARK,
4214 VI4_DATA20_MARK, VI4_DATA21_MARK,
4215 VI4_DATA22_MARK, VI4_DATA23_MARK,
4216};
4217
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4218static const unsigned int vin4_data18_b_pins[] = {
4219 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4220 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4221 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4222 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4223 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4224 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4225 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4226 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4227 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4228};
4229
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4230static const unsigned int vin4_data18_b_mux[] = {
4231 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4232 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4233 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4234 VI4_DATA10_MARK, VI4_DATA11_MARK,
4235 VI4_DATA12_MARK, VI4_DATA13_MARK,
4236 VI4_DATA14_MARK, VI4_DATA15_MARK,
4237 VI4_DATA18_MARK, VI4_DATA19_MARK,
4238 VI4_DATA20_MARK, VI4_DATA21_MARK,
4239 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4240};
4241
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4242static const unsigned int vin4_data_b_pins[] = {
4243 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4244 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4245 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4246 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4247 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4248 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4249 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4250 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4251 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4252 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4253 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4254 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4255};
4256
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4257static const unsigned int vin4_data_b_mux[] = {
4258 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4259 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4260 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4261 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4262 VI4_DATA8_MARK, VI4_DATA9_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4263 VI4_DATA10_MARK, VI4_DATA11_MARK,
4264 VI4_DATA12_MARK, VI4_DATA13_MARK,
4265 VI4_DATA14_MARK, VI4_DATA15_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4266 VI4_DATA16_MARK, VI4_DATA17_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4267 VI4_DATA18_MARK, VI4_DATA19_MARK,
4268 VI4_DATA20_MARK, VI4_DATA21_MARK,
4269 VI4_DATA22_MARK, VI4_DATA23_MARK,
4270};
4271
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4272static const unsigned int vin4_sync_pins[] = {
4273 /* VSYNC_N, HSYNC_N */
4274 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4275};
4276
4277static const unsigned int vin4_sync_mux[] = {
4278 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4279};
4280
4281static const unsigned int vin4_field_pins[] = {
4282 RCAR_GP_PIN(1, 16),
4283};
4284
4285static const unsigned int vin4_field_mux[] = {
4286 VI4_FIELD_MARK,
4287};
4288
4289static const unsigned int vin4_clkenb_pins[] = {
4290 RCAR_GP_PIN(1, 19),
4291};
4292
4293static const unsigned int vin4_clkenb_mux[] = {
4294 VI4_CLKENB_MARK,
4295};
4296
4297static const unsigned int vin4_clk_pins[] = {
4298 RCAR_GP_PIN(1, 27),
4299};
4300
4301static const unsigned int vin4_clk_mux[] = {
4302 VI4_CLK_MARK,
4303};
4304
4305/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4306static const unsigned int vin5_data_pins[] = {
4307 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4308 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4309 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4310 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4311 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4312 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4313 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4314 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4315};
4316
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4317static const unsigned int vin5_data_mux[] = {
4318 VI5_DATA0_MARK, VI5_DATA1_MARK,
4319 VI5_DATA2_MARK, VI5_DATA3_MARK,
4320 VI5_DATA4_MARK, VI5_DATA5_MARK,
4321 VI5_DATA6_MARK, VI5_DATA7_MARK,
4322 VI5_DATA8_MARK, VI5_DATA9_MARK,
4323 VI5_DATA10_MARK, VI5_DATA11_MARK,
4324 VI5_DATA12_MARK, VI5_DATA13_MARK,
4325 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4326};
4327
4328static const unsigned int vin5_sync_pins[] = {
4329 /* VSYNC_N, HSYNC_N */
4330 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4331};
4332
4333static const unsigned int vin5_sync_mux[] = {
4334 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4335};
4336
4337static const unsigned int vin5_field_pins[] = {
4338 RCAR_GP_PIN(1, 11),
4339};
4340
4341static const unsigned int vin5_field_mux[] = {
4342 VI5_FIELD_MARK,
4343};
4344
4345static const unsigned int vin5_clkenb_pins[] = {
4346 RCAR_GP_PIN(1, 20),
4347};
4348
4349static const unsigned int vin5_clkenb_mux[] = {
4350 VI5_CLKENB_MARK,
4351};
4352
4353static const unsigned int vin5_clk_pins[] = {
4354 RCAR_GP_PIN(1, 21),
4355};
4356
4357static const unsigned int vin5_clk_mux[] = {
4358 VI5_CLK_MARK,
4359};
4360
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4361static const struct {
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4362 struct sh_pfc_pin_group common[326];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4363#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4364 struct sh_pfc_pin_group automotive[31];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4365#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4366} pinmux_groups = {
4367 .common = {
4368 SH_PFC_PIN_GROUP(audio_clk_a_a),
4369 SH_PFC_PIN_GROUP(audio_clk_a_b),
4370 SH_PFC_PIN_GROUP(audio_clk_a_c),
4371 SH_PFC_PIN_GROUP(audio_clk_b_a),
4372 SH_PFC_PIN_GROUP(audio_clk_b_b),
4373 SH_PFC_PIN_GROUP(audio_clk_c_a),
4374 SH_PFC_PIN_GROUP(audio_clk_c_b),
4375 SH_PFC_PIN_GROUP(audio_clkout_a),
4376 SH_PFC_PIN_GROUP(audio_clkout_b),
4377 SH_PFC_PIN_GROUP(audio_clkout_c),
4378 SH_PFC_PIN_GROUP(audio_clkout_d),
4379 SH_PFC_PIN_GROUP(audio_clkout1_a),
4380 SH_PFC_PIN_GROUP(audio_clkout1_b),
4381 SH_PFC_PIN_GROUP(audio_clkout2_a),
4382 SH_PFC_PIN_GROUP(audio_clkout2_b),
4383 SH_PFC_PIN_GROUP(audio_clkout3_a),
4384 SH_PFC_PIN_GROUP(audio_clkout3_b),
4385 SH_PFC_PIN_GROUP(avb_link),
4386 SH_PFC_PIN_GROUP(avb_magic),
4387 SH_PFC_PIN_GROUP(avb_phy_int),
4388 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4389 SH_PFC_PIN_GROUP(avb_mdio),
4390 SH_PFC_PIN_GROUP(avb_mii),
4391 SH_PFC_PIN_GROUP(avb_avtp_pps),
4392 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4393 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4394 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4395 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4396 SH_PFC_PIN_GROUP(can0_data_a),
4397 SH_PFC_PIN_GROUP(can0_data_b),
4398 SH_PFC_PIN_GROUP(can1_data),
4399 SH_PFC_PIN_GROUP(can_clk),
4400 SH_PFC_PIN_GROUP(canfd0_data_a),
4401 SH_PFC_PIN_GROUP(canfd0_data_b),
4402 SH_PFC_PIN_GROUP(canfd1_data),
4403 SH_PFC_PIN_GROUP(du_rgb666),
4404 SH_PFC_PIN_GROUP(du_rgb888),
4405 SH_PFC_PIN_GROUP(du_clk_out_0),
4406 SH_PFC_PIN_GROUP(du_clk_out_1),
4407 SH_PFC_PIN_GROUP(du_sync),
4408 SH_PFC_PIN_GROUP(du_oddf),
4409 SH_PFC_PIN_GROUP(du_cde),
4410 SH_PFC_PIN_GROUP(du_disp),
4411 SH_PFC_PIN_GROUP(hscif0_data),
4412 SH_PFC_PIN_GROUP(hscif0_clk),
4413 SH_PFC_PIN_GROUP(hscif0_ctrl),
4414 SH_PFC_PIN_GROUP(hscif1_data_a),
4415 SH_PFC_PIN_GROUP(hscif1_clk_a),
4416 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4417 SH_PFC_PIN_GROUP(hscif1_data_b),
4418 SH_PFC_PIN_GROUP(hscif1_clk_b),
4419 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4420 SH_PFC_PIN_GROUP(hscif2_data_a),
4421 SH_PFC_PIN_GROUP(hscif2_clk_a),
4422 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4423 SH_PFC_PIN_GROUP(hscif2_data_b),
4424 SH_PFC_PIN_GROUP(hscif2_clk_b),
4425 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4426 SH_PFC_PIN_GROUP(hscif2_data_c),
4427 SH_PFC_PIN_GROUP(hscif2_clk_c),
4428 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4429 SH_PFC_PIN_GROUP(hscif3_data_a),
4430 SH_PFC_PIN_GROUP(hscif3_clk),
4431 SH_PFC_PIN_GROUP(hscif3_ctrl),
4432 SH_PFC_PIN_GROUP(hscif3_data_b),
4433 SH_PFC_PIN_GROUP(hscif3_data_c),
4434 SH_PFC_PIN_GROUP(hscif3_data_d),
4435 SH_PFC_PIN_GROUP(hscif4_data_a),
4436 SH_PFC_PIN_GROUP(hscif4_clk),
4437 SH_PFC_PIN_GROUP(hscif4_ctrl),
4438 SH_PFC_PIN_GROUP(hscif4_data_b),
4439 SH_PFC_PIN_GROUP(i2c0),
4440 SH_PFC_PIN_GROUP(i2c1_a),
4441 SH_PFC_PIN_GROUP(i2c1_b),
4442 SH_PFC_PIN_GROUP(i2c2_a),
4443 SH_PFC_PIN_GROUP(i2c2_b),
4444 SH_PFC_PIN_GROUP(i2c3),
4445 SH_PFC_PIN_GROUP(i2c5),
4446 SH_PFC_PIN_GROUP(i2c6_a),
4447 SH_PFC_PIN_GROUP(i2c6_b),
4448 SH_PFC_PIN_GROUP(i2c6_c),
4449 SH_PFC_PIN_GROUP(intc_ex_irq0),
4450 SH_PFC_PIN_GROUP(intc_ex_irq1),
4451 SH_PFC_PIN_GROUP(intc_ex_irq2),
4452 SH_PFC_PIN_GROUP(intc_ex_irq3),
4453 SH_PFC_PIN_GROUP(intc_ex_irq4),
4454 SH_PFC_PIN_GROUP(intc_ex_irq5),
4455 SH_PFC_PIN_GROUP(msiof0_clk),
4456 SH_PFC_PIN_GROUP(msiof0_sync),
4457 SH_PFC_PIN_GROUP(msiof0_ss1),
4458 SH_PFC_PIN_GROUP(msiof0_ss2),
4459 SH_PFC_PIN_GROUP(msiof0_txd),
4460 SH_PFC_PIN_GROUP(msiof0_rxd),
4461 SH_PFC_PIN_GROUP(msiof1_clk_a),
4462 SH_PFC_PIN_GROUP(msiof1_sync_a),
4463 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4464 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4465 SH_PFC_PIN_GROUP(msiof1_txd_a),
4466 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4467 SH_PFC_PIN_GROUP(msiof1_clk_b),
4468 SH_PFC_PIN_GROUP(msiof1_sync_b),
4469 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4470 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4471 SH_PFC_PIN_GROUP(msiof1_txd_b),
4472 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4473 SH_PFC_PIN_GROUP(msiof1_clk_c),
4474 SH_PFC_PIN_GROUP(msiof1_sync_c),
4475 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4476 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4477 SH_PFC_PIN_GROUP(msiof1_txd_c),
4478 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4479 SH_PFC_PIN_GROUP(msiof1_clk_d),
4480 SH_PFC_PIN_GROUP(msiof1_sync_d),
4481 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4482 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4483 SH_PFC_PIN_GROUP(msiof1_txd_d),
4484 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4485 SH_PFC_PIN_GROUP(msiof1_clk_e),
4486 SH_PFC_PIN_GROUP(msiof1_sync_e),
4487 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4488 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4489 SH_PFC_PIN_GROUP(msiof1_txd_e),
4490 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4491 SH_PFC_PIN_GROUP(msiof1_clk_f),
4492 SH_PFC_PIN_GROUP(msiof1_sync_f),
4493 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4494 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4495 SH_PFC_PIN_GROUP(msiof1_txd_f),
4496 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4497 SH_PFC_PIN_GROUP(msiof1_clk_g),
4498 SH_PFC_PIN_GROUP(msiof1_sync_g),
4499 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4500 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4501 SH_PFC_PIN_GROUP(msiof1_txd_g),
4502 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4503 SH_PFC_PIN_GROUP(msiof2_clk_a),
4504 SH_PFC_PIN_GROUP(msiof2_sync_a),
4505 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4506 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4507 SH_PFC_PIN_GROUP(msiof2_txd_a),
4508 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4509 SH_PFC_PIN_GROUP(msiof2_clk_b),
4510 SH_PFC_PIN_GROUP(msiof2_sync_b),
4511 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4512 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4513 SH_PFC_PIN_GROUP(msiof2_txd_b),
4514 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4515 SH_PFC_PIN_GROUP(msiof2_clk_c),
4516 SH_PFC_PIN_GROUP(msiof2_sync_c),
4517 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4518 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4519 SH_PFC_PIN_GROUP(msiof2_txd_c),
4520 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4521 SH_PFC_PIN_GROUP(msiof2_clk_d),
4522 SH_PFC_PIN_GROUP(msiof2_sync_d),
4523 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4524 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4525 SH_PFC_PIN_GROUP(msiof2_txd_d),
4526 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4527 SH_PFC_PIN_GROUP(msiof3_clk_a),
4528 SH_PFC_PIN_GROUP(msiof3_sync_a),
4529 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4530 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4531 SH_PFC_PIN_GROUP(msiof3_txd_a),
4532 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4533 SH_PFC_PIN_GROUP(msiof3_clk_b),
4534 SH_PFC_PIN_GROUP(msiof3_sync_b),
4535 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4536 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4537 SH_PFC_PIN_GROUP(msiof3_txd_b),
4538 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4539 SH_PFC_PIN_GROUP(msiof3_clk_c),
4540 SH_PFC_PIN_GROUP(msiof3_sync_c),
4541 SH_PFC_PIN_GROUP(msiof3_txd_c),
4542 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4543 SH_PFC_PIN_GROUP(msiof3_clk_d),
4544 SH_PFC_PIN_GROUP(msiof3_sync_d),
4545 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4546 SH_PFC_PIN_GROUP(msiof3_txd_d),
4547 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4548 SH_PFC_PIN_GROUP(msiof3_clk_e),
4549 SH_PFC_PIN_GROUP(msiof3_sync_e),
4550 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4551 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4552 SH_PFC_PIN_GROUP(msiof3_txd_e),
4553 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4554 SH_PFC_PIN_GROUP(pwm0),
4555 SH_PFC_PIN_GROUP(pwm1_a),
4556 SH_PFC_PIN_GROUP(pwm1_b),
4557 SH_PFC_PIN_GROUP(pwm2_a),
4558 SH_PFC_PIN_GROUP(pwm2_b),
4559 SH_PFC_PIN_GROUP(pwm3_a),
4560 SH_PFC_PIN_GROUP(pwm3_b),
4561 SH_PFC_PIN_GROUP(pwm4_a),
4562 SH_PFC_PIN_GROUP(pwm4_b),
4563 SH_PFC_PIN_GROUP(pwm5_a),
4564 SH_PFC_PIN_GROUP(pwm5_b),
4565 SH_PFC_PIN_GROUP(pwm6_a),
4566 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4567 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4568 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4569 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4570 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4571 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4572 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4573 SH_PFC_PIN_GROUP(sata0_devslp_a),
4574 SH_PFC_PIN_GROUP(sata0_devslp_b),
4575 SH_PFC_PIN_GROUP(scif0_data),
4576 SH_PFC_PIN_GROUP(scif0_clk),
4577 SH_PFC_PIN_GROUP(scif0_ctrl),
4578 SH_PFC_PIN_GROUP(scif1_data_a),
4579 SH_PFC_PIN_GROUP(scif1_clk),
4580 SH_PFC_PIN_GROUP(scif1_ctrl),
4581 SH_PFC_PIN_GROUP(scif1_data_b),
4582 SH_PFC_PIN_GROUP(scif2_data_a),
4583 SH_PFC_PIN_GROUP(scif2_clk),
4584 SH_PFC_PIN_GROUP(scif2_data_b),
4585 SH_PFC_PIN_GROUP(scif3_data_a),
4586 SH_PFC_PIN_GROUP(scif3_clk),
4587 SH_PFC_PIN_GROUP(scif3_ctrl),
4588 SH_PFC_PIN_GROUP(scif3_data_b),
4589 SH_PFC_PIN_GROUP(scif4_data_a),
4590 SH_PFC_PIN_GROUP(scif4_clk_a),
4591 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4592 SH_PFC_PIN_GROUP(scif4_data_b),
4593 SH_PFC_PIN_GROUP(scif4_clk_b),
4594 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4595 SH_PFC_PIN_GROUP(scif4_data_c),
4596 SH_PFC_PIN_GROUP(scif4_clk_c),
4597 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4598 SH_PFC_PIN_GROUP(scif5_data_a),
4599 SH_PFC_PIN_GROUP(scif5_clk_a),
4600 SH_PFC_PIN_GROUP(scif5_data_b),
4601 SH_PFC_PIN_GROUP(scif5_clk_b),
4602 SH_PFC_PIN_GROUP(scif_clk_a),
4603 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4604 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4605 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4606 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4607 SH_PFC_PIN_GROUP(sdhi0_cd),
4608 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4609 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4610 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4611 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4612 SH_PFC_PIN_GROUP(sdhi1_cd),
4613 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4614 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4615 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4616 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4617 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4618 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4619 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4620 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4621 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4622 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4623 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4624 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4625 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4626 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4627 SH_PFC_PIN_GROUP(sdhi3_cd),
4628 SH_PFC_PIN_GROUP(sdhi3_wp),
4629 SH_PFC_PIN_GROUP(sdhi3_ds),
4630 SH_PFC_PIN_GROUP(ssi0_data),
4631 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4632 SH_PFC_PIN_GROUP(ssi1_data_a),
4633 SH_PFC_PIN_GROUP(ssi1_data_b),
4634 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4635 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4636 SH_PFC_PIN_GROUP(ssi2_data_a),
4637 SH_PFC_PIN_GROUP(ssi2_data_b),
4638 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4639 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4640 SH_PFC_PIN_GROUP(ssi3_data),
4641 SH_PFC_PIN_GROUP(ssi349_ctrl),
4642 SH_PFC_PIN_GROUP(ssi4_data),
4643 SH_PFC_PIN_GROUP(ssi4_ctrl),
4644 SH_PFC_PIN_GROUP(ssi5_data),
4645 SH_PFC_PIN_GROUP(ssi5_ctrl),
4646 SH_PFC_PIN_GROUP(ssi6_data),
4647 SH_PFC_PIN_GROUP(ssi6_ctrl),
4648 SH_PFC_PIN_GROUP(ssi7_data),
4649 SH_PFC_PIN_GROUP(ssi78_ctrl),
4650 SH_PFC_PIN_GROUP(ssi8_data),
4651 SH_PFC_PIN_GROUP(ssi9_data_a),
4652 SH_PFC_PIN_GROUP(ssi9_data_b),
4653 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4654 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4655 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4656 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4657 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4658 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4659 SH_PFC_PIN_GROUP(tpu_to0),
4660 SH_PFC_PIN_GROUP(tpu_to1),
4661 SH_PFC_PIN_GROUP(tpu_to2),
4662 SH_PFC_PIN_GROUP(tpu_to3),
4663 SH_PFC_PIN_GROUP(usb0),
4664 SH_PFC_PIN_GROUP(usb1),
4665 SH_PFC_PIN_GROUP(usb30),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4666 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4667 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4668 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4669 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4670 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4671 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4672 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4673 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4674 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4675 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4676 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4677 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4678 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4679 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4680 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4681 SH_PFC_PIN_GROUP(vin4_sync),
4682 SH_PFC_PIN_GROUP(vin4_field),
4683 SH_PFC_PIN_GROUP(vin4_clkenb),
4684 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4685 BUS_DATA_PIN_GROUP(vin5_data, 8),
4686 BUS_DATA_PIN_GROUP(vin5_data, 10),
4687 BUS_DATA_PIN_GROUP(vin5_data, 12),
4688 BUS_DATA_PIN_GROUP(vin5_data, 16),
4689 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4690 SH_PFC_PIN_GROUP(vin5_sync),
4691 SH_PFC_PIN_GROUP(vin5_field),
4692 SH_PFC_PIN_GROUP(vin5_clkenb),
4693 SH_PFC_PIN_GROUP(vin5_clk),
4694 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4695#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4696 .automotive = {
4697 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4698 SH_PFC_PIN_GROUP(drif0_data0_a),
4699 SH_PFC_PIN_GROUP(drif0_data1_a),
4700 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4701 SH_PFC_PIN_GROUP(drif0_data0_b),
4702 SH_PFC_PIN_GROUP(drif0_data1_b),
4703 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4704 SH_PFC_PIN_GROUP(drif0_data0_c),
4705 SH_PFC_PIN_GROUP(drif0_data1_c),
4706 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4707 SH_PFC_PIN_GROUP(drif1_data0_a),
4708 SH_PFC_PIN_GROUP(drif1_data1_a),
4709 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4710 SH_PFC_PIN_GROUP(drif1_data0_b),
4711 SH_PFC_PIN_GROUP(drif1_data1_b),
4712 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4713 SH_PFC_PIN_GROUP(drif1_data0_c),
4714 SH_PFC_PIN_GROUP(drif1_data1_c),
4715 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4716 SH_PFC_PIN_GROUP(drif2_data0_a),
4717 SH_PFC_PIN_GROUP(drif2_data1_a),
4718 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4719 SH_PFC_PIN_GROUP(drif2_data0_b),
4720 SH_PFC_PIN_GROUP(drif2_data1_b),
4721 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4722 SH_PFC_PIN_GROUP(drif3_data0_a),
4723 SH_PFC_PIN_GROUP(drif3_data1_a),
4724 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4725 SH_PFC_PIN_GROUP(drif3_data0_b),
4726 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4727 SH_PFC_PIN_GROUP(mlb_3pin),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4728 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4729#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4730};
4731
4732static const char * const audio_clk_groups[] = {
4733 "audio_clk_a_a",
4734 "audio_clk_a_b",
4735 "audio_clk_a_c",
4736 "audio_clk_b_a",
4737 "audio_clk_b_b",
4738 "audio_clk_c_a",
4739 "audio_clk_c_b",
4740 "audio_clkout_a",
4741 "audio_clkout_b",
4742 "audio_clkout_c",
4743 "audio_clkout_d",
4744 "audio_clkout1_a",
4745 "audio_clkout1_b",
4746 "audio_clkout2_a",
4747 "audio_clkout2_b",
4748 "audio_clkout3_a",
4749 "audio_clkout3_b",
4750};
4751
4752static const char * const avb_groups[] = {
4753 "avb_link",
4754 "avb_magic",
4755 "avb_phy_int",
4756 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4757 "avb_mdio",
4758 "avb_mii",
4759 "avb_avtp_pps",
4760 "avb_avtp_match_a",
4761 "avb_avtp_capture_a",
4762 "avb_avtp_match_b",
4763 "avb_avtp_capture_b",
4764};
4765
4766static const char * const can0_groups[] = {
4767 "can0_data_a",
4768 "can0_data_b",
4769};
4770
4771static const char * const can1_groups[] = {
4772 "can1_data",
4773};
4774
4775static const char * const can_clk_groups[] = {
4776 "can_clk",
4777};
4778
4779static const char * const canfd0_groups[] = {
4780 "canfd0_data_a",
4781 "canfd0_data_b",
4782};
4783
4784static const char * const canfd1_groups[] = {
4785 "canfd1_data",
4786};
4787
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4788#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4789static const char * const drif0_groups[] = {
4790 "drif0_ctrl_a",
4791 "drif0_data0_a",
4792 "drif0_data1_a",
4793 "drif0_ctrl_b",
4794 "drif0_data0_b",
4795 "drif0_data1_b",
4796 "drif0_ctrl_c",
4797 "drif0_data0_c",
4798 "drif0_data1_c",
4799};
4800
4801static const char * const drif1_groups[] = {
4802 "drif1_ctrl_a",
4803 "drif1_data0_a",
4804 "drif1_data1_a",
4805 "drif1_ctrl_b",
4806 "drif1_data0_b",
4807 "drif1_data1_b",
4808 "drif1_ctrl_c",
4809 "drif1_data0_c",
4810 "drif1_data1_c",
4811};
4812
4813static const char * const drif2_groups[] = {
4814 "drif2_ctrl_a",
4815 "drif2_data0_a",
4816 "drif2_data1_a",
4817 "drif2_ctrl_b",
4818 "drif2_data0_b",
4819 "drif2_data1_b",
4820};
4821
4822static const char * const drif3_groups[] = {
4823 "drif3_ctrl_a",
4824 "drif3_data0_a",
4825 "drif3_data1_a",
4826 "drif3_ctrl_b",
4827 "drif3_data0_b",
4828 "drif3_data1_b",
4829};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4830#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4831
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4832static const char * const du_groups[] = {
4833 "du_rgb666",
4834 "du_rgb888",
4835 "du_clk_out_0",
4836 "du_clk_out_1",
4837 "du_sync",
4838 "du_oddf",
4839 "du_cde",
4840 "du_disp",
4841};
4842
4843static const char * const hscif0_groups[] = {
4844 "hscif0_data",
4845 "hscif0_clk",
4846 "hscif0_ctrl",
4847};
4848
4849static const char * const hscif1_groups[] = {
4850 "hscif1_data_a",
4851 "hscif1_clk_a",
4852 "hscif1_ctrl_a",
4853 "hscif1_data_b",
4854 "hscif1_clk_b",
4855 "hscif1_ctrl_b",
4856};
4857
4858static const char * const hscif2_groups[] = {
4859 "hscif2_data_a",
4860 "hscif2_clk_a",
4861 "hscif2_ctrl_a",
4862 "hscif2_data_b",
4863 "hscif2_clk_b",
4864 "hscif2_ctrl_b",
4865 "hscif2_data_c",
4866 "hscif2_clk_c",
4867 "hscif2_ctrl_c",
4868};
4869
4870static const char * const hscif3_groups[] = {
4871 "hscif3_data_a",
4872 "hscif3_clk",
4873 "hscif3_ctrl",
4874 "hscif3_data_b",
4875 "hscif3_data_c",
4876 "hscif3_data_d",
4877};
4878
4879static const char * const hscif4_groups[] = {
4880 "hscif4_data_a",
4881 "hscif4_clk",
4882 "hscif4_ctrl",
4883 "hscif4_data_b",
4884};
4885
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4886static const char * const i2c0_groups[] = {
4887 "i2c0",
4888};
4889
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4890static const char * const i2c1_groups[] = {
4891 "i2c1_a",
4892 "i2c1_b",
4893};
4894
4895static const char * const i2c2_groups[] = {
4896 "i2c2_a",
4897 "i2c2_b",
4898};
4899
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4900static const char * const i2c3_groups[] = {
4901 "i2c3",
4902};
4903
4904static const char * const i2c5_groups[] = {
4905 "i2c5",
4906};
4907
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4908static const char * const i2c6_groups[] = {
4909 "i2c6_a",
4910 "i2c6_b",
4911 "i2c6_c",
4912};
4913
4914static const char * const intc_ex_groups[] = {
4915 "intc_ex_irq0",
4916 "intc_ex_irq1",
4917 "intc_ex_irq2",
4918 "intc_ex_irq3",
4919 "intc_ex_irq4",
4920 "intc_ex_irq5",
4921};
4922
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4923#ifdef CONFIG_PINCTRL_PFC_R8A77965
4924static const char * const mlb_3pin_groups[] = {
4925 "mlb_3pin",
4926};
4927#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4928
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4929static const char * const msiof0_groups[] = {
4930 "msiof0_clk",
4931 "msiof0_sync",
4932 "msiof0_ss1",
4933 "msiof0_ss2",
4934 "msiof0_txd",
4935 "msiof0_rxd",
4936};
4937
4938static const char * const msiof1_groups[] = {
4939 "msiof1_clk_a",
4940 "msiof1_sync_a",
4941 "msiof1_ss1_a",
4942 "msiof1_ss2_a",
4943 "msiof1_txd_a",
4944 "msiof1_rxd_a",
4945 "msiof1_clk_b",
4946 "msiof1_sync_b",
4947 "msiof1_ss1_b",
4948 "msiof1_ss2_b",
4949 "msiof1_txd_b",
4950 "msiof1_rxd_b",
4951 "msiof1_clk_c",
4952 "msiof1_sync_c",
4953 "msiof1_ss1_c",
4954 "msiof1_ss2_c",
4955 "msiof1_txd_c",
4956 "msiof1_rxd_c",
4957 "msiof1_clk_d",
4958 "msiof1_sync_d",
4959 "msiof1_ss1_d",
4960 "msiof1_ss2_d",
4961 "msiof1_txd_d",
4962 "msiof1_rxd_d",
4963 "msiof1_clk_e",
4964 "msiof1_sync_e",
4965 "msiof1_ss1_e",
4966 "msiof1_ss2_e",
4967 "msiof1_txd_e",
4968 "msiof1_rxd_e",
4969 "msiof1_clk_f",
4970 "msiof1_sync_f",
4971 "msiof1_ss1_f",
4972 "msiof1_ss2_f",
4973 "msiof1_txd_f",
4974 "msiof1_rxd_f",
4975 "msiof1_clk_g",
4976 "msiof1_sync_g",
4977 "msiof1_ss1_g",
4978 "msiof1_ss2_g",
4979 "msiof1_txd_g",
4980 "msiof1_rxd_g",
4981};
4982
4983static const char * const msiof2_groups[] = {
4984 "msiof2_clk_a",
4985 "msiof2_sync_a",
4986 "msiof2_ss1_a",
4987 "msiof2_ss2_a",
4988 "msiof2_txd_a",
4989 "msiof2_rxd_a",
4990 "msiof2_clk_b",
4991 "msiof2_sync_b",
4992 "msiof2_ss1_b",
4993 "msiof2_ss2_b",
4994 "msiof2_txd_b",
4995 "msiof2_rxd_b",
4996 "msiof2_clk_c",
4997 "msiof2_sync_c",
4998 "msiof2_ss1_c",
4999 "msiof2_ss2_c",
5000 "msiof2_txd_c",
5001 "msiof2_rxd_c",
5002 "msiof2_clk_d",
5003 "msiof2_sync_d",
5004 "msiof2_ss1_d",
5005 "msiof2_ss2_d",
5006 "msiof2_txd_d",
5007 "msiof2_rxd_d",
5008};
5009
5010static const char * const msiof3_groups[] = {
5011 "msiof3_clk_a",
5012 "msiof3_sync_a",
5013 "msiof3_ss1_a",
5014 "msiof3_ss2_a",
5015 "msiof3_txd_a",
5016 "msiof3_rxd_a",
5017 "msiof3_clk_b",
5018 "msiof3_sync_b",
5019 "msiof3_ss1_b",
5020 "msiof3_ss2_b",
5021 "msiof3_txd_b",
5022 "msiof3_rxd_b",
5023 "msiof3_clk_c",
5024 "msiof3_sync_c",
5025 "msiof3_txd_c",
5026 "msiof3_rxd_c",
5027 "msiof3_clk_d",
5028 "msiof3_sync_d",
5029 "msiof3_ss1_d",
5030 "msiof3_txd_d",
5031 "msiof3_rxd_d",
5032 "msiof3_clk_e",
5033 "msiof3_sync_e",
5034 "msiof3_ss1_e",
5035 "msiof3_ss2_e",
5036 "msiof3_txd_e",
5037 "msiof3_rxd_e",
5038};
5039
5040static const char * const pwm0_groups[] = {
5041 "pwm0",
5042};
5043
5044static const char * const pwm1_groups[] = {
5045 "pwm1_a",
5046 "pwm1_b",
5047};
5048
5049static const char * const pwm2_groups[] = {
5050 "pwm2_a",
5051 "pwm2_b",
5052};
5053
5054static const char * const pwm3_groups[] = {
5055 "pwm3_a",
5056 "pwm3_b",
5057};
5058
5059static const char * const pwm4_groups[] = {
5060 "pwm4_a",
5061 "pwm4_b",
5062};
5063
5064static const char * const pwm5_groups[] = {
5065 "pwm5_a",
5066 "pwm5_b",
5067};
5068
5069static const char * const pwm6_groups[] = {
5070 "pwm6_a",
5071 "pwm6_b",
5072};
5073
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5074static const char * const qspi0_groups[] = {
5075 "qspi0_ctrl",
5076 "qspi0_data2",
5077 "qspi0_data4",
5078};
5079
5080static const char * const qspi1_groups[] = {
5081 "qspi1_ctrl",
5082 "qspi1_data2",
5083 "qspi1_data4",
5084};
5085
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5086static const char * const sata0_groups[] = {
5087 "sata0_devslp_a",
5088 "sata0_devslp_b",
5089};
5090
5091static const char * const scif0_groups[] = {
5092 "scif0_data",
5093 "scif0_clk",
5094 "scif0_ctrl",
5095};
5096
5097static const char * const scif1_groups[] = {
5098 "scif1_data_a",
5099 "scif1_clk",
5100 "scif1_ctrl",
5101 "scif1_data_b",
5102};
5103static const char * const scif2_groups[] = {
5104 "scif2_data_a",
5105 "scif2_clk",
5106 "scif2_data_b",
5107};
5108
5109static const char * const scif3_groups[] = {
5110 "scif3_data_a",
5111 "scif3_clk",
5112 "scif3_ctrl",
5113 "scif3_data_b",
5114};
5115
5116static const char * const scif4_groups[] = {
5117 "scif4_data_a",
5118 "scif4_clk_a",
5119 "scif4_ctrl_a",
5120 "scif4_data_b",
5121 "scif4_clk_b",
5122 "scif4_ctrl_b",
5123 "scif4_data_c",
5124 "scif4_clk_c",
5125 "scif4_ctrl_c",
5126};
5127
5128static const char * const scif5_groups[] = {
5129 "scif5_data_a",
5130 "scif5_clk_a",
5131 "scif5_data_b",
5132 "scif5_clk_b",
5133};
5134
5135static const char * const scif_clk_groups[] = {
5136 "scif_clk_a",
5137 "scif_clk_b",
5138};
5139
5140static const char * const sdhi0_groups[] = {
5141 "sdhi0_data1",
5142 "sdhi0_data4",
5143 "sdhi0_ctrl",
5144 "sdhi0_cd",
5145 "sdhi0_wp",
5146};
5147
5148static const char * const sdhi1_groups[] = {
5149 "sdhi1_data1",
5150 "sdhi1_data4",
5151 "sdhi1_ctrl",
5152 "sdhi1_cd",
5153 "sdhi1_wp",
5154};
5155
5156static const char * const sdhi2_groups[] = {
5157 "sdhi2_data1",
5158 "sdhi2_data4",
5159 "sdhi2_data8",
5160 "sdhi2_ctrl",
5161 "sdhi2_cd_a",
5162 "sdhi2_wp_a",
5163 "sdhi2_cd_b",
5164 "sdhi2_wp_b",
5165 "sdhi2_ds",
5166};
5167
5168static const char * const sdhi3_groups[] = {
5169 "sdhi3_data1",
5170 "sdhi3_data4",
5171 "sdhi3_data8",
5172 "sdhi3_ctrl",
5173 "sdhi3_cd",
5174 "sdhi3_wp",
5175 "sdhi3_ds",
5176};
5177
5178static const char * const ssi_groups[] = {
5179 "ssi0_data",
5180 "ssi01239_ctrl",
5181 "ssi1_data_a",
5182 "ssi1_data_b",
5183 "ssi1_ctrl_a",
5184 "ssi1_ctrl_b",
5185 "ssi2_data_a",
5186 "ssi2_data_b",
5187 "ssi2_ctrl_a",
5188 "ssi2_ctrl_b",
5189 "ssi3_data",
5190 "ssi349_ctrl",
5191 "ssi4_data",
5192 "ssi4_ctrl",
5193 "ssi5_data",
5194 "ssi5_ctrl",
5195 "ssi6_data",
5196 "ssi6_ctrl",
5197 "ssi7_data",
5198 "ssi78_ctrl",
5199 "ssi8_data",
5200 "ssi9_data_a",
5201 "ssi9_data_b",
5202 "ssi9_ctrl_a",
5203 "ssi9_ctrl_b",
5204};
5205
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5206static const char * const tmu_groups[] = {
5207 "tmu_tclk1_a",
5208 "tmu_tclk1_b",
5209 "tmu_tclk2_a",
5210 "tmu_tclk2_b",
5211};
5212
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5213static const char * const tpu_groups[] = {
5214 "tpu_to0",
5215 "tpu_to1",
5216 "tpu_to2",
5217 "tpu_to3",
5218};
5219
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5220static const char * const usb0_groups[] = {
5221 "usb0",
5222};
5223
5224static const char * const usb1_groups[] = {
5225 "usb1",
5226};
5227
5228static const char * const usb30_groups[] = {
5229 "usb30",
5230};
5231
5232static const char * const vin4_groups[] = {
5233 "vin4_data8_a",
5234 "vin4_data10_a",
5235 "vin4_data12_a",
5236 "vin4_data16_a",
5237 "vin4_data18_a",
5238 "vin4_data20_a",
5239 "vin4_data24_a",
5240 "vin4_data8_b",
5241 "vin4_data10_b",
5242 "vin4_data12_b",
5243 "vin4_data16_b",
5244 "vin4_data18_b",
5245 "vin4_data20_b",
5246 "vin4_data24_b",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5247 "vin4_g8",
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5248 "vin4_sync",
5249 "vin4_field",
5250 "vin4_clkenb",
5251 "vin4_clk",
5252};
5253
5254static const char * const vin5_groups[] = {
5255 "vin5_data8",
5256 "vin5_data10",
5257 "vin5_data12",
5258 "vin5_data16",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5259 "vin5_high8",
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5260 "vin5_sync",
5261 "vin5_field",
5262 "vin5_clkenb",
5263 "vin5_clk",
5264};
5265
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5266static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5267 struct sh_pfc_function common[53];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5268#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5269 struct sh_pfc_function automotive[5];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5270#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5271} pinmux_functions = {
5272 .common = {
5273 SH_PFC_FUNCTION(audio_clk),
5274 SH_PFC_FUNCTION(avb),
5275 SH_PFC_FUNCTION(can0),
5276 SH_PFC_FUNCTION(can1),
5277 SH_PFC_FUNCTION(can_clk),
5278 SH_PFC_FUNCTION(canfd0),
5279 SH_PFC_FUNCTION(canfd1),
5280 SH_PFC_FUNCTION(du),
5281 SH_PFC_FUNCTION(hscif0),
5282 SH_PFC_FUNCTION(hscif1),
5283 SH_PFC_FUNCTION(hscif2),
5284 SH_PFC_FUNCTION(hscif3),
5285 SH_PFC_FUNCTION(hscif4),
5286 SH_PFC_FUNCTION(i2c0),
5287 SH_PFC_FUNCTION(i2c1),
5288 SH_PFC_FUNCTION(i2c2),
5289 SH_PFC_FUNCTION(i2c3),
5290 SH_PFC_FUNCTION(i2c5),
5291 SH_PFC_FUNCTION(i2c6),
5292 SH_PFC_FUNCTION(intc_ex),
5293 SH_PFC_FUNCTION(msiof0),
5294 SH_PFC_FUNCTION(msiof1),
5295 SH_PFC_FUNCTION(msiof2),
5296 SH_PFC_FUNCTION(msiof3),
5297 SH_PFC_FUNCTION(pwm0),
5298 SH_PFC_FUNCTION(pwm1),
5299 SH_PFC_FUNCTION(pwm2),
5300 SH_PFC_FUNCTION(pwm3),
5301 SH_PFC_FUNCTION(pwm4),
5302 SH_PFC_FUNCTION(pwm5),
5303 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5304 SH_PFC_FUNCTION(qspi0),
5305 SH_PFC_FUNCTION(qspi1),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5306 SH_PFC_FUNCTION(sata0),
5307 SH_PFC_FUNCTION(scif0),
5308 SH_PFC_FUNCTION(scif1),
5309 SH_PFC_FUNCTION(scif2),
5310 SH_PFC_FUNCTION(scif3),
5311 SH_PFC_FUNCTION(scif4),
5312 SH_PFC_FUNCTION(scif5),
5313 SH_PFC_FUNCTION(scif_clk),
5314 SH_PFC_FUNCTION(sdhi0),
5315 SH_PFC_FUNCTION(sdhi1),
5316 SH_PFC_FUNCTION(sdhi2),
5317 SH_PFC_FUNCTION(sdhi3),
5318 SH_PFC_FUNCTION(ssi),
5319 SH_PFC_FUNCTION(tmu),
5320 SH_PFC_FUNCTION(tpu),
5321 SH_PFC_FUNCTION(usb0),
5322 SH_PFC_FUNCTION(usb1),
5323 SH_PFC_FUNCTION(usb30),
5324 SH_PFC_FUNCTION(vin4),
5325 SH_PFC_FUNCTION(vin5),
5326 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5327#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5328 .automotive = {
5329 SH_PFC_FUNCTION(drif0),
5330 SH_PFC_FUNCTION(drif1),
5331 SH_PFC_FUNCTION(drif2),
5332 SH_PFC_FUNCTION(drif3),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5333 SH_PFC_FUNCTION(mlb_3pin),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5334 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5335#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5336};
5337
5338static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5339#define F_(x, y) FN_##y
5340#define FM(x) FN_##x
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5341 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5342 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5343 1, 1, 1, 1, 1),
5344 GROUP(
5345 /* GP0_31_16 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5346 GP_0_15_FN, GPSR0_15,
5347 GP_0_14_FN, GPSR0_14,
5348 GP_0_13_FN, GPSR0_13,
5349 GP_0_12_FN, GPSR0_12,
5350 GP_0_11_FN, GPSR0_11,
5351 GP_0_10_FN, GPSR0_10,
5352 GP_0_9_FN, GPSR0_9,
5353 GP_0_8_FN, GPSR0_8,
5354 GP_0_7_FN, GPSR0_7,
5355 GP_0_6_FN, GPSR0_6,
5356 GP_0_5_FN, GPSR0_5,
5357 GP_0_4_FN, GPSR0_4,
5358 GP_0_3_FN, GPSR0_3,
5359 GP_0_2_FN, GPSR0_2,
5360 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5361 GP_0_0_FN, GPSR0_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5362 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5363 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5364 0, 0,
5365 0, 0,
5366 0, 0,
5367 GP_1_28_FN, GPSR1_28,
5368 GP_1_27_FN, GPSR1_27,
5369 GP_1_26_FN, GPSR1_26,
5370 GP_1_25_FN, GPSR1_25,
5371 GP_1_24_FN, GPSR1_24,
5372 GP_1_23_FN, GPSR1_23,
5373 GP_1_22_FN, GPSR1_22,
5374 GP_1_21_FN, GPSR1_21,
5375 GP_1_20_FN, GPSR1_20,
5376 GP_1_19_FN, GPSR1_19,
5377 GP_1_18_FN, GPSR1_18,
5378 GP_1_17_FN, GPSR1_17,
5379 GP_1_16_FN, GPSR1_16,
5380 GP_1_15_FN, GPSR1_15,
5381 GP_1_14_FN, GPSR1_14,
5382 GP_1_13_FN, GPSR1_13,
5383 GP_1_12_FN, GPSR1_12,
5384 GP_1_11_FN, GPSR1_11,
5385 GP_1_10_FN, GPSR1_10,
5386 GP_1_9_FN, GPSR1_9,
5387 GP_1_8_FN, GPSR1_8,
5388 GP_1_7_FN, GPSR1_7,
5389 GP_1_6_FN, GPSR1_6,
5390 GP_1_5_FN, GPSR1_5,
5391 GP_1_4_FN, GPSR1_4,
5392 GP_1_3_FN, GPSR1_3,
5393 GP_1_2_FN, GPSR1_2,
5394 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5395 GP_1_0_FN, GPSR1_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5396 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5397 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5398 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5399 1, 1, 1, 1),
5400 GROUP(
5401 /* GP2_31_15 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5402 GP_2_14_FN, GPSR2_14,
5403 GP_2_13_FN, GPSR2_13,
5404 GP_2_12_FN, GPSR2_12,
5405 GP_2_11_FN, GPSR2_11,
5406 GP_2_10_FN, GPSR2_10,
5407 GP_2_9_FN, GPSR2_9,
5408 GP_2_8_FN, GPSR2_8,
5409 GP_2_7_FN, GPSR2_7,
5410 GP_2_6_FN, GPSR2_6,
5411 GP_2_5_FN, GPSR2_5,
5412 GP_2_4_FN, GPSR2_4,
5413 GP_2_3_FN, GPSR2_3,
5414 GP_2_2_FN, GPSR2_2,
5415 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5416 GP_2_0_FN, GPSR2_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5417 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5418 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5419 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5420 1, 1, 1, 1, 1),
5421 GROUP(
5422 /* GP3_31_16 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5423 GP_3_15_FN, GPSR3_15,
5424 GP_3_14_FN, GPSR3_14,
5425 GP_3_13_FN, GPSR3_13,
5426 GP_3_12_FN, GPSR3_12,
5427 GP_3_11_FN, GPSR3_11,
5428 GP_3_10_FN, GPSR3_10,
5429 GP_3_9_FN, GPSR3_9,
5430 GP_3_8_FN, GPSR3_8,
5431 GP_3_7_FN, GPSR3_7,
5432 GP_3_6_FN, GPSR3_6,
5433 GP_3_5_FN, GPSR3_5,
5434 GP_3_4_FN, GPSR3_4,
5435 GP_3_3_FN, GPSR3_3,
5436 GP_3_2_FN, GPSR3_2,
5437 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5438 GP_3_0_FN, GPSR3_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5439 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5440 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5441 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5442 1, 1, 1, 1, 1, 1, 1),
5443 GROUP(
5444 /* GP4_31_18 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5445 GP_4_17_FN, GPSR4_17,
5446 GP_4_16_FN, GPSR4_16,
5447 GP_4_15_FN, GPSR4_15,
5448 GP_4_14_FN, GPSR4_14,
5449 GP_4_13_FN, GPSR4_13,
5450 GP_4_12_FN, GPSR4_12,
5451 GP_4_11_FN, GPSR4_11,
5452 GP_4_10_FN, GPSR4_10,
5453 GP_4_9_FN, GPSR4_9,
5454 GP_4_8_FN, GPSR4_8,
5455 GP_4_7_FN, GPSR4_7,
5456 GP_4_6_FN, GPSR4_6,
5457 GP_4_5_FN, GPSR4_5,
5458 GP_4_4_FN, GPSR4_4,
5459 GP_4_3_FN, GPSR4_3,
5460 GP_4_2_FN, GPSR4_2,
5461 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5462 GP_4_0_FN, GPSR4_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5463 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5464 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5465 0, 0,
5466 0, 0,
5467 0, 0,
5468 0, 0,
5469 0, 0,
5470 0, 0,
5471 GP_5_25_FN, GPSR5_25,
5472 GP_5_24_FN, GPSR5_24,
5473 GP_5_23_FN, GPSR5_23,
5474 GP_5_22_FN, GPSR5_22,
5475 GP_5_21_FN, GPSR5_21,
5476 GP_5_20_FN, GPSR5_20,
5477 GP_5_19_FN, GPSR5_19,
5478 GP_5_18_FN, GPSR5_18,
5479 GP_5_17_FN, GPSR5_17,
5480 GP_5_16_FN, GPSR5_16,
5481 GP_5_15_FN, GPSR5_15,
5482 GP_5_14_FN, GPSR5_14,
5483 GP_5_13_FN, GPSR5_13,
5484 GP_5_12_FN, GPSR5_12,
5485 GP_5_11_FN, GPSR5_11,
5486 GP_5_10_FN, GPSR5_10,
5487 GP_5_9_FN, GPSR5_9,
5488 GP_5_8_FN, GPSR5_8,
5489 GP_5_7_FN, GPSR5_7,
5490 GP_5_6_FN, GPSR5_6,
5491 GP_5_5_FN, GPSR5_5,
5492 GP_5_4_FN, GPSR5_4,
5493 GP_5_3_FN, GPSR5_3,
5494 GP_5_2_FN, GPSR5_2,
5495 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5496 GP_5_0_FN, GPSR5_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5497 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5498 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5499 GP_6_31_FN, GPSR6_31,
5500 GP_6_30_FN, GPSR6_30,
5501 GP_6_29_FN, GPSR6_29,
5502 GP_6_28_FN, GPSR6_28,
5503 GP_6_27_FN, GPSR6_27,
5504 GP_6_26_FN, GPSR6_26,
5505 GP_6_25_FN, GPSR6_25,
5506 GP_6_24_FN, GPSR6_24,
5507 GP_6_23_FN, GPSR6_23,
5508 GP_6_22_FN, GPSR6_22,
5509 GP_6_21_FN, GPSR6_21,
5510 GP_6_20_FN, GPSR6_20,
5511 GP_6_19_FN, GPSR6_19,
5512 GP_6_18_FN, GPSR6_18,
5513 GP_6_17_FN, GPSR6_17,
5514 GP_6_16_FN, GPSR6_16,
5515 GP_6_15_FN, GPSR6_15,
5516 GP_6_14_FN, GPSR6_14,
5517 GP_6_13_FN, GPSR6_13,
5518 GP_6_12_FN, GPSR6_12,
5519 GP_6_11_FN, GPSR6_11,
5520 GP_6_10_FN, GPSR6_10,
5521 GP_6_9_FN, GPSR6_9,
5522 GP_6_8_FN, GPSR6_8,
5523 GP_6_7_FN, GPSR6_7,
5524 GP_6_6_FN, GPSR6_6,
5525 GP_6_5_FN, GPSR6_5,
5526 GP_6_4_FN, GPSR6_4,
5527 GP_6_3_FN, GPSR6_3,
5528 GP_6_2_FN, GPSR6_2,
5529 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5530 GP_6_0_FN, GPSR6_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5531 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5532 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5533 GROUP(-28, 1, 1, 1, 1),
5534 GROUP(
5535 /* GP7_31_4 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5536 GP_7_3_FN, GPSR7_3,
5537 GP_7_2_FN, GPSR7_2,
5538 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5539 GP_7_0_FN, GPSR7_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5540 },
5541#undef F_
5542#undef FM
5543
5544#define F_(x, y) x,
5545#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5546 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5547 IP0_31_28
5548 IP0_27_24
5549 IP0_23_20
5550 IP0_19_16
5551 IP0_15_12
5552 IP0_11_8
5553 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5554 IP0_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5555 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5556 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5557 IP1_31_28
5558 IP1_27_24
5559 IP1_23_20
5560 IP1_19_16
5561 IP1_15_12
5562 IP1_11_8
5563 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5564 IP1_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5565 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5566 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5567 IP2_31_28
5568 IP2_27_24
5569 IP2_23_20
5570 IP2_19_16
5571 IP2_15_12
5572 IP2_11_8
5573 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5574 IP2_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5575 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5576 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5577 IP3_31_28
5578 IP3_27_24
5579 IP3_23_20
5580 IP3_19_16
5581 IP3_15_12
5582 IP3_11_8
5583 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5584 IP3_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5585 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5586 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5587 IP4_31_28
5588 IP4_27_24
5589 IP4_23_20
5590 IP4_19_16
5591 IP4_15_12
5592 IP4_11_8
5593 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5594 IP4_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5595 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5596 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5597 IP5_31_28
5598 IP5_27_24
5599 IP5_23_20
5600 IP5_19_16
5601 IP5_15_12
5602 IP5_11_8
5603 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5604 IP5_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5605 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5606 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5607 IP6_31_28
5608 IP6_27_24
5609 IP6_23_20
5610 IP6_19_16
5611 IP6_15_12
5612 IP6_11_8
5613 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5614 IP6_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5615 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5616 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5617 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5618 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5619 IP7_31_28
5620 IP7_27_24
5621 IP7_23_20
5622 IP7_19_16
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5623 /* IP7_15_12 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5624 IP7_11_8
5625 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5626 IP7_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5627 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5628 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5629 IP8_31_28
5630 IP8_27_24
5631 IP8_23_20
5632 IP8_19_16
5633 IP8_15_12
5634 IP8_11_8
5635 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5636 IP8_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5637 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5638 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5639 IP9_31_28
5640 IP9_27_24
5641 IP9_23_20
5642 IP9_19_16
5643 IP9_15_12
5644 IP9_11_8
5645 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5646 IP9_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5647 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5648 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5649 IP10_31_28
5650 IP10_27_24
5651 IP10_23_20
5652 IP10_19_16
5653 IP10_15_12
5654 IP10_11_8
5655 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5656 IP10_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5657 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5658 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5659 IP11_31_28
5660 IP11_27_24
5661 IP11_23_20
5662 IP11_19_16
5663 IP11_15_12
5664 IP11_11_8
5665 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5666 IP11_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5667 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5668 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5669 IP12_31_28
5670 IP12_27_24
5671 IP12_23_20
5672 IP12_19_16
5673 IP12_15_12
5674 IP12_11_8
5675 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5676 IP12_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5677 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5678 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5679 IP13_31_28
5680 IP13_27_24
5681 IP13_23_20
5682 IP13_19_16
5683 IP13_15_12
5684 IP13_11_8
5685 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5686 IP13_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5687 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5688 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5689 IP14_31_28
5690 IP14_27_24
5691 IP14_23_20
5692 IP14_19_16
5693 IP14_15_12
5694 IP14_11_8
5695 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5696 IP14_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5697 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5698 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5699 IP15_31_28
5700 IP15_27_24
5701 IP15_23_20
5702 IP15_19_16
5703 IP15_15_12
5704 IP15_11_8
5705 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5706 IP15_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5707 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5708 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5709 IP16_31_28
5710 IP16_27_24
5711 IP16_23_20
5712 IP16_19_16
5713 IP16_15_12
5714 IP16_11_8
5715 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5716 IP16_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5717 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5718 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5719 IP17_31_28
5720 IP17_27_24
5721 IP17_23_20
5722 IP17_19_16
5723 IP17_15_12
5724 IP17_11_8
5725 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5726 IP17_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5727 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5728 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5729 GROUP(-24, 4, 4),
5730 GROUP(
5731 /* IP18_31_8 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5732 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5733 IP18_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5734 },
5735#undef F_
5736#undef FM
5737
5738#define F_(x, y) x,
5739#define FM(x) FN_##x,
5740 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5741 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5742 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5743 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5744 MOD_SEL0_31_30_29
5745 MOD_SEL0_28_27
5746 MOD_SEL0_26_25_24
5747 MOD_SEL0_23
5748 MOD_SEL0_22
5749 MOD_SEL0_21
5750 MOD_SEL0_20
5751 MOD_SEL0_19
5752 MOD_SEL0_18_17
5753 MOD_SEL0_16
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5754 /* RESERVED 15 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5755 MOD_SEL0_14_13
5756 MOD_SEL0_12
5757 MOD_SEL0_11
5758 MOD_SEL0_10
5759 MOD_SEL0_9_8
5760 MOD_SEL0_7_6
5761 MOD_SEL0_5
5762 MOD_SEL0_4_3
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5763 /* RESERVED 2, 1, 0 */ ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5764 },
5765 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5766 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5767 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5768 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5769 MOD_SEL1_31_30
5770 MOD_SEL1_29_28_27
5771 MOD_SEL1_26
5772 MOD_SEL1_25_24
5773 MOD_SEL1_23_22_21
5774 MOD_SEL1_20
5775 MOD_SEL1_19
5776 MOD_SEL1_18_17
5777 MOD_SEL1_16
5778 MOD_SEL1_15_14
5779 MOD_SEL1_13
5780 MOD_SEL1_12
5781 MOD_SEL1_11
5782 MOD_SEL1_10
5783 MOD_SEL1_9
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5784 /* RESERVED 8, 7 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5785 MOD_SEL1_6
5786 MOD_SEL1_5
5787 MOD_SEL1_4
5788 MOD_SEL1_3
5789 MOD_SEL1_2
5790 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5791 MOD_SEL1_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5792 },
5793 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5794 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5795 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5796 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5797 MOD_SEL2_31
5798 MOD_SEL2_30
5799 MOD_SEL2_29
5800 MOD_SEL2_28_27
5801 MOD_SEL2_26
5802 MOD_SEL2_25_24_23
5803 MOD_SEL2_22
5804 MOD_SEL2_21
5805 MOD_SEL2_20
5806 MOD_SEL2_19
5807 MOD_SEL2_18
5808 MOD_SEL2_17
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5809 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5810 MOD_SEL2_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5811 },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]5812 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5813};
5814
5815static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5816 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5817 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5818 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5819 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5820 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5821 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5822 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5823 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5824 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5827 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5828 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5829 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5830 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5831 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5832 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5833 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5834 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5837 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5838 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5839 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5840 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5841 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5842 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5843 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5844 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5847 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5848 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5849 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5850 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5851 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5852 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5853 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5854 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5857 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5858 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5859 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5860 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5861 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5862 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5863 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5864 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5865 } },
5866 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5867 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5868 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5869 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5870 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5871 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5872 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5873 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5874 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5875 } },
5876 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5877 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5878 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5879 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5880 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5881 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5882 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5883 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5884 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5885 } },
5886 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5887 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5888 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5889 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5890 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5891 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5892 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5893 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5894 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5895 } },
5896 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5897 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5898 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5899 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5900 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5901 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5902 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5903 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5904 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5905 } },
5906 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5907 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5908 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5909 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5910 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5911 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5912 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5913 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5914 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5915 } },
5916 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5917 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5918 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5919 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5920 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5921 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5922 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5923 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5924 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5925 } },
5926 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5927 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5928 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5929 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5930 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5931 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5932 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5933 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5934 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5935 } },
5936 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5937 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5938 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5939 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5940 } },
5941 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5942 { PIN_TDO, 28, 2 }, /* TDO */
5943 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5944 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5945 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5946 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5947 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5948 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5949 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5950 } },
5951 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5952 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5953 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5954 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5955 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5956 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5957 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5958 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5959 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5960 } },
5961 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5962 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5963 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5964 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5965 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5966 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5967 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5968 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5969 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5970 } },
5971 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5972 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5973 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5974 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5975 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5976 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5977 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5978 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5979 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5980 } },
5981 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5982 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5983 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5984 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5985 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5986 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5987 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5988 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5989 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5990 } },
5991 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5992 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5993 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5994 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5995 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5996 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5997 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5998 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5999 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6000 } },
6001 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6002 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6003 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6004 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6005 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6006 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6007 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6008 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6009 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6010 } },
6011 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6012 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6013 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6014 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6015 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6016 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6017 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6018 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6019 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6020 } },
6021 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6022 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6023 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6024 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6025 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6026 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6027 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6028 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6029 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6030 } },
6031 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6032 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6033 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6034 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6035 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6036 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6037 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6038 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6039 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6040 } },
6041 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6042 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6043 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6044 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6045 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6046 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6047 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6048 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6049 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6050 } },
6051 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6052 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6053 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6054 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6055 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6056 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6057 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6058 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6059 } },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6060 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6061};
6062
6063enum ioctrl_regs {
6064 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6065 TDSELCTRL,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6066};
6067
6068static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6069 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6070 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6071 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6072};
6073
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6074static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6075{
6076 int bit = -EINVAL;
6077
6078 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6079
6080 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6081 bit = pin & 0x1f;
6082
6083 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6084 bit = (pin & 0x1f) + 12;
6085
6086 return bit;
6087}
6088
6089static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6090 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6091 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6092 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6093 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6094 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6095 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6096 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6097 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6098 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6099 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6100 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6101 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6102 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6103 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6104 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6105 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6106 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6107 [16] = PIN_AVB_RXC, /* AVB_RXC */
6108 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6109 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6110 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6111 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6112 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6113 [22] = PIN_AVB_TXC, /* AVB_TXC */
6114 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6115 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6116 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6117 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6118 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6119 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6120 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6121 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6122 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6123 } },
6124 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6125 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6126 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6127 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6128 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6129 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6130 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6131 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6132 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6133 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6134 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6135 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6136 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6137 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6138 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6139 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6140 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6141 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6142 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6143 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6144 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6145 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6146 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6147 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6148 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6149 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6150 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6151 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6152 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6153 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6154 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6155 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6156 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6157 } },
6158 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6159 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6160 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6161 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6162 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6163 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6164 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6165 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6166 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6167 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6168 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6169 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6170 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6171 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6172 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6173 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6174 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6175 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6176 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6177 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6178 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6179 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6180 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6181 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6182 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6183 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6184 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6185 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6186 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6187 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6188 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6189 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6190 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6191 } },
6192 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6193 [ 0] = SH_PFC_PIN_NONE,
6194 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6195 [ 2] = PIN_FSCLKST, /* FSCLKST */
6196 [ 3] = PIN_EXTALR, /* EXTALR*/
6197 [ 4] = PIN_TRST_N, /* TRST# */
6198 [ 5] = PIN_TCK, /* TCK */
6199 [ 6] = PIN_TMS, /* TMS */
6200 [ 7] = PIN_TDI, /* TDI */
6201 [ 8] = SH_PFC_PIN_NONE,
6202 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6203 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6204 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6205 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6206 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6207 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6208 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6209 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6210 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6211 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6212 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6213 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6214 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6215 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6216 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6217 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6218 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6219 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6220 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6221 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6222 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6223 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6224 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6225 } },
6226 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6227 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6228 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6229 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6230 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6231 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6232 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6233 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6234 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6235 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6236 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6237 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6238 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6239 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6240 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6241 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6242 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6243 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6244 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6245 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6246 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6247 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6248 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6249 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6250 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6251 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6252 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6253 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6254 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6255 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6256 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6257 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6258 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6259 } },
6260 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6261 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6262 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6263 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6264 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6265 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6266 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6267 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6268 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6269 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6270 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6271 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6272 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6273 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6274 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6275 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6276 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6277 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6278 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6279 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6280 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6281 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6282 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6283 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6284 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6285 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6286 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6287 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6288 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6289 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6290 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6291 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6292 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6293 } },
6294 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6295 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6296 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6297 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6298 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6299 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6300 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6301 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6302 [ 7] = SH_PFC_PIN_NONE,
6303 [ 8] = SH_PFC_PIN_NONE,
6304 [ 9] = SH_PFC_PIN_NONE,
6305 [10] = SH_PFC_PIN_NONE,
6306 [11] = SH_PFC_PIN_NONE,
6307 [12] = SH_PFC_PIN_NONE,
6308 [13] = SH_PFC_PIN_NONE,
6309 [14] = SH_PFC_PIN_NONE,
6310 [15] = SH_PFC_PIN_NONE,
6311 [16] = SH_PFC_PIN_NONE,
6312 [17] = SH_PFC_PIN_NONE,
6313 [18] = SH_PFC_PIN_NONE,
6314 [19] = SH_PFC_PIN_NONE,
6315 [20] = SH_PFC_PIN_NONE,
6316 [21] = SH_PFC_PIN_NONE,
6317 [22] = SH_PFC_PIN_NONE,
6318 [23] = SH_PFC_PIN_NONE,
6319 [24] = SH_PFC_PIN_NONE,
6320 [25] = SH_PFC_PIN_NONE,
6321 [26] = SH_PFC_PIN_NONE,
6322 [27] = SH_PFC_PIN_NONE,
6323 [28] = SH_PFC_PIN_NONE,
6324 [29] = SH_PFC_PIN_NONE,
6325 [30] = SH_PFC_PIN_NONE,
6326 [31] = SH_PFC_PIN_NONE,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6327 } },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6328 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6329};
6330
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6331static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6332 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6333 .get_bias = rcar_pinmux_get_bias,
6334 .set_bias = rcar_pinmux_set_bias,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6335};
6336
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6337#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6338const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6339 .name = "r8a774b1_pfc",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6340 .ops = &r8a77965_pfc_ops,
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6341 .unlock_reg = 0xe6060000, /* PMMR */
6342
6343 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6344
6345 .pins = pinmux_pins,
6346 .nr_pins = ARRAY_SIZE(pinmux_pins),
6347 .groups = pinmux_groups.common,
6348 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6349 .functions = pinmux_functions.common,
6350 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6351
6352 .cfg_regs = pinmux_config_regs,
6353 .drive_regs = pinmux_drive_regs,
6354 .bias_regs = pinmux_bias_regs,
6355 .ioctrl_regs = pinmux_ioctrl_regs,
6356
6357 .pinmux_data = pinmux_data,
6358 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6359};
6360#endif
6361
6362#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6363const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6364 .name = "r8a77965_pfc",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6365 .ops = &r8a77965_pfc_ops,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6366 .unlock_reg = 0xe6060000, /* PMMR */
6367
6368 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6369
6370 .pins = pinmux_pins,
6371 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6372 .groups = pinmux_groups.common,
6373 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6374 ARRAY_SIZE(pinmux_groups.automotive),
6375 .functions = pinmux_functions.common,
6376 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6377 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6378
6379 .cfg_regs = pinmux_config_regs,
6380 .drive_regs = pinmux_drive_regs,
6381 .bias_regs = pinmux_bias_regs,
6382 .ioctrl_regs = pinmux_ioctrl_regs,
6383
6384 .pinmux_data = pinmux_data,
6385 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6386};
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6387#endif