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git01.mediatek.com / filogic / uboot / ac73f47476abd12c12830c464a096d0313e82d11 / . / arch / arm / include / asm / arch-mxs / sys_proto.h
blob: 17afd1b29e4f8d4d2c0870e0e71de4a53d277f5b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]2/*
Otavio Salvadord8e90632012-08-19 04:58:28 +0000[diff] [blame]3 * Freescale i.MX23/i.MX28 specific functions
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]4 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]7 */
8
Peng Fanf664c142015-08-13 10:55:34 +0800[diff] [blame]9#ifndef __MXS_SYS_PROTO_H__
10#define __MXS_SYS_PROTO_H__
Jeroen Hofstee4f2ef482014-10-08 22:57:50 +0200[diff] [blame]11
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]12#include <asm/mach-imx/sys_proto.h>
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]13
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900[diff] [blame]14int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
15 int (*cd)(int));
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000[diff] [blame]16
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]17#ifdef CONFIG_SPL_BUILD
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]18
19#if defined(CONFIG_MX23)
20#include <asm/arch/iomux-mx23.h>
21#elif defined(CONFIG_MX28)
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]22#include <asm/arch/iomux-mx28.h>
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]23#endif
24
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]25void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
26 const iomux_cfg_t *iomux_setup,
27 const unsigned int iomux_size);
Michael Heimpold364e5362015-12-13 12:08:37 +0100[diff] [blame]28
29void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]30#endif
31
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]32struct mxs_pair {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]33 uint8_t boot_pads;
34 uint8_t boot_mask;
35 const char *mode;
36};
37
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]38static const struct mxs_pair mxs_boot_modes[] = {
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]39#if defined(CONFIG_MX23)
40 { 0x00, 0x0f, "USB" },
41 { 0x01, 0x1f, "I2C, master" },
42 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
43 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
44 { 0x04, 0x1f, "NAND" },
Marek Vasutedc43b02013-09-20 01:36:44 +0200[diff] [blame]45 { 0x06, 0x1f, "JTAG" },
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]46 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
47 { 0x09, 0x1f, "SSP SD/MMC #0" },
48 { 0x0a, 0x1f, "SSP SD/MMC #1" },
49 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
50#elif defined(CONFIG_MX28)
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]51 { 0x00, 0x0f, "USB #0" },
52 { 0x01, 0x1f, "I2C #0, master, 3V3" },
53 { 0x11, 0x1f, "I2C #0, master, 1V8" },
54 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
55 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
56 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
57 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
58 { 0x04, 0x1f, "NAND, 3V3" },
59 { 0x14, 0x1f, "NAND, 1V8" },
Marek Vasutedc43b02013-09-20 01:36:44 +0200[diff] [blame]60 { 0x06, 0x1f, "JTAG" },
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]61 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
62 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
63 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
64 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
65 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
66 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
67 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]68#endif
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]69};
70
Graeme Russ9bf144c2015-01-25 12:07:53 +1100[diff] [blame]71#define MXS_BM_USB 0x00
72#define MXS_BM_I2C_MASTER_3V3 0x01
73#define MXS_BM_I2C_MASTER_1V8 0x11
74#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
75#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
76#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
77#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
78#define MXS_BM_NAND_3V3 0x04
79#define MXS_BM_NAND_1V8 0x14
80#define MXS_BM_JTAG 0x06
81#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
82#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
83#define MXS_BM_SDMMC0_3V3 0x09
84#define MXS_BM_SDMMC0_1V8 0x19
85#define MXS_BM_SDMMC1_3V3 0x0a
86#define MXS_BM_SDMMC1_1V8 0x1a
87
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]88#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_TEXT_BASE - 0x200))
Mans Rullgard2f66b402018-04-21 16:11:09 +0100[diff] [blame]89
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000[diff] [blame]90struct mxs_spl_data {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]91 uint8_t boot_mode_idx;
Marek Vasut9136fe92012-05-01 11:09:44 +0000[diff] [blame]92 uint32_t mem_dram_size;
93};
94
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000[diff] [blame]95int mxs_dram_init(void);
Fabio Estevam93f3a892011-12-20 05:46:33 +0000[diff] [blame]96
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]97#endif /* __SYS_PROTO_H__ */