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git01.mediatek.com / filogic / uboot / 4f2ef48dd80976c9798db7c01932f936d585e045 / . / arch / arm / include / asm / arch-mxs / sys_proto.h
blob: 062f3de1d05bfd4de1011762b55fbb6311c84fc9 [file] [log] [blame]
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]1/*
Otavio Salvadord8e90632012-08-19 04:58:28 +0000[diff] [blame]2 * Freescale i.MX23/i.MX28 specific functions
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]8 */
9
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]10#ifndef __SYS_PROTO_H__
11#define __SYS_PROTO_H__
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]12
Jeroen Hofstee4f2ef482014-10-08 22:57:50 +0200[diff] [blame^]13#include <asm/imx-common/regs-common.h>
14
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]15int mxs_reset_block(struct mxs_register_32 *reg);
16int mxs_wait_mask_set(struct mxs_register_32 *reg,
Robert Delienfb98d4a2012-02-26 12:15:05 +0000[diff] [blame]17 uint32_t mask,
fabio.estevam@freescale.com6815cf62012-08-22 10:10:11 +0000[diff] [blame]18 unsigned int timeout);
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]19int mxs_wait_mask_clr(struct mxs_register_32 *reg,
Robert Delienfb98d4a2012-02-26 12:15:05 +0000[diff] [blame]20 uint32_t mask,
fabio.estevam@freescale.com6815cf62012-08-22 10:10:11 +0000[diff] [blame]21 unsigned int timeout);
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]22
Marek Vasut722181e2013-01-22 15:01:03 +0000[diff] [blame]23int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000[diff] [blame]24
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]25#ifdef CONFIG_SPL_BUILD
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]26
27#if defined(CONFIG_MX23)
28#include <asm/arch/iomux-mx23.h>
29#elif defined(CONFIG_MX28)
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]30#include <asm/arch/iomux-mx28.h>
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]31#endif
32
Marek Vasut0dc62ba2013-08-31 15:53:44 +0200[diff] [blame]33void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
34 const iomux_cfg_t *iomux_setup,
35 const unsigned int iomux_size);
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]36#endif
37
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]38struct mxs_pair {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]39 uint8_t boot_pads;
40 uint8_t boot_mask;
41 const char *mode;
42};
43
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]44static const struct mxs_pair mxs_boot_modes[] = {
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]45#if defined(CONFIG_MX23)
46 { 0x00, 0x0f, "USB" },
47 { 0x01, 0x1f, "I2C, master" },
48 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
49 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
50 { 0x04, 0x1f, "NAND" },
Marek Vasutedc43b02013-09-20 01:36:44 +0200[diff] [blame]51 { 0x06, 0x1f, "JTAG" },
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]52 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
53 { 0x09, 0x1f, "SSP SD/MMC #0" },
54 { 0x0a, 0x1f, "SSP SD/MMC #1" },
55 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
56#elif defined(CONFIG_MX28)
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]57 { 0x00, 0x0f, "USB #0" },
58 { 0x01, 0x1f, "I2C #0, master, 3V3" },
59 { 0x11, 0x1f, "I2C #0, master, 1V8" },
60 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
61 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
62 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
63 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
64 { 0x04, 0x1f, "NAND, 3V3" },
65 { 0x14, 0x1f, "NAND, 1V8" },
Marek Vasutedc43b02013-09-20 01:36:44 +0200[diff] [blame]66 { 0x06, 0x1f, "JTAG" },
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]67 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
68 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
69 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
70 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
71 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
72 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
73 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame]74#endif
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]75};
76
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000[diff] [blame]77struct mxs_spl_data {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]78 uint8_t boot_mode_idx;
Marek Vasut9136fe92012-05-01 11:09:44 +0000[diff] [blame]79 uint32_t mem_dram_size;
80};
81
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000[diff] [blame]82int mxs_dram_init(void);
Fabio Estevam93f3a892011-12-20 05:46:33 +0000[diff] [blame]83
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]84#endif /* __SYS_PROTO_H__ */