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git01.mediatek.com / filogic / uboot / 2e0fac5c8e2cf27e6ba2ada2f30bc6d19d833d2b / . / arch / arm / include / asm / arch-mxs / sys_proto.h
blob: 8aaf196dfc8a80a1f01ce223be93d0e6ac4218a1 [file] [log] [blame]
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]1/*
Otavio Salvadord8e90632012-08-19 04:58:28 +0000[diff] [blame]2 * Freescale i.MX23/i.MX28 specific functions
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]23#ifndef __SYS_PROTO_H__
24#define __SYS_PROTO_H__
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]25
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]26int mxs_reset_block(struct mxs_register_32 *reg);
27int mxs_wait_mask_set(struct mxs_register_32 *reg,
Robert Delienfb98d4a2012-02-26 12:15:05 +0000[diff] [blame]28 uint32_t mask,
fabio.estevam@freescale.com6815cf62012-08-22 10:10:11 +0000[diff] [blame]29 unsigned int timeout);
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]30int mxs_wait_mask_clr(struct mxs_register_32 *reg,
Robert Delienfb98d4a2012-02-26 12:15:05 +0000[diff] [blame]31 uint32_t mask,
fabio.estevam@freescale.com6815cf62012-08-22 10:10:11 +0000[diff] [blame]32 unsigned int timeout);
Marek Vasutc140e982011-11-08 23:18:08 +0000[diff] [blame]33
Marek Vasutde0a6bf2011-11-08 23:18:09 +0000[diff] [blame]34int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
35
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]36#ifdef CONFIG_SPL_BUILD
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]37
38#if defined(CONFIG_MX23)
39#include <asm/arch/iomux-mx23.h>
40#elif defined(CONFIG_MX28)
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]41#include <asm/arch/iomux-mx28.h>
Otavio Salvador3038ae12013-01-11 03:19:05 +0000[diff] [blame]42#endif
43
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000[diff] [blame]44void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
Marek Vasut151f49d2011-12-02 03:47:40 +0000[diff] [blame]45 const unsigned int iomux_size);
46#endif
47
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]48struct mxs_pair {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]49 uint8_t boot_pads;
50 uint8_t boot_mask;
51 const char *mode;
52};
53
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]54static const struct mxs_pair mxs_boot_modes[] = {
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame^]55#if defined(CONFIG_MX23)
56 { 0x00, 0x0f, "USB" },
57 { 0x01, 0x1f, "I2C, master" },
58 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
59 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
60 { 0x04, 0x1f, "NAND" },
61 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
62 { 0x09, 0x1f, "SSP SD/MMC #0" },
63 { 0x0a, 0x1f, "SSP SD/MMC #1" },
64 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
65#elif defined(CONFIG_MX28)
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]66 { 0x00, 0x0f, "USB #0" },
67 { 0x01, 0x1f, "I2C #0, master, 3V3" },
68 { 0x11, 0x1f, "I2C #0, master, 1V8" },
69 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
70 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
71 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
72 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
73 { 0x04, 0x1f, "NAND, 3V3" },
74 { 0x14, 0x1f, "NAND, 1V8" },
75 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
76 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
77 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
78 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
79 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
80 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
81 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
Otavio Salvador2e0fac52013-01-11 03:19:09 +0000[diff] [blame^]82#endif
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]83};
84
Otavio Salvadorf930ea62012-08-05 09:05:32 +0000[diff] [blame]85struct mxs_spl_data {
Marek Vasutb28fe462012-05-01 11:09:45 +0000[diff] [blame]86 uint8_t boot_mode_idx;
Marek Vasut9136fe92012-05-01 11:09:44 +0000[diff] [blame]87 uint32_t mem_dram_size;
88};
89
Otavio Salvadora2bbe0c2012-08-19 04:58:30 +0000[diff] [blame]90int mxs_dram_init(void);
Fabio Estevam93f3a892011-12-20 05:46:33 +0000[diff] [blame]91
Otavio Salvadorcbf0bf22012-08-13 09:53:12 +0000[diff] [blame]92#endif /* __SYS_PROTO_H__ */