Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Altera SPI driver |
| 4 | * |
| 5 | * based on bfin_spi.c |
| 6 | * Copyright (c) 2005-2008 Analog Devices Inc. |
| 7 | * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 8 | */ |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 12 | #include <malloc.h> |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 13 | #include <fdtdec.h> |
Jagan Teki | a6f4875 | 2015-10-27 23:11:11 +0530 | [diff] [blame] | 14 | #include <spi.h> |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 15 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 17 | |
Jagan Teki | a6f4875 | 2015-10-27 23:11:11 +0530 | [diff] [blame] | 18 | #define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) |
| 19 | #define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) |
| 20 | |
Tom Rini | b0f0a21 | 2021-08-19 15:06:54 -0400 | [diff] [blame] | 21 | #define ALTERA_SPI_IDLE_VAL 0xff |
Marek Vasut | 7bb4fc3 | 2014-10-22 21:56:04 +0200 | [diff] [blame] | 22 | |
Marek Vasut | 4206602 | 2014-10-22 21:55:58 +0200 | [diff] [blame] | 23 | struct altera_spi_regs { |
| 24 | u32 rxdata; |
| 25 | u32 txdata; |
| 26 | u32 status; |
| 27 | u32 control; |
| 28 | u32 _reserved; |
| 29 | u32 slave_sel; |
| 30 | }; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 31 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 32 | struct altera_spi_plat { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 33 | struct altera_spi_regs *regs; |
| 34 | }; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 35 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 36 | struct altera_spi_priv { |
| 37 | struct altera_spi_regs *regs; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 38 | }; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 39 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 40 | static void spi_cs_activate(struct udevice *dev, uint cs) |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 41 | { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 42 | struct udevice *bus = dev->parent; |
| 43 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 44 | struct altera_spi_regs *const regs = priv->regs; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 45 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 46 | writel(1 << cs, ®s->slave_sel); |
| 47 | writel(ALTERA_SPI_CONTROL_SSO_MSK, ®s->control); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 48 | } |
| 49 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 50 | static void spi_cs_deactivate(struct udevice *dev) |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 51 | { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 52 | struct udevice *bus = dev->parent; |
| 53 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 54 | struct altera_spi_regs *const regs = priv->regs; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 55 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 56 | writel(0, ®s->control); |
| 57 | writel(0, ®s->slave_sel); |
Thomas Chou | 55be2b5 | 2010-12-27 09:30:17 +0800 | [diff] [blame] | 58 | } |
| 59 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 60 | static int altera_spi_claim_bus(struct udevice *dev) |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 61 | { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 62 | struct udevice *bus = dev->parent; |
| 63 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 64 | struct altera_spi_regs *const regs = priv->regs; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 65 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 66 | writel(0, ®s->control); |
| 67 | writel(0, ®s->slave_sel); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 68 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 69 | return 0; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 70 | } |
| 71 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 72 | static int altera_spi_release_bus(struct udevice *dev) |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 73 | { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 74 | struct udevice *bus = dev->parent; |
| 75 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 76 | struct altera_spi_regs *const regs = priv->regs; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 77 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 78 | writel(0, ®s->slave_sel); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 79 | |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 80 | return 0; |
| 81 | } |
| 82 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 83 | static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 84 | const void *dout, void *din, unsigned long flags) |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 85 | { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 86 | struct udevice *bus = dev->parent; |
| 87 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 88 | struct altera_spi_regs *const regs = priv->regs; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 89 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 90 | |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 91 | /* assume spi core configured to do 8 bit transfers */ |
Marek Vasut | 5c97e30 | 2014-10-22 21:56:02 +0200 | [diff] [blame] | 92 | unsigned int bytes = bitlen / 8; |
| 93 | const unsigned char *txp = dout; |
| 94 | unsigned char *rxp = din; |
| 95 | uint32_t reg, data, start; |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 96 | |
| 97 | debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, |
Simon Glass | 75e534b | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 98 | dev_seq(bus), slave_plat->cs, bitlen, bytes, flags); |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 99 | |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 100 | if (bitlen == 0) |
| 101 | goto done; |
| 102 | |
| 103 | if (bitlen % 8) { |
| 104 | flags |= SPI_XFER_END; |
| 105 | goto done; |
| 106 | } |
| 107 | |
| 108 | /* empty read buffer */ |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 109 | if (readl(®s->status) & ALTERA_SPI_STATUS_RRDY_MSK) |
| 110 | readl(®s->rxdata); |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 111 | |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 112 | if (flags & SPI_XFER_BEGIN) |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 113 | spi_cs_activate(dev, slave_plat->cs); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 114 | |
| 115 | while (bytes--) { |
Marek Vasut | 5c97e30 | 2014-10-22 21:56:02 +0200 | [diff] [blame] | 116 | if (txp) |
| 117 | data = *txp++; |
| 118 | else |
Tom Rini | b0f0a21 | 2021-08-19 15:06:54 -0400 | [diff] [blame] | 119 | data = ALTERA_SPI_IDLE_VAL; |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 120 | |
Marek Vasut | 5c97e30 | 2014-10-22 21:56:02 +0200 | [diff] [blame] | 121 | debug("%s: tx:%x ", __func__, data); |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 122 | writel(data, ®s->txdata); |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 123 | |
Marek Vasut | ec6938e | 2014-10-22 21:56:01 +0200 | [diff] [blame] | 124 | start = get_timer(0); |
| 125 | while (1) { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 126 | reg = readl(®s->status); |
Marek Vasut | ec6938e | 2014-10-22 21:56:01 +0200 | [diff] [blame] | 127 | if (reg & ALTERA_SPI_STATUS_RRDY_MSK) |
| 128 | break; |
| 129 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 130 | debug("%s: Transmission timed out!\n", __func__); |
| 131 | return -1; |
Marek Vasut | ec6938e | 2014-10-22 21:56:01 +0200 | [diff] [blame] | 132 | } |
| 133 | } |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 134 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 135 | data = readl(®s->rxdata); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 136 | if (rxp) |
Marek Vasut | 5c97e30 | 2014-10-22 21:56:02 +0200 | [diff] [blame] | 137 | *rxp++ = data & 0xff; |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 138 | |
Marek Vasut | 5c97e30 | 2014-10-22 21:56:02 +0200 | [diff] [blame] | 139 | debug("rx:%x\n", data); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 140 | } |
Marek Vasut | a49ffc3 | 2014-10-22 21:56:00 +0200 | [diff] [blame] | 141 | |
| 142 | done: |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 143 | if (flags & SPI_XFER_END) |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 144 | spi_cs_deactivate(dev); |
Thomas Chou | 3a673f1 | 2010-04-30 11:34:16 +0800 | [diff] [blame] | 145 | |
| 146 | return 0; |
| 147 | } |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 148 | |
| 149 | static int altera_spi_set_speed(struct udevice *bus, uint speed) |
| 150 | { |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static int altera_spi_set_mode(struct udevice *bus, uint mode) |
| 155 | { |
| 156 | return 0; |
| 157 | } |
| 158 | |
| 159 | static int altera_spi_probe(struct udevice *bus) |
| 160 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 161 | struct altera_spi_plat *plat = dev_get_plat(bus); |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 162 | struct altera_spi_priv *priv = dev_get_priv(bus); |
| 163 | |
| 164 | priv->regs = plat->regs; |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 169 | static int altera_spi_of_to_plat(struct udevice *bus) |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 170 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 171 | struct altera_spi_plat *plat = dev_get_plat(bus); |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 172 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 173 | plat->regs = map_physmem(dev_read_addr(bus), |
Thomas Chou | 3f1f1a2 | 2015-11-14 11:17:25 +0800 | [diff] [blame] | 174 | sizeof(struct altera_spi_regs), |
| 175 | MAP_NOCACHE); |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | static const struct dm_spi_ops altera_spi_ops = { |
| 181 | .claim_bus = altera_spi_claim_bus, |
| 182 | .release_bus = altera_spi_release_bus, |
| 183 | .xfer = altera_spi_xfer, |
| 184 | .set_speed = altera_spi_set_speed, |
| 185 | .set_mode = altera_spi_set_mode, |
| 186 | /* |
| 187 | * cs_info is not needed, since we require all chip selects to be |
| 188 | * in the device tree explicitly |
| 189 | */ |
| 190 | }; |
| 191 | |
| 192 | static const struct udevice_id altera_spi_ids[] = { |
Thomas Chou | ef4b350 | 2015-10-31 20:55:48 +0800 | [diff] [blame] | 193 | { .compatible = "altr,spi-1.0" }, |
| 194 | {} |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | U_BOOT_DRIVER(altera_spi) = { |
| 198 | .name = "altera_spi", |
| 199 | .id = UCLASS_SPI, |
| 200 | .of_match = altera_spi_ids, |
| 201 | .ops = &altera_spi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 202 | .of_to_plat = altera_spi_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 203 | .plat_auto = sizeof(struct altera_spi_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 204 | .priv_auto = sizeof(struct altera_spi_priv), |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 205 | .probe = altera_spi_probe, |
| 206 | }; |