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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Chou3a673f12010-04-30 11:34:16 +08002/*
3 * Altera SPI driver
4 *
5 * based on bfin_spi.c
6 * Copyright (c) 2005-2008 Analog Devices Inc.
7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
Thomas Chou3a673f12010-04-30 11:34:16 +08008 */
9#include <common.h>
Thomas Chouc5899542015-10-14 08:33:34 +080010#include <dm.h>
11#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Thomas Chou3a673f12010-04-30 11:34:16 +080013#include <malloc.h>
Thomas Chouc5899542015-10-14 08:33:34 +080014#include <fdtdec.h>
Jagan Tekia6f48752015-10-27 23:11:11 +053015#include <spi.h>
Thomas Chouc5899542015-10-14 08:33:34 +080016#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060017#include <linux/bitops.h>
Thomas Chouc5899542015-10-14 08:33:34 +080018
Jagan Tekia6f48752015-10-27 23:11:11 +053019#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
20#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
21
Marek Vasut7bb4fc32014-10-22 21:56:04 +020022#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
Jagan Tekia6f48752015-10-27 23:11:11 +053023#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
Marek Vasut7bb4fc32014-10-22 21:56:04 +020024#endif
25
Marek Vasut42066022014-10-22 21:55:58 +020026struct altera_spi_regs {
27 u32 rxdata;
28 u32 txdata;
29 u32 status;
30 u32 control;
31 u32 _reserved;
32 u32 slave_sel;
33};
Thomas Chou3a673f12010-04-30 11:34:16 +080034
Simon Glassb75b15b2020-12-03 16:55:23 -070035struct altera_spi_plat {
Thomas Chouc5899542015-10-14 08:33:34 +080036 struct altera_spi_regs *regs;
37};
Thomas Chou3a673f12010-04-30 11:34:16 +080038
Thomas Chouc5899542015-10-14 08:33:34 +080039struct altera_spi_priv {
40 struct altera_spi_regs *regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080041};
Thomas Chou3a673f12010-04-30 11:34:16 +080042
Thomas Chouc5899542015-10-14 08:33:34 +080043static void spi_cs_activate(struct udevice *dev, uint cs)
Thomas Chou3a673f12010-04-30 11:34:16 +080044{
Thomas Chouc5899542015-10-14 08:33:34 +080045 struct udevice *bus = dev->parent;
46 struct altera_spi_priv *priv = dev_get_priv(bus);
47 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080048
Thomas Chouc5899542015-10-14 08:33:34 +080049 writel(1 << cs, &regs->slave_sel);
50 writel(ALTERA_SPI_CONTROL_SSO_MSK, &regs->control);
Thomas Chou3a673f12010-04-30 11:34:16 +080051}
52
Thomas Chouc5899542015-10-14 08:33:34 +080053static void spi_cs_deactivate(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080054{
Thomas Chouc5899542015-10-14 08:33:34 +080055 struct udevice *bus = dev->parent;
56 struct altera_spi_priv *priv = dev_get_priv(bus);
57 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080058
Thomas Chouc5899542015-10-14 08:33:34 +080059 writel(0, &regs->control);
60 writel(0, &regs->slave_sel);
Thomas Chou55be2b52010-12-27 09:30:17 +080061}
62
Thomas Chouc5899542015-10-14 08:33:34 +080063static int altera_spi_claim_bus(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080064{
Thomas Chouc5899542015-10-14 08:33:34 +080065 struct udevice *bus = dev->parent;
66 struct altera_spi_priv *priv = dev_get_priv(bus);
67 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080068
Thomas Chouc5899542015-10-14 08:33:34 +080069 writel(0, &regs->control);
70 writel(0, &regs->slave_sel);
Thomas Chou3a673f12010-04-30 11:34:16 +080071
Thomas Chouc5899542015-10-14 08:33:34 +080072 return 0;
Thomas Chou3a673f12010-04-30 11:34:16 +080073}
74
Thomas Chouc5899542015-10-14 08:33:34 +080075static int altera_spi_release_bus(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080076{
Thomas Chouc5899542015-10-14 08:33:34 +080077 struct udevice *bus = dev->parent;
78 struct altera_spi_priv *priv = dev_get_priv(bus);
79 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080080
Thomas Chouc5899542015-10-14 08:33:34 +080081 writel(0, &regs->slave_sel);
Thomas Chou3a673f12010-04-30 11:34:16 +080082
Thomas Chou3a673f12010-04-30 11:34:16 +080083 return 0;
84}
85
Thomas Chouc5899542015-10-14 08:33:34 +080086static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen,
87 const void *dout, void *din, unsigned long flags)
Thomas Chou3a673f12010-04-30 11:34:16 +080088{
Thomas Chouc5899542015-10-14 08:33:34 +080089 struct udevice *bus = dev->parent;
90 struct altera_spi_priv *priv = dev_get_priv(bus);
91 struct altera_spi_regs *const regs = priv->regs;
Simon Glassb75b15b2020-12-03 16:55:23 -070092 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Thomas Chou3a673f12010-04-30 11:34:16 +080093
Thomas Chou3a673f12010-04-30 11:34:16 +080094 /* assume spi core configured to do 8 bit transfers */
Marek Vasut5c97e302014-10-22 21:56:02 +020095 unsigned int bytes = bitlen / 8;
96 const unsigned char *txp = dout;
97 unsigned char *rxp = din;
98 uint32_t reg, data, start;
Thomas Chou3a673f12010-04-30 11:34:16 +080099
100 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
Simon Glass75e534b2020-12-16 21:20:07 -0700101 dev_seq(bus), slave_plat->cs, bitlen, bytes, flags);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200102
Thomas Chou3a673f12010-04-30 11:34:16 +0800103 if (bitlen == 0)
104 goto done;
105
106 if (bitlen % 8) {
107 flags |= SPI_XFER_END;
108 goto done;
109 }
110
111 /* empty read buffer */
Thomas Chouc5899542015-10-14 08:33:34 +0800112 if (readl(&regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
113 readl(&regs->rxdata);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200114
Thomas Chou3a673f12010-04-30 11:34:16 +0800115 if (flags & SPI_XFER_BEGIN)
Thomas Chouc5899542015-10-14 08:33:34 +0800116 spi_cs_activate(dev, slave_plat->cs);
Thomas Chou3a673f12010-04-30 11:34:16 +0800117
118 while (bytes--) {
Marek Vasut5c97e302014-10-22 21:56:02 +0200119 if (txp)
120 data = *txp++;
121 else
122 data = CONFIG_ALTERA_SPI_IDLE_VAL;
Marek Vasuta49ffc32014-10-22 21:56:00 +0200123
Marek Vasut5c97e302014-10-22 21:56:02 +0200124 debug("%s: tx:%x ", __func__, data);
Thomas Chouc5899542015-10-14 08:33:34 +0800125 writel(data, &regs->txdata);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200126
Marek Vasutec6938e2014-10-22 21:56:01 +0200127 start = get_timer(0);
128 while (1) {
Thomas Chouc5899542015-10-14 08:33:34 +0800129 reg = readl(&regs->status);
Marek Vasutec6938e2014-10-22 21:56:01 +0200130 if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
131 break;
132 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
Thomas Chouc5899542015-10-14 08:33:34 +0800133 debug("%s: Transmission timed out!\n", __func__);
134 return -1;
Marek Vasutec6938e2014-10-22 21:56:01 +0200135 }
136 }
Marek Vasuta49ffc32014-10-22 21:56:00 +0200137
Thomas Chouc5899542015-10-14 08:33:34 +0800138 data = readl(&regs->rxdata);
Thomas Chou3a673f12010-04-30 11:34:16 +0800139 if (rxp)
Marek Vasut5c97e302014-10-22 21:56:02 +0200140 *rxp++ = data & 0xff;
Marek Vasuta49ffc32014-10-22 21:56:00 +0200141
Marek Vasut5c97e302014-10-22 21:56:02 +0200142 debug("rx:%x\n", data);
Thomas Chou3a673f12010-04-30 11:34:16 +0800143 }
Marek Vasuta49ffc32014-10-22 21:56:00 +0200144
145done:
Thomas Chou3a673f12010-04-30 11:34:16 +0800146 if (flags & SPI_XFER_END)
Thomas Chouc5899542015-10-14 08:33:34 +0800147 spi_cs_deactivate(dev);
Thomas Chou3a673f12010-04-30 11:34:16 +0800148
149 return 0;
150}
Thomas Chouc5899542015-10-14 08:33:34 +0800151
152static int altera_spi_set_speed(struct udevice *bus, uint speed)
153{
154 return 0;
155}
156
157static int altera_spi_set_mode(struct udevice *bus, uint mode)
158{
159 return 0;
160}
161
162static int altera_spi_probe(struct udevice *bus)
163{
Simon Glassb75b15b2020-12-03 16:55:23 -0700164 struct altera_spi_plat *plat = dev_get_plat(bus);
Thomas Chouc5899542015-10-14 08:33:34 +0800165 struct altera_spi_priv *priv = dev_get_priv(bus);
166
167 priv->regs = plat->regs;
168
169 return 0;
170}
171
Simon Glassaad29ae2020-12-03 16:55:21 -0700172static int altera_spi_of_to_plat(struct udevice *bus)
Thomas Chouc5899542015-10-14 08:33:34 +0800173{
Simon Glassb75b15b2020-12-03 16:55:23 -0700174 struct altera_spi_plat *plat = dev_get_plat(bus);
Thomas Chouc5899542015-10-14 08:33:34 +0800175
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900176 plat->regs = map_physmem(dev_read_addr(bus),
Thomas Chou3f1f1a22015-11-14 11:17:25 +0800177 sizeof(struct altera_spi_regs),
178 MAP_NOCACHE);
Thomas Chouc5899542015-10-14 08:33:34 +0800179
180 return 0;
181}
182
183static const struct dm_spi_ops altera_spi_ops = {
184 .claim_bus = altera_spi_claim_bus,
185 .release_bus = altera_spi_release_bus,
186 .xfer = altera_spi_xfer,
187 .set_speed = altera_spi_set_speed,
188 .set_mode = altera_spi_set_mode,
189 /*
190 * cs_info is not needed, since we require all chip selects to be
191 * in the device tree explicitly
192 */
193};
194
195static const struct udevice_id altera_spi_ids[] = {
Thomas Chouef4b3502015-10-31 20:55:48 +0800196 { .compatible = "altr,spi-1.0" },
197 {}
Thomas Chouc5899542015-10-14 08:33:34 +0800198};
199
200U_BOOT_DRIVER(altera_spi) = {
201 .name = "altera_spi",
202 .id = UCLASS_SPI,
203 .of_match = altera_spi_ids,
204 .ops = &altera_spi_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -0700205 .of_to_plat = altera_spi_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -0700206 .plat_auto = sizeof(struct altera_spi_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700207 .priv_auto = sizeof(struct altera_spi_priv),
Thomas Chouc5899542015-10-14 08:33:34 +0800208 .probe = altera_spi_probe,
209};