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git01.mediatek.com / filogic / uboot / a950f1a2eac1a1e6b534724412dbf3ff6d388bdb / . / arch / arm / include / asm / arch-tegra30 / pinmux.h
blob: 686417d5b3fcb9d57c766273331433314d5fecd9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]2/*
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]4 */
5
6#ifndef _TEGRA30_PINMUX_H_
7#define _TEGRA30_PINMUX_H_
8
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]9enum pmux_pingrp {
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]10 PMUX_PINGRP_ULPI_DATA0_PO1,
11 PMUX_PINGRP_ULPI_DATA1_PO2,
12 PMUX_PINGRP_ULPI_DATA2_PO3,
13 PMUX_PINGRP_ULPI_DATA3_PO4,
14 PMUX_PINGRP_ULPI_DATA4_PO5,
15 PMUX_PINGRP_ULPI_DATA5_PO6,
16 PMUX_PINGRP_ULPI_DATA6_PO7,
17 PMUX_PINGRP_ULPI_DATA7_PO0,
18 PMUX_PINGRP_ULPI_CLK_PY0,
19 PMUX_PINGRP_ULPI_DIR_PY1,
20 PMUX_PINGRP_ULPI_NXT_PY2,
21 PMUX_PINGRP_ULPI_STP_PY3,
22 PMUX_PINGRP_DAP3_FS_PP0,
23 PMUX_PINGRP_DAP3_DIN_PP1,
24 PMUX_PINGRP_DAP3_DOUT_PP2,
25 PMUX_PINGRP_DAP3_SCLK_PP3,
26 PMUX_PINGRP_PV0,
27 PMUX_PINGRP_PV1,
28 PMUX_PINGRP_SDMMC1_CLK_PZ0,
29 PMUX_PINGRP_SDMMC1_CMD_PZ1,
30 PMUX_PINGRP_SDMMC1_DAT3_PY4,
31 PMUX_PINGRP_SDMMC1_DAT2_PY5,
32 PMUX_PINGRP_SDMMC1_DAT1_PY6,
33 PMUX_PINGRP_SDMMC1_DAT0_PY7,
34 PMUX_PINGRP_PV2,
35 PMUX_PINGRP_PV3,
36 PMUX_PINGRP_CLK2_OUT_PW5,
37 PMUX_PINGRP_CLK2_REQ_PCC5,
38 PMUX_PINGRP_LCD_PWR1_PC1,
39 PMUX_PINGRP_LCD_PWR2_PC6,
40 PMUX_PINGRP_LCD_SDIN_PZ2,
41 PMUX_PINGRP_LCD_SDOUT_PN5,
42 PMUX_PINGRP_LCD_WR_N_PZ3,
43 PMUX_PINGRP_LCD_CS0_N_PN4,
44 PMUX_PINGRP_LCD_DC0_PN6,
45 PMUX_PINGRP_LCD_SCK_PZ4,
46 PMUX_PINGRP_LCD_PWR0_PB2,
47 PMUX_PINGRP_LCD_PCLK_PB3,
48 PMUX_PINGRP_LCD_DE_PJ1,
49 PMUX_PINGRP_LCD_HSYNC_PJ3,
50 PMUX_PINGRP_LCD_VSYNC_PJ4,
51 PMUX_PINGRP_LCD_D0_PE0,
52 PMUX_PINGRP_LCD_D1_PE1,
53 PMUX_PINGRP_LCD_D2_PE2,
54 PMUX_PINGRP_LCD_D3_PE3,
55 PMUX_PINGRP_LCD_D4_PE4,
56 PMUX_PINGRP_LCD_D5_PE5,
57 PMUX_PINGRP_LCD_D6_PE6,
58 PMUX_PINGRP_LCD_D7_PE7,
59 PMUX_PINGRP_LCD_D8_PF0,
60 PMUX_PINGRP_LCD_D9_PF1,
61 PMUX_PINGRP_LCD_D10_PF2,
62 PMUX_PINGRP_LCD_D11_PF3,
63 PMUX_PINGRP_LCD_D12_PF4,
64 PMUX_PINGRP_LCD_D13_PF5,
65 PMUX_PINGRP_LCD_D14_PF6,
66 PMUX_PINGRP_LCD_D15_PF7,
67 PMUX_PINGRP_LCD_D16_PM0,
68 PMUX_PINGRP_LCD_D17_PM1,
69 PMUX_PINGRP_LCD_D18_PM2,
70 PMUX_PINGRP_LCD_D19_PM3,
71 PMUX_PINGRP_LCD_D20_PM4,
72 PMUX_PINGRP_LCD_D21_PM5,
73 PMUX_PINGRP_LCD_D22_PM6,
74 PMUX_PINGRP_LCD_D23_PM7,
75 PMUX_PINGRP_LCD_CS1_N_PW0,
76 PMUX_PINGRP_LCD_M1_PW1,
77 PMUX_PINGRP_LCD_DC1_PD2,
78 PMUX_PINGRP_HDMI_INT_PN7,
79 PMUX_PINGRP_DDC_SCL_PV4,
80 PMUX_PINGRP_DDC_SDA_PV5,
81 PMUX_PINGRP_CRT_HSYNC_PV6,
82 PMUX_PINGRP_CRT_VSYNC_PV7,
83 PMUX_PINGRP_VI_D0_PT4,
84 PMUX_PINGRP_VI_D1_PD5,
85 PMUX_PINGRP_VI_D2_PL0,
86 PMUX_PINGRP_VI_D3_PL1,
87 PMUX_PINGRP_VI_D4_PL2,
88 PMUX_PINGRP_VI_D5_PL3,
89 PMUX_PINGRP_VI_D6_PL4,
90 PMUX_PINGRP_VI_D7_PL5,
91 PMUX_PINGRP_VI_D8_PL6,
92 PMUX_PINGRP_VI_D9_PL7,
93 PMUX_PINGRP_VI_D10_PT2,
94 PMUX_PINGRP_VI_D11_PT3,
95 PMUX_PINGRP_VI_PCLK_PT0,
96 PMUX_PINGRP_VI_MCLK_PT1,
97 PMUX_PINGRP_VI_VSYNC_PD6,
98 PMUX_PINGRP_VI_HSYNC_PD7,
99 PMUX_PINGRP_UART2_RXD_PC3,
100 PMUX_PINGRP_UART2_TXD_PC2,
101 PMUX_PINGRP_UART2_RTS_N_PJ6,
102 PMUX_PINGRP_UART2_CTS_N_PJ5,
103 PMUX_PINGRP_UART3_TXD_PW6,
104 PMUX_PINGRP_UART3_RXD_PW7,
105 PMUX_PINGRP_UART3_CTS_N_PA1,
106 PMUX_PINGRP_UART3_RTS_N_PC0,
107 PMUX_PINGRP_PU0,
108 PMUX_PINGRP_PU1,
109 PMUX_PINGRP_PU2,
110 PMUX_PINGRP_PU3,
111 PMUX_PINGRP_PU4,
112 PMUX_PINGRP_PU5,
113 PMUX_PINGRP_PU6,
114 PMUX_PINGRP_GEN1_I2C_SDA_PC5,
115 PMUX_PINGRP_GEN1_I2C_SCL_PC4,
116 PMUX_PINGRP_DAP4_FS_PP4,
117 PMUX_PINGRP_DAP4_DIN_PP5,
118 PMUX_PINGRP_DAP4_DOUT_PP6,
119 PMUX_PINGRP_DAP4_SCLK_PP7,
120 PMUX_PINGRP_CLK3_OUT_PEE0,
121 PMUX_PINGRP_CLK3_REQ_PEE1,
122 PMUX_PINGRP_GMI_WP_N_PC7,
123 PMUX_PINGRP_GMI_IORDY_PI5,
124 PMUX_PINGRP_GMI_WAIT_PI7,
125 PMUX_PINGRP_GMI_ADV_N_PK0,
126 PMUX_PINGRP_GMI_CLK_PK1,
127 PMUX_PINGRP_GMI_CS0_N_PJ0,
128 PMUX_PINGRP_GMI_CS1_N_PJ2,
129 PMUX_PINGRP_GMI_CS2_N_PK3,
130 PMUX_PINGRP_GMI_CS3_N_PK4,
131 PMUX_PINGRP_GMI_CS4_N_PK2,
132 PMUX_PINGRP_GMI_CS6_N_PI3,
133 PMUX_PINGRP_GMI_CS7_N_PI6,
134 PMUX_PINGRP_GMI_AD0_PG0,
135 PMUX_PINGRP_GMI_AD1_PG1,
136 PMUX_PINGRP_GMI_AD2_PG2,
137 PMUX_PINGRP_GMI_AD3_PG3,
138 PMUX_PINGRP_GMI_AD4_PG4,
139 PMUX_PINGRP_GMI_AD5_PG5,
140 PMUX_PINGRP_GMI_AD6_PG6,
141 PMUX_PINGRP_GMI_AD7_PG7,
142 PMUX_PINGRP_GMI_AD8_PH0,
143 PMUX_PINGRP_GMI_AD9_PH1,
144 PMUX_PINGRP_GMI_AD10_PH2,
145 PMUX_PINGRP_GMI_AD11_PH3,
146 PMUX_PINGRP_GMI_AD12_PH4,
147 PMUX_PINGRP_GMI_AD13_PH5,
148 PMUX_PINGRP_GMI_AD14_PH6,
149 PMUX_PINGRP_GMI_AD15_PH7,
150 PMUX_PINGRP_GMI_A16_PJ7,
151 PMUX_PINGRP_GMI_A17_PB0,
152 PMUX_PINGRP_GMI_A18_PB1,
153 PMUX_PINGRP_GMI_A19_PK7,
154 PMUX_PINGRP_GMI_WR_N_PI0,
155 PMUX_PINGRP_GMI_OE_N_PI1,
156 PMUX_PINGRP_GMI_DQS_PI2,
157 PMUX_PINGRP_GMI_RST_N_PI4,
158 PMUX_PINGRP_GEN2_I2C_SCL_PT5,
159 PMUX_PINGRP_GEN2_I2C_SDA_PT6,
160 PMUX_PINGRP_SDMMC4_CLK_PCC4,
161 PMUX_PINGRP_SDMMC4_CMD_PT7,
162 PMUX_PINGRP_SDMMC4_DAT0_PAA0,
163 PMUX_PINGRP_SDMMC4_DAT1_PAA1,
164 PMUX_PINGRP_SDMMC4_DAT2_PAA2,
165 PMUX_PINGRP_SDMMC4_DAT3_PAA3,
166 PMUX_PINGRP_SDMMC4_DAT4_PAA4,
167 PMUX_PINGRP_SDMMC4_DAT5_PAA5,
168 PMUX_PINGRP_SDMMC4_DAT6_PAA6,
169 PMUX_PINGRP_SDMMC4_DAT7_PAA7,
170 PMUX_PINGRP_SDMMC4_RST_N_PCC3,
171 PMUX_PINGRP_CAM_MCLK_PCC0,
172 PMUX_PINGRP_PCC1,
173 PMUX_PINGRP_PBB0,
174 PMUX_PINGRP_CAM_I2C_SCL_PBB1,
175 PMUX_PINGRP_CAM_I2C_SDA_PBB2,
176 PMUX_PINGRP_PBB3,
177 PMUX_PINGRP_PBB4,
178 PMUX_PINGRP_PBB5,
179 PMUX_PINGRP_PBB6,
180 PMUX_PINGRP_PBB7,
181 PMUX_PINGRP_PCC2,
182 PMUX_PINGRP_JTAG_RTCK_PU7,
183 PMUX_PINGRP_PWR_I2C_SCL_PZ6,
184 PMUX_PINGRP_PWR_I2C_SDA_PZ7,
185 PMUX_PINGRP_KB_ROW0_PR0,
186 PMUX_PINGRP_KB_ROW1_PR1,
187 PMUX_PINGRP_KB_ROW2_PR2,
188 PMUX_PINGRP_KB_ROW3_PR3,
189 PMUX_PINGRP_KB_ROW4_PR4,
190 PMUX_PINGRP_KB_ROW5_PR5,
191 PMUX_PINGRP_KB_ROW6_PR6,
192 PMUX_PINGRP_KB_ROW7_PR7,
193 PMUX_PINGRP_KB_ROW8_PS0,
194 PMUX_PINGRP_KB_ROW9_PS1,
195 PMUX_PINGRP_KB_ROW10_PS2,
196 PMUX_PINGRP_KB_ROW11_PS3,
197 PMUX_PINGRP_KB_ROW12_PS4,
198 PMUX_PINGRP_KB_ROW13_PS5,
199 PMUX_PINGRP_KB_ROW14_PS6,
200 PMUX_PINGRP_KB_ROW15_PS7,
201 PMUX_PINGRP_KB_COL0_PQ0,
202 PMUX_PINGRP_KB_COL1_PQ1,
203 PMUX_PINGRP_KB_COL2_PQ2,
204 PMUX_PINGRP_KB_COL3_PQ3,
205 PMUX_PINGRP_KB_COL4_PQ4,
206 PMUX_PINGRP_KB_COL5_PQ5,
207 PMUX_PINGRP_KB_COL6_PQ6,
208 PMUX_PINGRP_KB_COL7_PQ7,
209 PMUX_PINGRP_CLK_32K_OUT_PA0,
210 PMUX_PINGRP_SYS_CLK_REQ_PZ5,
211 PMUX_PINGRP_CORE_PWR_REQ,
212 PMUX_PINGRP_CPU_PWR_REQ,
213 PMUX_PINGRP_PWR_INT_N,
214 PMUX_PINGRP_CLK_32K_IN,
215 PMUX_PINGRP_OWR,
216 PMUX_PINGRP_DAP1_FS_PN0,
217 PMUX_PINGRP_DAP1_DIN_PN1,
218 PMUX_PINGRP_DAP1_DOUT_PN2,
219 PMUX_PINGRP_DAP1_SCLK_PN3,
220 PMUX_PINGRP_CLK1_REQ_PEE2,
221 PMUX_PINGRP_CLK1_OUT_PW4,
222 PMUX_PINGRP_SPDIF_IN_PK6,
223 PMUX_PINGRP_SPDIF_OUT_PK5,
224 PMUX_PINGRP_DAP2_FS_PA2,
225 PMUX_PINGRP_DAP2_DIN_PA4,
226 PMUX_PINGRP_DAP2_DOUT_PA5,
227 PMUX_PINGRP_DAP2_SCLK_PA3,
228 PMUX_PINGRP_SPI2_MOSI_PX0,
229 PMUX_PINGRP_SPI2_MISO_PX1,
230 PMUX_PINGRP_SPI2_CS0_N_PX3,
231 PMUX_PINGRP_SPI2_SCK_PX2,
232 PMUX_PINGRP_SPI1_MOSI_PX4,
233 PMUX_PINGRP_SPI1_SCK_PX5,
234 PMUX_PINGRP_SPI1_CS0_N_PX6,
235 PMUX_PINGRP_SPI1_MISO_PX7,
236 PMUX_PINGRP_SPI2_CS1_N_PW2,
237 PMUX_PINGRP_SPI2_CS2_N_PW3,
238 PMUX_PINGRP_SDMMC3_CLK_PA6,
239 PMUX_PINGRP_SDMMC3_CMD_PA7,
240 PMUX_PINGRP_SDMMC3_DAT0_PB7,
241 PMUX_PINGRP_SDMMC3_DAT1_PB6,
242 PMUX_PINGRP_SDMMC3_DAT2_PB5,
243 PMUX_PINGRP_SDMMC3_DAT3_PB4,
244 PMUX_PINGRP_SDMMC3_DAT4_PD1,
245 PMUX_PINGRP_SDMMC3_DAT5_PD0,
246 PMUX_PINGRP_SDMMC3_DAT6_PD3,
247 PMUX_PINGRP_SDMMC3_DAT7_PD4,
248 PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
249 PMUX_PINGRP_PEX_L0_RST_N_PDD1,
250 PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
251 PMUX_PINGRP_PEX_WAKE_N_PDD3,
252 PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
253 PMUX_PINGRP_PEX_L1_RST_N_PDD5,
254 PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
255 PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
256 PMUX_PINGRP_PEX_L2_RST_N_PCC6,
257 PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
258 PMUX_PINGRP_HDMI_CEC_PEE3,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]259 PMUX_PINGRP_COUNT,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]260};
261
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]262enum pmux_drvgrp {
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]263 PMUX_DRVGRP_AO1,
264 PMUX_DRVGRP_AO2,
265 PMUX_DRVGRP_AT1,
266 PMUX_DRVGRP_AT2,
267 PMUX_DRVGRP_AT3,
268 PMUX_DRVGRP_AT4,
269 PMUX_DRVGRP_AT5,
270 PMUX_DRVGRP_CDEV1,
271 PMUX_DRVGRP_CDEV2,
272 PMUX_DRVGRP_CSUS,
273 PMUX_DRVGRP_DAP1,
274 PMUX_DRVGRP_DAP2,
275 PMUX_DRVGRP_DAP3,
276 PMUX_DRVGRP_DAP4,
277 PMUX_DRVGRP_DBG,
278 PMUX_DRVGRP_LCD1,
279 PMUX_DRVGRP_LCD2,
280 PMUX_DRVGRP_SDIO2,
281 PMUX_DRVGRP_SDIO3,
282 PMUX_DRVGRP_SPI,
283 PMUX_DRVGRP_UAA,
284 PMUX_DRVGRP_UAB,
285 PMUX_DRVGRP_UART2,
286 PMUX_DRVGRP_UART3,
287 PMUX_DRVGRP_VI1,
288 PMUX_DRVGRP_SDIO1 = (0x84 / 4),
289 PMUX_DRVGRP_CRT = (0x90 / 4),
290 PMUX_DRVGRP_DDC,
291 PMUX_DRVGRP_GMA,
292 PMUX_DRVGRP_GMB,
293 PMUX_DRVGRP_GMC,
294 PMUX_DRVGRP_GMD,
295 PMUX_DRVGRP_GME,
296 PMUX_DRVGRP_GMF,
297 PMUX_DRVGRP_GMG,
298 PMUX_DRVGRP_GMH,
299 PMUX_DRVGRP_OWR,
300 PMUX_DRVGRP_UDA,
301 PMUX_DRVGRP_GPV,
302 PMUX_DRVGRP_DEV3,
303 PMUX_DRVGRP_CEC = (0xd0 / 4),
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]304 PMUX_DRVGRP_COUNT,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]305};
306
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]307enum pmux_func {
Stephen Warren7d9fae52014-04-22 14:37:52 -0600[diff] [blame]308 PMUX_FUNC_DEFAULT,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]309 PMUX_FUNC_BLINK,
310 PMUX_FUNC_CEC,
311 PMUX_FUNC_CLK_12M_OUT,
312 PMUX_FUNC_CLK_32K_IN,
313 PMUX_FUNC_CORE_PWR_REQ,
314 PMUX_FUNC_CPU_PWR_REQ,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]315 PMUX_FUNC_CRT,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]316 PMUX_FUNC_DAP,
317 PMUX_FUNC_DDR,
318 PMUX_FUNC_DEV3,
319 PMUX_FUNC_DISPLAYA,
320 PMUX_FUNC_DISPLAYB,
321 PMUX_FUNC_DTV,
322 PMUX_FUNC_EXTPERIPH1,
323 PMUX_FUNC_EXTPERIPH2,
324 PMUX_FUNC_EXTPERIPH3,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]325 PMUX_FUNC_GMI,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]326 PMUX_FUNC_GMI_ALT,
327 PMUX_FUNC_HDA,
328 PMUX_FUNC_HDCP,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]329 PMUX_FUNC_HDMI,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]330 PMUX_FUNC_HSI,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]331 PMUX_FUNC_I2C1,
332 PMUX_FUNC_I2C2,
333 PMUX_FUNC_I2C3,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]334 PMUX_FUNC_I2C4,
335 PMUX_FUNC_I2CPWR,
336 PMUX_FUNC_I2S0,
337 PMUX_FUNC_I2S1,
338 PMUX_FUNC_I2S2,
339 PMUX_FUNC_I2S3,
340 PMUX_FUNC_I2S4,
341 PMUX_FUNC_INVALID,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]342 PMUX_FUNC_KBC,
343 PMUX_FUNC_MIO,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]344 PMUX_FUNC_NAND,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]345 PMUX_FUNC_NAND_ALT,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]346 PMUX_FUNC_OWR,
347 PMUX_FUNC_PCIE,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]348 PMUX_FUNC_PWM0,
349 PMUX_FUNC_PWM1,
350 PMUX_FUNC_PWM2,
351 PMUX_FUNC_PWM3,
352 PMUX_FUNC_PWR_INT_N,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]353 PMUX_FUNC_RTCK,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]354 PMUX_FUNC_SATA,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]355 PMUX_FUNC_SDMMC1,
356 PMUX_FUNC_SDMMC2,
357 PMUX_FUNC_SDMMC3,
358 PMUX_FUNC_SDMMC4,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]359 PMUX_FUNC_SPDIF,
360 PMUX_FUNC_SPI1,
361 PMUX_FUNC_SPI2,
362 PMUX_FUNC_SPI2_ALT,
363 PMUX_FUNC_SPI3,
364 PMUX_FUNC_SPI4,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]365 PMUX_FUNC_SPI5,
366 PMUX_FUNC_SPI6,
367 PMUX_FUNC_SYSCLK,
368 PMUX_FUNC_TEST,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]369 PMUX_FUNC_TRACE,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]370 PMUX_FUNC_UARTA,
371 PMUX_FUNC_UARTB,
372 PMUX_FUNC_UARTC,
373 PMUX_FUNC_UARTD,
374 PMUX_FUNC_UARTE,
375 PMUX_FUNC_ULPI,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]376 PMUX_FUNC_VGP1,
377 PMUX_FUNC_VGP2,
378 PMUX_FUNC_VGP3,
379 PMUX_FUNC_VGP4,
380 PMUX_FUNC_VGP5,
381 PMUX_FUNC_VGP6,
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]382 PMUX_FUNC_VI,
383 PMUX_FUNC_VI_ALT1,
384 PMUX_FUNC_VI_ALT2,
385 PMUX_FUNC_VI_ALT3,
Stephen Warren70b080f2014-03-21 15:58:03 -0600[diff] [blame]386 PMUX_FUNC_RSVD1,
387 PMUX_FUNC_RSVD2,
388 PMUX_FUNC_RSVD3,
389 PMUX_FUNC_RSVD4,
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]390 PMUX_FUNC_COUNT,
Tom Warren13ac5442012-12-11 13:34:12 +0000[diff] [blame]391};
392
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200[diff] [blame]393static const char * const tegra_pinctrl_to_pingrp[] = {
394 [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
395 [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
396 [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
397 [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
398 [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
399 [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
400 [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
401 [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
402 [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
403 [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
404 [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
405 [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
406 [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
407 [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
408 [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
409 [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
410 [PMUX_PINGRP_PV0] = "pv0",
411 [PMUX_PINGRP_PV1] = "pv1",
412 [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
413 [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
414 [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
415 [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
416 [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
417 [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
418 [PMUX_PINGRP_PV2] = "pv2",
419 [PMUX_PINGRP_PV3] = "pv3",
420 [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
421 [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
422 [PMUX_PINGRP_LCD_PWR1_PC1] = "lcd_pwr1_pc1",
423 [PMUX_PINGRP_LCD_PWR2_PC6] = "lcd_pwr2_pc6",
424 [PMUX_PINGRP_LCD_SDIN_PZ2] = "lcd_sdin_pz2",
425 [PMUX_PINGRP_LCD_SDOUT_PN5] = "lcd_sdout_pn5",
426 [PMUX_PINGRP_LCD_WR_N_PZ3] = "lcd_wr_n_pz3",
427 [PMUX_PINGRP_LCD_CS0_N_PN4] = "lcd_cs0_n_pn4",
428 [PMUX_PINGRP_LCD_DC0_PN6] = "lcd_dc0_pn6",
429 [PMUX_PINGRP_LCD_SCK_PZ4] = "lcd_sck_pz4",
430 [PMUX_PINGRP_LCD_PWR0_PB2] = "lcd_pwr0_pb2",
431 [PMUX_PINGRP_LCD_PCLK_PB3] = "lcd_pclk_pb3",
432 [PMUX_PINGRP_LCD_DE_PJ1] = "lcd_de_pj1",
433 [PMUX_PINGRP_LCD_HSYNC_PJ3] = "lcd_hsync_pj3",
434 [PMUX_PINGRP_LCD_VSYNC_PJ4] = "lcd_vsync_pj4",
435 [PMUX_PINGRP_LCD_D0_PE0] = "lcd_d0_pe0",
436 [PMUX_PINGRP_LCD_D1_PE1] = "lcd_d1_pe1",
437 [PMUX_PINGRP_LCD_D2_PE2] = "lcd_d2_pe2",
438 [PMUX_PINGRP_LCD_D3_PE3] = "lcd_d3_pe3",
439 [PMUX_PINGRP_LCD_D4_PE4] = "lcd_d4_pe4",
440 [PMUX_PINGRP_LCD_D5_PE5] = "lcd_d5_pe5",
441 [PMUX_PINGRP_LCD_D6_PE6] = "lcd_d6_pe6",
442 [PMUX_PINGRP_LCD_D7_PE7] = "lcd_d7_pe7",
443 [PMUX_PINGRP_LCD_D8_PF0] = "lcd_d8_pf0",
444 [PMUX_PINGRP_LCD_D9_PF1] = "lcd_d9_pf1",
445 [PMUX_PINGRP_LCD_D10_PF2] = "lcd_d10_pf2",
446 [PMUX_PINGRP_LCD_D11_PF3] = "lcd_d11_pf3",
447 [PMUX_PINGRP_LCD_D12_PF4] = "lcd_d12_pf4",
448 [PMUX_PINGRP_LCD_D13_PF5] = "lcd_d13_pf5",
449 [PMUX_PINGRP_LCD_D14_PF6] = "lcd_d14_pf6",
450 [PMUX_PINGRP_LCD_D15_PF7] = "lcd_d15_pf7",
451 [PMUX_PINGRP_LCD_D16_PM0] = "lcd_d16_pm0",
452 [PMUX_PINGRP_LCD_D17_PM1] = "lcd_d17_pm1",
453 [PMUX_PINGRP_LCD_D18_PM2] = "lcd_d18_pm2",
454 [PMUX_PINGRP_LCD_D19_PM3] = "lcd_d19_pm3",
455 [PMUX_PINGRP_LCD_D20_PM4] = "lcd_d20_pm4",
456 [PMUX_PINGRP_LCD_D21_PM5] = "lcd_d21_pm5",
457 [PMUX_PINGRP_LCD_D22_PM6] = "lcd_d22_pm6",
458 [PMUX_PINGRP_LCD_D23_PM7] = "lcd_d23_pm7",
459 [PMUX_PINGRP_LCD_CS1_N_PW0] = "lcd_cs1_n_pw0",
460 [PMUX_PINGRP_LCD_M1_PW1] = "lcd_m1_pw1",
461 [PMUX_PINGRP_LCD_DC1_PD2] = "lcd_dc1_pd2",
462 [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
463 [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
464 [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
465 [PMUX_PINGRP_CRT_HSYNC_PV6] = "crt_hsync_pv6",
466 [PMUX_PINGRP_CRT_VSYNC_PV7] = "crt_vsync_pv7",
467 [PMUX_PINGRP_VI_D0_PT4] = "vi_d0_pt4",
468 [PMUX_PINGRP_VI_D1_PD5] = "vi_d1_pd5",
469 [PMUX_PINGRP_VI_D2_PL0] = "vi_d2_pl0",
470 [PMUX_PINGRP_VI_D3_PL1] = "vi_d3_pl1",
471 [PMUX_PINGRP_VI_D4_PL2] = "vi_d4_pl2",
472 [PMUX_PINGRP_VI_D5_PL3] = "vi_d5_pl3",
473 [PMUX_PINGRP_VI_D6_PL4] = "vi_d6_pl4",
474 [PMUX_PINGRP_VI_D7_PL5] = "vi_d7_pl5",
475 [PMUX_PINGRP_VI_D8_PL6] = "vi_d8_pl6",
476 [PMUX_PINGRP_VI_D9_PL7] = "vi_d9_pl7",
477 [PMUX_PINGRP_VI_D10_PT2] = "vi_d10_pt2",
478 [PMUX_PINGRP_VI_D11_PT3] = "vi_d11_pt3",
479 [PMUX_PINGRP_VI_PCLK_PT0] = "vi_pclk_pt0",
480 [PMUX_PINGRP_VI_MCLK_PT1] = "vi_mclk_pt1",
481 [PMUX_PINGRP_VI_VSYNC_PD6] = "vi_vsync_pd6",
482 [PMUX_PINGRP_VI_HSYNC_PD7] = "vi_hsync_pd7",
483 [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
484 [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
485 [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
486 [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
487 [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
488 [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
489 [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
490 [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
491 [PMUX_PINGRP_PU0] = "pu0",
492 [PMUX_PINGRP_PU1] = "pu1",
493 [PMUX_PINGRP_PU2] = "pu2",
494 [PMUX_PINGRP_PU3] = "pu3",
495 [PMUX_PINGRP_PU4] = "pu4",
496 [PMUX_PINGRP_PU5] = "pu5",
497 [PMUX_PINGRP_PU6] = "pu6",
498 [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
499 [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
500 [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
501 [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
502 [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
503 [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
504 [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
505 [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
506 [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7",
507 [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5",
508 [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7",
509 [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0",
510 [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1",
511 [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0",
512 [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2",
513 [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3",
514 [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4",
515 [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2",
516 [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3",
517 [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6",
518 [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0",
519 [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1",
520 [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2",
521 [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3",
522 [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4",
523 [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5",
524 [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6",
525 [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7",
526 [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0",
527 [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1",
528 [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2",
529 [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3",
530 [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4",
531 [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5",
532 [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6",
533 [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7",
534 [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7",
535 [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0",
536 [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1",
537 [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7",
538 [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0",
539 [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1",
540 [PMUX_PINGRP_GMI_DQS_PI2] = "gmi_dqs_pi2",
541 [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4",
542 [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
543 [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
544 [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
545 [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
546 [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
547 [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
548 [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
549 [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
550 [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
551 [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
552 [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
553 [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
554 [PMUX_PINGRP_SDMMC4_RST_N_PCC3] = "sdmmc4_rst_n_pcc3",
555 [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
556 [PMUX_PINGRP_PCC1] = "pcc1",
557 [PMUX_PINGRP_PBB0] = "pbb0",
558 [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
559 [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
560 [PMUX_PINGRP_PBB3] = "pbb3",
561 [PMUX_PINGRP_PBB4] = "pbb4",
562 [PMUX_PINGRP_PBB5] = "pbb5",
563 [PMUX_PINGRP_PBB6] = "pbb6",
564 [PMUX_PINGRP_PBB7] = "pbb7",
565 [PMUX_PINGRP_PCC2] = "pcc2",
566 [PMUX_PINGRP_JTAG_RTCK_PU7] = "jtag_rtck_pu7",
567 [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
568 [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
569 [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
570 [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
571 [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
572 [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
573 [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
574 [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
575 [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
576 [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
577 [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
578 [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
579 [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
580 [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
581 [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
582 [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
583 [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
584 [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
585 [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
586 [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
587 [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
588 [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
589 [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
590 [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
591 [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
592 [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
593 [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
594 [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5",
595 [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
596 [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
597 [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
598 [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
599 [PMUX_PINGRP_OWR] = "owr",
600 [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
601 [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
602 [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
603 [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
604 [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2",
605 [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4",
606 [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
607 [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
608 [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
609 [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
610 [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
611 [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
612 [PMUX_PINGRP_SPI2_MOSI_PX0] = "spi2_mosi_px0",
613 [PMUX_PINGRP_SPI2_MISO_PX1] = "spi2_miso_px1",
614 [PMUX_PINGRP_SPI2_CS0_N_PX3] = "spi2_cs0_n_px3",
615 [PMUX_PINGRP_SPI2_SCK_PX2] = "spi2_sck_px2",
616 [PMUX_PINGRP_SPI1_MOSI_PX4] = "spi1_mosi_px4",
617 [PMUX_PINGRP_SPI1_SCK_PX5] = "spi1_sck_px5",
618 [PMUX_PINGRP_SPI1_CS0_N_PX6] = "spi1_cs0_n_px6",
619 [PMUX_PINGRP_SPI1_MISO_PX7] = "spi1_miso_px7",
620 [PMUX_PINGRP_SPI2_CS1_N_PW2] = "spi2_cs1_n_pw2",
621 [PMUX_PINGRP_SPI2_CS2_N_PW3] = "spi2_cs2_n_pw3",
622 [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
623 [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
624 [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
625 [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
626 [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
627 [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
628 [PMUX_PINGRP_SDMMC3_DAT4_PD1] = "sdmmc3_dat4_pd1",
629 [PMUX_PINGRP_SDMMC3_DAT5_PD0] = "sdmmc3_dat5_pd0",
630 [PMUX_PINGRP_SDMMC3_DAT6_PD3] = "sdmmc3_dat6_pd3",
631 [PMUX_PINGRP_SDMMC3_DAT7_PD4] = "sdmmc3_dat7_pd4",
632 [PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0] = "pex_l0_prsnt_n_pdd0",
633 [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
634 [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
635 [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
636 [PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4] = "pex_l1_prsnt_n_pdd4",
637 [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
638 [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
639 [PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7] = "pex_l2_prsnt_n_pdd7",
640 [PMUX_PINGRP_PEX_L2_RST_N_PCC6] = "pex_l2_rst_n_pcc6",
641 [PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7] = "pex_l2_clkreq_n_pcc7",
642 [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
643};
644
645static const char * const tegra_pinctrl_to_drvgrp[] = {
646 [PMUX_DRVGRP_AO1] = "drive_ao1",
647 [PMUX_DRVGRP_AO2] = "drive_ao2",
648 [PMUX_DRVGRP_AT1] = "drive_at1",
649 [PMUX_DRVGRP_AT2] = "drive_at2",
650 [PMUX_DRVGRP_AT3] = "drive_at3",
651 [PMUX_DRVGRP_AT4] = "drive_at4",
652 [PMUX_DRVGRP_AT5] = "drive_at5",
653 [PMUX_DRVGRP_CDEV1] = "drive_cdev1",
654 [PMUX_DRVGRP_CDEV2] = "drive_cdev2",
655 [PMUX_DRVGRP_CSUS] = "drive_csus",
656 [PMUX_DRVGRP_DAP1] = "drive_dap1",
657 [PMUX_DRVGRP_DAP2] = "drive_dap2",
658 [PMUX_DRVGRP_DAP3] = "drive_dap3",
659 [PMUX_DRVGRP_DAP4] = "drive_dap4",
660 [PMUX_DRVGRP_DBG] = "drive_dbg",
661 [PMUX_DRVGRP_LCD1] = "drive_lcd1",
662 [PMUX_DRVGRP_LCD2] = "drive_lcd2",
663 [PMUX_DRVGRP_SDIO2] = "drive_sdio2",
664 [PMUX_DRVGRP_SDIO3] = "drive_sdio3",
665 [PMUX_DRVGRP_SPI] = "drive_spi",
666 [PMUX_DRVGRP_UAA] = "drive_uaa",
667 [PMUX_DRVGRP_UAB] = "drive_uab",
668 [PMUX_DRVGRP_UART2] = "drive_uart2",
669 [PMUX_DRVGRP_UART3] = "drive_uart3",
670 [PMUX_DRVGRP_VI1] = "drive_vi1",
671 [PMUX_DRVGRP_SDIO1] = "drive_sdio1",
672 [PMUX_DRVGRP_CRT] = "drive_crt",
673 [PMUX_DRVGRP_DDC] = "drive_ddc",
674 [PMUX_DRVGRP_GMA] = "drive_gma",
675 [PMUX_DRVGRP_GMB] = "drive_gmb",
676 [PMUX_DRVGRP_GMC] = "drive_gmc",
677 [PMUX_DRVGRP_GMD] = "drive_gmd",
678 [PMUX_DRVGRP_GME] = "drive_gme",
679 [PMUX_DRVGRP_GMF] = "drive_gmf",
680 [PMUX_DRVGRP_GMG] = "drive_gmg",
681 [PMUX_DRVGRP_GMH] = "drive_gmh",
682 [PMUX_DRVGRP_OWR] = "drive_owr",
683 [PMUX_DRVGRP_UDA] = "drive_uda",
684 [PMUX_DRVGRP_GPV] = "drive_gpv",
685 [PMUX_DRVGRP_DEV3] = "drive_dev3",
686 [PMUX_DRVGRP_CEC] = "drive_cec",
687};
688
689static const char * const tegra_pinctrl_to_func[] = {
690 [PMUX_FUNC_DEFAULT] = "default",
691 [PMUX_FUNC_BLINK] = "blink",
692 [PMUX_FUNC_CEC] = "cec",
693 [PMUX_FUNC_CLK_12M_OUT] = "clk_12m_out",
694 [PMUX_FUNC_CLK_32K_IN] = "clk_32k_in",
695 [PMUX_FUNC_CORE_PWR_REQ] = "core_pwr_req",
696 [PMUX_FUNC_CPU_PWR_REQ] = "cpu_pwr_req",
697 [PMUX_FUNC_CRT] = "crt",
698 [PMUX_FUNC_DAP] = "dap",
699 [PMUX_FUNC_DDR] = "ddr",
700 [PMUX_FUNC_DEV3] = "dev3",
701 [PMUX_FUNC_DISPLAYA] = "displaya",
702 [PMUX_FUNC_DISPLAYB] = "displayb",
703 [PMUX_FUNC_DTV] = "dtv",
704 [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
705 [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
706 [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
707 [PMUX_FUNC_GMI] = "gmi",
708 [PMUX_FUNC_GMI_ALT] = "gmi_alt",
709 [PMUX_FUNC_HDA] = "hda",
710 [PMUX_FUNC_HDCP] = "hdcp",
711 [PMUX_FUNC_HDMI] = "hdmi",
712 [PMUX_FUNC_HSI] = "hsi",
713 [PMUX_FUNC_I2C1] = "i2c1",
714 [PMUX_FUNC_I2C2] = "i2c2",
715 [PMUX_FUNC_I2C3] = "i2c3",
716 [PMUX_FUNC_I2C4] = "i2c4",
717 [PMUX_FUNC_I2CPWR] = "i2cpwr",
718 [PMUX_FUNC_I2S0] = "i2s0",
719 [PMUX_FUNC_I2S1] = "i2s1",
720 [PMUX_FUNC_I2S2] = "i2s2",
721 [PMUX_FUNC_I2S3] = "i2s3",
722 [PMUX_FUNC_I2S4] = "i2s4",
723 [PMUX_FUNC_INVALID] = "invalid",
724 [PMUX_FUNC_KBC] = "kbc",
725 [PMUX_FUNC_MIO] = "mio",
726 [PMUX_FUNC_NAND] = "nand",
727 [PMUX_FUNC_NAND_ALT] = "nand_alt",
728 [PMUX_FUNC_OWR] = "owr",
729 [PMUX_FUNC_PCIE] = "pcie",
730 [PMUX_FUNC_PWM0] = "pwm0",
731 [PMUX_FUNC_PWM1] = "pwm1",
732 [PMUX_FUNC_PWM2] = "pwm2",
733 [PMUX_FUNC_PWM3] = "pwm3",
734 [PMUX_FUNC_PWR_INT_N] = "pwr_int_n",
735 [PMUX_FUNC_RTCK] = "rtck",
736 [PMUX_FUNC_SATA] = "sata",
737 [PMUX_FUNC_SDMMC1] = "sdmmc1",
738 [PMUX_FUNC_SDMMC2] = "sdmmc2",
739 [PMUX_FUNC_SDMMC3] = "sdmmc3",
740 [PMUX_FUNC_SDMMC4] = "sdmmc4",
741 [PMUX_FUNC_SPDIF] = "spdif",
742 [PMUX_FUNC_SPI1] = "spi1",
743 [PMUX_FUNC_SPI2] = "spi2",
744 [PMUX_FUNC_SPI2_ALT] = "spi2_alt",
745 [PMUX_FUNC_SPI3] = "spi3",
746 [PMUX_FUNC_SPI4] = "spi4",
747 [PMUX_FUNC_SPI5] = "spi5",
748 [PMUX_FUNC_SPI6] = "spi6",
749 [PMUX_FUNC_SYSCLK] = "sysclk",
750 [PMUX_FUNC_TEST] = "test",
751 [PMUX_FUNC_TRACE] = "trace",
752 [PMUX_FUNC_UARTA] = "uarta",
753 [PMUX_FUNC_UARTB] = "uartb",
754 [PMUX_FUNC_UARTC] = "uartc",
755 [PMUX_FUNC_UARTD] = "uartd",
756 [PMUX_FUNC_UARTE] = "uarte",
757 [PMUX_FUNC_ULPI] = "ulpi",
758 [PMUX_FUNC_VGP1] = "vgp1",
759 [PMUX_FUNC_VGP2] = "vgp2",
760 [PMUX_FUNC_VGP3] = "vgp3",
761 [PMUX_FUNC_VGP4] = "vgp4",
762 [PMUX_FUNC_VGP5] = "vgp5",
763 [PMUX_FUNC_VGP6] = "vgp6",
764 [PMUX_FUNC_VI] = "vi",
765 [PMUX_FUNC_VI_ALT1] = "vi_alt1",
766 [PMUX_FUNC_VI_ALT2] = "vi_alt2",
767 [PMUX_FUNC_VI_ALT3] = "vi_alt3",
768 [PMUX_FUNC_RSVD1] = "rsvd1",
769 [PMUX_FUNC_RSVD2] = "rsvd2",
770 [PMUX_FUNC_RSVD3] = "rsvd3",
771 [PMUX_FUNC_RSVD4] = "rsvd4",
772};
773
Stephen Warren51f9e722015-02-24 14:08:29 -0700[diff] [blame]774#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]775#define TEGRA_PMX_SOC_HAS_DRVGRPS
Stephen Warren3e9fb7b2015-02-24 14:08:25 -0700[diff] [blame]776#define TEGRA_PMX_GRPS_HAVE_LPMD
777#define TEGRA_PMX_GRPS_HAVE_SCHMT
778#define TEGRA_PMX_GRPS_HAVE_HSM
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]779#define TEGRA_PMX_PINS_HAVE_E_INPUT
780#define TEGRA_PMX_PINS_HAVE_LOCK
781#define TEGRA_PMX_PINS_HAVE_OD
782#define TEGRA_PMX_PINS_HAVE_IO_RESET
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]783#include <asm/arch-tegra/pinmux.h>
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]784
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]785#endif /* _TEGRA30_PINMUX_H_ */