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git01.mediatek.com / filogic / uboot / a856b1a4731480ce08993496d2584b9520aed0f7 / . / arch / arm / dts / rk3588s-u-boot.dtsi
blob: cd7e6cb50ee2413c72dc1cc88f3ad07a962fd591 [file] [log] [blame]
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9 dmc {
10 compatible = "rockchip,rk3588-dmc";
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]11 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]12 status = "okay";
13 };
14
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame^]15 usb_host0_ehci: usb@fc800000 {
16 compatible = "generic-ehci";
17 reg = <0x0 0xfc800000 0x0 0x40000>;
18 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
19 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
20 clock-names = "usbhost", "arbiter";
21 power-domains = <&power RK3588_PD_USB>;
22 status = "disabled";
23 };
24
25 usb_host0_ohci: usb@fc840000 {
26 compatible = "generic-ohci";
27 reg = <0x0 0xfc840000 0x0 0x40000>;
28 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
29 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
30 clock-names = "usbhost", "arbiter";
31 power-domains = <&power RK3588_PD_USB>;
32 status = "disabled";
33 };
34
35 usb_host1_ehci: usb@fc880000 {
36 compatible = "generic-ehci";
37 reg = <0x0 0xfc880000 0x0 0x40000>;
38 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
39 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
40 clock-names = "usbhost", "arbiter";
41 power-domains = <&power RK3588_PD_USB>;
42 status = "disabled";
43 };
44
45 usb_host1_ohci: usb@fc8c0000 {
46 compatible = "generic-ohci";
47 reg = <0x0 0xfc8c0000 0x0 0x40000>;
48 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
49 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
50 clock-names = "usbhost", "arbiter";
51 power-domains = <&power RK3588_PD_USB>;
52 status = "disabled";
53 };
54
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]55 pmu1_grf: syscon@fd58a000 {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]56 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]57 compatible = "rockchip,rk3588-pmu1-grf", "syscon";
58 reg = <0x0 0xfd58a000 0x0 0x2000>;
59 };
Jagan Teki275d8512023-01-30 20:27:47 +0530[diff] [blame]60
Eugen Hristeva856b1a2023-05-15 12:59:45 +0300[diff] [blame^]61 usb2phy2_grf: syscon@fd5d8000 {
62 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
63 "simple-mfd";
64 reg = <0x0 0xfd5d8000 0x0 0x4000>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67
68 u2phy2: usb2-phy@8000 {
69 compatible = "rockchip,rk3588-usb2phy";
70 reg = <0x8000 0x10>;
71 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
72 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
73 clock-names = "phyclk";
74 #clock-cells = <0>;
75 status = "disabled";
76
77 u2phy2_host: host-port {
78 #phy-cells = <0>;
79 status = "disabled";
80 };
81 };
82 };
83
84 usb2phy3_grf: syscon@fd5dc000 {
85 compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
86 "simple-mfd";
87 reg = <0x0 0xfd5dc000 0x0 0x4000>;
88 #address-cells = <1>;
89 #size-cells = <1>;
90
91 u2phy3: usb2-phy@c000 {
92 compatible = "rockchip,rk3588-usb2phy";
93 reg = <0xc000 0x10>;
94 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
96 clock-names = "phyclk";
97 #clock-cells = <0>;
98 status = "disabled";
99
100 u2phy3_host: host-port {
101 #phy-cells = <0>;
102 status = "disabled";
103 };
104 };
105 };
106
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000[diff] [blame]107 otp: nvmem@fecc0000 {
108 compatible = "rockchip,rk3588-otp";
109 reg = <0x0 0xfecc0000 0x0 0x400>;
110 #address-cells = <1>;
111 #size-cells = <1>;
112 status = "okay";
113
114 cpu_id: id@7 {
115 reg = <0x07 0x10>;
116 };
117 };
Chris Morgan7f255042023-04-13 09:13:03 -0500[diff] [blame]118
119 rng: rng@fe378000 {
120 compatible = "rockchip,trngv1";
121 reg = <0x0 0xfe378000 0x0 0x200>;
122 status = "disabled";
123 };
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]124};
125
126&xin24m {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]127 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]128 status = "okay";
129};
130
131&cru {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]132 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]133 status = "okay";
134};
135
136&sys_grf {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]137 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]138 status = "okay";
139};
140
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000[diff] [blame]141&scmi {
142 bootph-pre-ram;
143};
144
145&scmi_clk {
146 bootph-pre-ram;
147};
148
149&sdmmc {
150 bootph-pre-ram;
151 u-boot,spl-fifo-mode;
152};
153
Jonas Karlmanced8be02023-04-18 16:46:41 +0000[diff] [blame]154&sdhci {
155 bootph-pre-ram;
156};
157
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]158&uart2 {
159 clock-frequency = <24000000>;
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]160 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]161 status = "okay";
162};
163
164&ioc {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]165 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]166};