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git01.mediatek.com / filogic / uboot / c38e6d4240af930c52f7b60391626eb9dadbe821 / . / arch / arm / dts / rk3588s-u-boot.dtsi
blob: 5201ba246d87e441f3290fb01da0947c084f553c [file] [log] [blame]
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9 dmc {
10 compatible = "rockchip,rk3588-dmc";
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]11 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]12 status = "okay";
13 };
14
15 pmu1_grf: syscon@fd58a000 {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]16 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]17 compatible = "rockchip,rk3588-pmu1-grf", "syscon";
18 reg = <0x0 0xfd58a000 0x0 0x2000>;
19 };
Jagan Teki275d8512023-01-30 20:27:47 +0530[diff] [blame]20
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000[diff] [blame]21 otp: nvmem@fecc0000 {
22 compatible = "rockchip,rk3588-otp";
23 reg = <0x0 0xfecc0000 0x0 0x400>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 status = "okay";
27
28 cpu_id: id@7 {
29 reg = <0x07 0x10>;
30 };
31 };
Chris Morgan7f255042023-04-13 09:13:03 -0500[diff] [blame]32
33 rng: rng@fe378000 {
34 compatible = "rockchip,trngv1";
35 reg = <0x0 0xfe378000 0x0 0x200>;
36 status = "disabled";
37 };
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]38};
39
40&xin24m {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]41 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]42 status = "okay";
43};
44
45&cru {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]46 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]47 status = "okay";
48};
49
50&sys_grf {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]51 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]52 status = "okay";
53};
54
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000[diff] [blame]55&scmi {
56 bootph-pre-ram;
57};
58
59&scmi_clk {
60 bootph-pre-ram;
61};
62
63&sdmmc {
64 bootph-pre-ram;
65 u-boot,spl-fifo-mode;
66};
67
Jonas Karlmanced8be02023-04-18 16:46:41 +0000[diff] [blame]68&sdhci {
69 bootph-pre-ram;
70};
71
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]72&uart2 {
73 clock-frequency = <24000000>;
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]74 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]75 status = "okay";
76};
77
78&ioc {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]79 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]80};