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git01.mediatek.com / filogic / uboot / fc805c2d88fc0bbe52837ae7c0f258a963e5fe47 / . / arch / arm / dts / rk3588s-u-boot.dtsi
blob: 3cb22f35420e7cbe87e4186a7fe2b1ed945074fa [file] [log] [blame]
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include "rockchip-u-boot.dtsi"
7
8/ {
9 dmc {
10 compatible = "rockchip,rk3588-dmc";
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]11 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]12 status = "okay";
13 };
14
15 pmu1_grf: syscon@fd58a000 {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]16 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]17 compatible = "rockchip,rk3588-pmu1-grf", "syscon";
18 reg = <0x0 0xfd58a000 0x0 0x2000>;
19 };
Jagan Teki275d8512023-01-30 20:27:47 +0530[diff] [blame]20
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000[diff] [blame]21 otp: nvmem@fecc0000 {
22 compatible = "rockchip,rk3588-otp";
23 reg = <0x0 0xfecc0000 0x0 0x400>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 status = "okay";
27
28 cpu_id: id@7 {
29 reg = <0x07 0x10>;
30 };
31 };
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]32};
33
34&xin24m {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]35 bootph-all;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]36 status = "okay";
37};
38
39&cru {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]40 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]41 status = "okay";
42};
43
44&sys_grf {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]45 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]46 status = "okay";
47};
48
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000[diff] [blame^]49&scmi {
50 bootph-pre-ram;
51};
52
53&scmi_clk {
54 bootph-pre-ram;
55};
56
57&sdmmc {
58 bootph-pre-ram;
59 u-boot,spl-fifo-mode;
60};
61
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]62&uart2 {
63 clock-frequency = <24000000>;
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]64 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]65 status = "okay";
66};
67
68&ioc {
Tom Rinide70b472023-03-27 15:20:19 -0400[diff] [blame]69 bootph-pre-ram;
Jagan Tekia4dd7932023-01-30 20:27:46 +0530[diff] [blame]70};