Roger Quadros | a4b5a92 | 2024-05-13 15:13:54 +0300 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only OR MIT |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 2 | /* |
| 3 | * AM625 SK: https://www.ti.com/lit/zip/sprr448 |
| 4 | * |
Roger Quadros | a4b5a92 | 2024-05-13 15:13:54 +0300 | [diff] [blame^] | 5 | * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 10 | #include "k3-am62x-sk-common.dtsi" |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 11 | |
| 12 | / { |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 13 | compatible = "ti,am625-sk", "ti,am625"; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 14 | model = "Texas Instruments AM625 SK"; |
| 15 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 16 | opp-table { |
| 17 | /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ |
| 18 | opp-1400000000 { |
| 19 | opp-hz = /bits/ 64 <1400000000>; |
| 20 | opp-supported-hw = <0x01 0x0004>; |
| 21 | clock-latency-ns = <6000000>; |
| 22 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 23 | }; |
| 24 | |
| 25 | memory@80000000 { |
| 26 | device_type = "memory"; |
| 27 | /* 2G RAM */ |
| 28 | reg = <0x00000000 0x80000000 0x00000000 0x80000000>; |
| 29 | |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 30 | }; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 31 | |
| 32 | vmain_pd: regulator-0 { |
| 33 | /* TPS65988 PD CONTROLLER OUTPUT */ |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 34 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 35 | compatible = "regulator-fixed"; |
| 36 | regulator-name = "vmain_pd"; |
| 37 | regulator-min-microvolt = <5000000>; |
| 38 | regulator-max-microvolt = <5000000>; |
| 39 | regulator-always-on; |
| 40 | regulator-boot-on; |
| 41 | }; |
| 42 | |
| 43 | vcc_5v0: regulator-1 { |
| 44 | /* Output of LM34936 */ |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 45 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 46 | compatible = "regulator-fixed"; |
| 47 | regulator-name = "vcc_5v0"; |
| 48 | regulator-min-microvolt = <5000000>; |
| 49 | regulator-max-microvolt = <5000000>; |
| 50 | vin-supply = <&vmain_pd>; |
| 51 | regulator-always-on; |
| 52 | regulator-boot-on; |
| 53 | }; |
| 54 | |
| 55 | vcc_3v3_sys: regulator-2 { |
| 56 | /* output of LM61460-Q1 */ |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 57 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 58 | compatible = "regulator-fixed"; |
| 59 | regulator-name = "vcc_3v3_sys"; |
| 60 | regulator-min-microvolt = <3300000>; |
| 61 | regulator-max-microvolt = <3300000>; |
| 62 | vin-supply = <&vmain_pd>; |
| 63 | regulator-always-on; |
| 64 | regulator-boot-on; |
| 65 | }; |
| 66 | |
| 67 | vdd_mmc1: regulator-3 { |
| 68 | /* TPS22918DBVR */ |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 69 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 70 | compatible = "regulator-fixed"; |
| 71 | regulator-name = "vdd_mmc1"; |
| 72 | regulator-min-microvolt = <3300000>; |
| 73 | regulator-max-microvolt = <3300000>; |
| 74 | regulator-boot-on; |
| 75 | enable-active-high; |
| 76 | vin-supply = <&vcc_3v3_sys>; |
| 77 | gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; |
| 78 | }; |
| 79 | |
| 80 | vdd_sd_dv: regulator-4 { |
| 81 | /* Output of TLV71033 */ |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 82 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 83 | compatible = "regulator-gpio"; |
| 84 | regulator-name = "tlv71033"; |
| 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&vdd_sd_dv_pins_default>; |
| 87 | regulator-min-microvolt = <1800000>; |
| 88 | regulator-max-microvolt = <3300000>; |
| 89 | regulator-boot-on; |
| 90 | vin-supply = <&vcc_5v0>; |
| 91 | gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; |
| 92 | states = <1800000 0x0>, |
| 93 | <3300000 0x1>; |
| 94 | }; |
| 95 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 96 | vcc_1v8: regulator-5 { |
| 97 | /* output of TPS6282518DMQ */ |
| 98 | compatible = "regulator-fixed"; |
| 99 | regulator-name = "vcc_1v8"; |
| 100 | regulator-min-microvolt = <1800000>; |
| 101 | regulator-max-microvolt = <1800000>; |
| 102 | vin-supply = <&vcc_3v3_sys>; |
| 103 | regulator-always-on; |
| 104 | regulator-boot-on; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 105 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | &main_pmx0 { |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 109 | main_rgmii2_pins_default: main-rgmii2-default-pins { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 110 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 111 | pinctrl-single,pins = < |
| 112 | AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ |
| 113 | AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ |
| 114 | AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ |
| 115 | AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ |
| 116 | AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ |
| 117 | AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ |
| 118 | AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ |
| 119 | AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ |
| 120 | AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ |
| 121 | AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ |
| 122 | AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ |
| 123 | AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ |
| 124 | >; |
| 125 | }; |
| 126 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 127 | ospi0_pins_default: ospi0-default-pins { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 128 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 129 | pinctrl-single,pins = < |
| 130 | AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ |
| 131 | AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ |
| 132 | AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ |
| 133 | AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ |
| 134 | AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ |
| 135 | AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ |
| 136 | AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ |
| 137 | AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ |
| 138 | AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ |
| 139 | AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ |
| 140 | AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ |
| 141 | >; |
| 142 | }; |
| 143 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 144 | vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 145 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 146 | pinctrl-single,pins = < |
| 147 | AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ |
| 148 | >; |
| 149 | }; |
| 150 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 151 | main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 152 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 153 | pinctrl-single,pins = < |
| 154 | AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ |
| 155 | >; |
| 156 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 157 | }; |
| 158 | |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 159 | &main_gpio0 { |
| 160 | bootph-all; |
| 161 | }; |
| 162 | |
| 163 | &main_gpio1 { |
| 164 | bootph-all; |
| 165 | }; |
| 166 | |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 167 | &main_i2c1 { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 168 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 169 | exp1: gpio@22 { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 170 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 171 | compatible = "ti,tca6424"; |
| 172 | reg = <0x22>; |
| 173 | gpio-controller; |
| 174 | #gpio-cells = <2>; |
| 175 | gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", |
| 176 | "PRU_DETECT", "MMC1_SD_EN", |
| 177 | "VPP_LDO_EN", "EXP_PS_3V3_En", |
| 178 | "EXP_PS_5V0_En", "EXP_HAT_DETECT", |
| 179 | "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", |
| 180 | "UART1_FET_BUF_EN", "WL_LT_EN", |
| 181 | "GPIO_HDMI_RSTn", "CSI_GPIO1", |
| 182 | "CSI_GPIO2", "PRU_3V3_EN", |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 183 | "HDMI_INTn", "PD_I2C_IRQ", |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 184 | "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", |
| 185 | "MCASP1_FET_SEL", "UART1_FET_SEL", |
| 186 | "TSINT#", "IO_EXP_TEST_LED"; |
| 187 | |
| 188 | interrupt-parent = <&main_gpio1>; |
| 189 | interrupts = <23 IRQ_TYPE_EDGE_FALLING>; |
| 190 | interrupt-controller; |
| 191 | #interrupt-cells = <2>; |
| 192 | |
| 193 | pinctrl-names = "default"; |
| 194 | pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; |
| 195 | }; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 196 | }; |
| 197 | |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 198 | &sdhci1 { |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 199 | vmmc-supply = <&vdd_mmc1>; |
| 200 | vqmmc-supply = <&vdd_sd_dv>; |
Nishanth Menon | c5ac2c7 | 2022-05-25 13:38:48 +0530 | [diff] [blame] | 201 | }; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 202 | |
| 203 | &cpsw3g { |
| 204 | pinctrl-names = "default"; |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 205 | pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | &cpsw_port2 { |
| 209 | phy-mode = "rgmii-rxid"; |
| 210 | phy-handle = <&cpsw3g_phy1>; |
| 211 | }; |
| 212 | |
| 213 | &cpsw3g_mdio { |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 214 | cpsw3g_phy1: ethernet-phy@1 { |
| 215 | reg = <1>; |
| 216 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| 217 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| 218 | ti,min-output-impedance; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | &mailbox0_cluster0 { |
| 223 | mbox_m4_0: mbox-m4-0 { |
| 224 | ti,mbox-rx = <0 0 0>; |
| 225 | ti,mbox-tx = <1 0 0>; |
| 226 | }; |
| 227 | }; |
| 228 | |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 229 | &fss { |
| 230 | bootph-all; |
| 231 | }; |
| 232 | |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 233 | &ospi0 { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 234 | bootph-all; |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 235 | status = "okay"; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 236 | pinctrl-names = "default"; |
| 237 | pinctrl-0 = <&ospi0_pins_default>; |
| 238 | |
Nishanth Menon | 96934b0 | 2023-09-11 09:02:56 -0500 | [diff] [blame] | 239 | flash@0 { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 240 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 241 | compatible = "jedec,spi-nor"; |
| 242 | reg = <0x0>; |
| 243 | spi-tx-bus-width = <8>; |
| 244 | spi-rx-bus-width = <8>; |
| 245 | spi-max-frequency = <25000000>; |
| 246 | cdns,tshsl-ns = <60>; |
| 247 | cdns,tsd2d-ns = <60>; |
| 248 | cdns,tchsh-ns = <60>; |
| 249 | cdns,tslch-ns = <60>; |
| 250 | cdns,read-delay = <4>; |
| 251 | |
| 252 | partitions { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 253 | bootph-all; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 254 | compatible = "fixed-partitions"; |
| 255 | #address-cells = <1>; |
| 256 | #size-cells = <1>; |
| 257 | |
| 258 | partition@0 { |
| 259 | label = "ospi.tiboot3"; |
| 260 | reg = <0x0 0x80000>; |
| 261 | }; |
| 262 | |
| 263 | partition@80000 { |
| 264 | label = "ospi.tispl"; |
| 265 | reg = <0x80000 0x200000>; |
| 266 | }; |
| 267 | |
| 268 | partition@280000 { |
| 269 | label = "ospi.u-boot"; |
| 270 | reg = <0x280000 0x400000>; |
| 271 | }; |
| 272 | |
| 273 | partition@680000 { |
| 274 | label = "ospi.env"; |
| 275 | reg = <0x680000 0x40000>; |
| 276 | }; |
| 277 | |
| 278 | partition@6c0000 { |
| 279 | label = "ospi.env.backup"; |
| 280 | reg = <0x6c0000 0x40000>; |
| 281 | }; |
| 282 | |
| 283 | partition@800000 { |
| 284 | label = "ospi.rootfs"; |
| 285 | reg = <0x800000 0x37c0000>; |
| 286 | }; |
| 287 | |
| 288 | partition@3fc0000 { |
Nishanth Menon | c72e8e7 | 2023-11-14 21:28:54 -0600 | [diff] [blame] | 289 | bootph-pre-ram; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 290 | label = "ospi.phypattern"; |
| 291 | reg = <0x3fc0000 0x40000>; |
| 292 | }; |
| 293 | }; |
| 294 | }; |
| 295 | }; |
| 296 | |
Nishanth Menon | e17596d | 2023-07-27 04:03:31 -0500 | [diff] [blame] | 297 | &tlv320aic3106 { |
| 298 | DVDD-supply = <&vcc_1v8>; |
Dhruva Gole | 0d350bd | 2022-10-27 20:23:09 +0530 | [diff] [blame] | 299 | }; |