blob: 7c98c1b855d13b321e9f501ec7cdc2785b7806bc [file] [log] [blame]
Nishanth Menonc5ac2c72022-05-25 13:38:48 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM625 SK: https://www.ti.com/lit/zip/sprr448
4 *
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8/dts-v1/;
9
Nishanth Menone17596d2023-07-27 04:03:31 -050010#include "k3-am62x-sk-common.dtsi"
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053011
12/ {
Nishanth Menone17596d2023-07-27 04:03:31 -050013 compatible = "ti,am625-sk", "ti,am625";
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053014 model = "Texas Instruments AM625 SK";
15
Nishanth Menone17596d2023-07-27 04:03:31 -050016 opp-table {
17 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
18 opp-1400000000 {
19 opp-hz = /bits/ 64 <1400000000>;
20 opp-supported-hw = <0x01 0x0004>;
21 clock-latency-ns = <6000000>;
22 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053023 };
24
25 memory@80000000 {
26 device_type = "memory";
27 /* 2G RAM */
28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
29
Nishanth Menonc5ac2c72022-05-25 13:38:48 +053030 };
Dhruva Gole0d350bd2022-10-27 20:23:09 +053031
32 vmain_pd: regulator-0 {
33 /* TPS65988 PD CONTROLLER OUTPUT */
34 compatible = "regulator-fixed";
35 regulator-name = "vmain_pd";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 regulator-always-on;
39 regulator-boot-on;
40 };
41
42 vcc_5v0: regulator-1 {
43 /* Output of LM34936 */
44 compatible = "regulator-fixed";
45 regulator-name = "vcc_5v0";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 vin-supply = <&vmain_pd>;
49 regulator-always-on;
50 regulator-boot-on;
51 };
52
53 vcc_3v3_sys: regulator-2 {
54 /* output of LM61460-Q1 */
55 compatible = "regulator-fixed";
56 regulator-name = "vcc_3v3_sys";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 vin-supply = <&vmain_pd>;
60 regulator-always-on;
61 regulator-boot-on;
62 };
63
64 vdd_mmc1: regulator-3 {
65 /* TPS22918DBVR */
66 compatible = "regulator-fixed";
67 regulator-name = "vdd_mmc1";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 regulator-boot-on;
71 enable-active-high;
72 vin-supply = <&vcc_3v3_sys>;
73 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
74 };
75
76 vdd_sd_dv: regulator-4 {
77 /* Output of TLV71033 */
78 compatible = "regulator-gpio";
79 regulator-name = "tlv71033";
80 pinctrl-names = "default";
81 pinctrl-0 = <&vdd_sd_dv_pins_default>;
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-boot-on;
85 vin-supply = <&vcc_5v0>;
86 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
87 states = <1800000 0x0>,
88 <3300000 0x1>;
89 };
90
Nishanth Menone17596d2023-07-27 04:03:31 -050091 vcc_1v8: regulator-5 {
92 /* output of TPS6282518DMQ */
93 compatible = "regulator-fixed";
94 regulator-name = "vcc_1v8";
95 regulator-min-microvolt = <1800000>;
96 regulator-max-microvolt = <1800000>;
97 vin-supply = <&vcc_3v3_sys>;
98 regulator-always-on;
99 regulator-boot-on;
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530100 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530101};
102
103&main_pmx0 {
Nishanth Menone17596d2023-07-27 04:03:31 -0500104 main_rgmii2_pins_default: main-rgmii2-default-pins {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530105 pinctrl-single,pins = <
106 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
107 AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
108 AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
109 AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
110 AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
111 AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
112 AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
113 AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
114 AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
115 AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
116 AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
117 AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
118 >;
119 };
120
Nishanth Menone17596d2023-07-27 04:03:31 -0500121 ospi0_pins_default: ospi0-default-pins {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530122 pinctrl-single,pins = <
123 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
124 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
125 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
126 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
127 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
128 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
129 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
130 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
131 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
132 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
133 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
134 >;
135 };
136
Nishanth Menone17596d2023-07-27 04:03:31 -0500137 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530138 pinctrl-single,pins = <
139 AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
140 >;
141 };
142
Nishanth Menone17596d2023-07-27 04:03:31 -0500143 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530144 pinctrl-single,pins = <
145 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
146 >;
147 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530148};
149
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530150&main_i2c1 {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530151 exp1: gpio@22 {
152 compatible = "ti,tca6424";
153 reg = <0x22>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
157 "PRU_DETECT", "MMC1_SD_EN",
158 "VPP_LDO_EN", "EXP_PS_3V3_En",
159 "EXP_PS_5V0_En", "EXP_HAT_DETECT",
160 "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
161 "UART1_FET_BUF_EN", "WL_LT_EN",
162 "GPIO_HDMI_RSTn", "CSI_GPIO1",
163 "CSI_GPIO2", "PRU_3V3_EN",
Nishanth Menone17596d2023-07-27 04:03:31 -0500164 "HDMI_INTn", "PD_I2C_IRQ",
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530165 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
166 "MCASP1_FET_SEL", "UART1_FET_SEL",
167 "TSINT#", "IO_EXP_TEST_LED";
168
169 interrupt-parent = <&main_gpio1>;
170 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173
174 pinctrl-names = "default";
175 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
176 };
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530177};
178
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530179&sdhci1 {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530180 vmmc-supply = <&vdd_mmc1>;
181 vqmmc-supply = <&vdd_sd_dv>;
Nishanth Menonc5ac2c72022-05-25 13:38:48 +0530182};
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530183
184&cpsw3g {
185 pinctrl-names = "default";
Nishanth Menone17596d2023-07-27 04:03:31 -0500186 pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530187};
188
189&cpsw_port2 {
190 phy-mode = "rgmii-rxid";
191 phy-handle = <&cpsw3g_phy1>;
192};
193
194&cpsw3g_mdio {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530195 cpsw3g_phy1: ethernet-phy@1 {
196 reg = <1>;
197 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
198 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
199 ti,min-output-impedance;
200 };
201};
202
203&mailbox0_cluster0 {
204 mbox_m4_0: mbox-m4-0 {
205 ti,mbox-rx = <0 0 0>;
206 ti,mbox-tx = <1 0 0>;
207 };
208};
209
210&ospi0 {
Nishanth Menone17596d2023-07-27 04:03:31 -0500211 status = "okay";
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530212 pinctrl-names = "default";
213 pinctrl-0 = <&ospi0_pins_default>;
214
Nishanth Menon96934b02023-09-11 09:02:56 -0500215 flash@0 {
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530216 compatible = "jedec,spi-nor";
217 reg = <0x0>;
218 spi-tx-bus-width = <8>;
219 spi-rx-bus-width = <8>;
220 spi-max-frequency = <25000000>;
221 cdns,tshsl-ns = <60>;
222 cdns,tsd2d-ns = <60>;
223 cdns,tchsh-ns = <60>;
224 cdns,tslch-ns = <60>;
225 cdns,read-delay = <4>;
226
227 partitions {
228 compatible = "fixed-partitions";
229 #address-cells = <1>;
230 #size-cells = <1>;
231
232 partition@0 {
233 label = "ospi.tiboot3";
234 reg = <0x0 0x80000>;
235 };
236
237 partition@80000 {
238 label = "ospi.tispl";
239 reg = <0x80000 0x200000>;
240 };
241
242 partition@280000 {
243 label = "ospi.u-boot";
244 reg = <0x280000 0x400000>;
245 };
246
247 partition@680000 {
248 label = "ospi.env";
249 reg = <0x680000 0x40000>;
250 };
251
252 partition@6c0000 {
253 label = "ospi.env.backup";
254 reg = <0x6c0000 0x40000>;
255 };
256
257 partition@800000 {
258 label = "ospi.rootfs";
259 reg = <0x800000 0x37c0000>;
260 };
261
262 partition@3fc0000 {
263 label = "ospi.phypattern";
264 reg = <0x3fc0000 0x40000>;
265 };
266 };
267 };
268};
269
Nishanth Menone17596d2023-07-27 04:03:31 -0500270&tlv320aic3106 {
271 DVDD-supply = <&vcc_1v8>;
Dhruva Gole0d350bd2022-10-27 20:23:09 +0530272};