blob: ab22385c84b2c2c1f18e5316080656694af2aaa3 [file] [log] [blame]
Troy Kiskya18d7862013-01-18 16:14:24 +00001/*
2 * (C) Copyright 2012
3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not write to the Free Software
20 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
21 * MA 02110-1301 USA
22 *
Anatolij Gustschinfd4b3d32013-04-30 11:15:33 +000023 * Refer doc/README.imximage for more details about how-to configure
Troy Kiskya18d7862013-01-18 16:14:24 +000024 * and create imximage boot image
25 *
26 * The syntax is taken as close as possible with the kwbimage
27 */
Stefano Babic53b603c2012-02-22 00:24:40 +000028
Troy Kiskya18d7862013-01-18 16:14:24 +000029/* image version */
Stefano Babic53b603c2012-02-22 00:24:40 +000030IMAGE_VERSION 2
31
Troy Kiskya18d7862013-01-18 16:14:24 +000032/*
33 * Boot Device : one of
34 * spi, sd (the board has no nand neither onenand)
35 */
Stefano Babic53b603c2012-02-22 00:24:40 +000036BOOT_FROM nor
37
Troy Kiskya18d7862013-01-18 16:14:24 +000038/*
39 * Device Configuration Data (DCD)
40 *
41 * Each entry must have the format:
42 * Addr-type Address Value
43 *
44 * where:
45 * Addr-type register length (1,2 or 4 bytes)
46 * Address absolute address of the register
47 * value value to be stored in the register
48 */
49/* IOMUX for RAM only */
Stefano Babic53b603c2012-02-22 00:24:40 +000050DATA 4 0x53fa8554 0x300020
51DATA 4 0x53fa8560 0x300020
52DATA 4 0x53fa8594 0x300020
53DATA 4 0x53fa8584 0x300020
54DATA 4 0x53fa8558 0x300040
55DATA 4 0x53fa8568 0x300040
56DATA 4 0x53fa8590 0x300040
57DATA 4 0x53fa857c 0x300040
58DATA 4 0x53fa8564 0x300040
59DATA 4 0x53fa8580 0x300040
60DATA 4 0x53fa8570 0x300220
61DATA 4 0x53fa8578 0x300220
62DATA 4 0x53fa872c 0x300000
63DATA 4 0x53fa8728 0x300000
64DATA 4 0x53fa871c 0x300000
65DATA 4 0x53fa8718 0x300000
66DATA 4 0x53fa8574 0x300020
67DATA 4 0x53fa8588 0x300020
68DATA 4 0x53fa855c 0x0
69DATA 4 0x53fa858c 0x0
70DATA 4 0x53fa856c 0x300040
71DATA 4 0x53fa86f0 0x300000
72DATA 4 0x53fa8720 0x300000
73DATA 4 0x53fa86fc 0x0
74DATA 4 0x53fa86f4 0x0
75DATA 4 0x53fa8714 0x0
76DATA 4 0x53fa8724 0x4000000
Troy Kiskya18d7862013-01-18 16:14:24 +000077
78/* DDR RAM */
Stefano Babic53b603c2012-02-22 00:24:40 +000079DATA 4 0x63fd9088 0x40404040
80DATA 4 0x63fd9090 0x40404040
81DATA 4 0x63fd907C 0x01420143
82DATA 4 0x63fd9080 0x01450146
83DATA 4 0x63fd9018 0x00111740
84DATA 4 0x63fd9000 0x84190000
Troy Kiskya18d7862013-01-18 16:14:24 +000085
86/* esdcfgX */
Stefano Babic53b603c2012-02-22 00:24:40 +000087DATA 4 0x63fd900C 0x9f5152e3
88DATA 4 0x63fd9010 0xb68e8a63
89DATA 4 0x63fd9014 0x01ff00db
Troy Kiskya18d7862013-01-18 16:14:24 +000090
91/* Read/Write command delay */
Stefano Babic53b603c2012-02-22 00:24:40 +000092DATA 4 0x63fd902c 0x000026d2
Troy Kiskya18d7862013-01-18 16:14:24 +000093
94/* Out of reset delays */
Stefano Babic53b603c2012-02-22 00:24:40 +000095DATA 4 0x63fd9030 0x00ff0e21
Troy Kiskya18d7862013-01-18 16:14:24 +000096
97/* ESDCTL ODT timing control */
Stefano Babic53b603c2012-02-22 00:24:40 +000098DATA 4 0x63fd9008 0x12273030
Troy Kiskya18d7862013-01-18 16:14:24 +000099
100/* ESDCTL power down control */
Stefano Babic53b603c2012-02-22 00:24:40 +0000101DATA 4 0x63fd9004 0x0002002d
Troy Kiskya18d7862013-01-18 16:14:24 +0000102
103/* Set registers in DDR memory chips */
Stefano Babic53b603c2012-02-22 00:24:40 +0000104DATA 4 0x63fd901c 0x00008032
105DATA 4 0x63fd901c 0x00008033
106DATA 4 0x63fd901c 0x00028031
107DATA 4 0x63fd901c 0x052080b0
108DATA 4 0x63fd901c 0x04008040
Troy Kiskya18d7862013-01-18 16:14:24 +0000109
110/* ESDCTL refresh control */
Stefano Babic53b603c2012-02-22 00:24:40 +0000111DATA 4 0x63fd9020 0x00005800
Troy Kiskya18d7862013-01-18 16:14:24 +0000112
113/* PHY ZQ HW control */
Stefano Babic53b603c2012-02-22 00:24:40 +0000114DATA 4 0x63fd9040 0x05380003
Troy Kiskya18d7862013-01-18 16:14:24 +0000115
116/* PHY ODT control */
Stefano Babic53b603c2012-02-22 00:24:40 +0000117DATA 4 0x63fd9058 0x00022222
Troy Kiskya18d7862013-01-18 16:14:24 +0000118
119/* start DDR3 */
Stefano Babic53b603c2012-02-22 00:24:40 +0000120DATA 4 0x63fd901c 0x00000000