Blame - board/esg/ima3-mx53/imximage.cfg - filogic/uboot

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Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	1	/*
				2	* (C) Copyright 2012
				3	* Stefano Babic DENX Software Engineering sbabic@denx.de.
				4	*
				5	* See file CREDITS for list of people who contributed to this
				6	* project.
				7	*
				8	* This program is free software; you can redistribute it and/or
				9	* modify it under the terms of the GNU General Public License as
				10	* published by the Free Software Foundation; either version 2 of
				11	* the License or (at your option) any later version.
				12	*
				13	* This program is distributed in the hope that it will be useful,
				14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				16	* GNU General Public License for more details.
				17	*
				18	* You should have received a copy of the GNU General Public License
				19	* along with this program; if not write to the Free Software
				20	* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
				21	* MA 02110-1301 USA
				22	*
				23	* Refer docs/README.imxmage for more details about how-to configure
				24	* and create imximage boot image
				25	*
				26	* The syntax is taken as close as possible with the kwbimage
				27	*/
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	28
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	29	/* image version */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	30	IMAGE_VERSION 2
				31
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	32	/*
				33	* Boot Device : one of
				34	* spi, sd (the board has no nand neither onenand)
				35	*/
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	36	BOOT_FROM nor
				37
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	38	/*
				39	* Device Configuration Data (DCD)
				40	*
				41	* Each entry must have the format:
				42	* Addr-type Address Value
				43	*
				44	* where:
				45	* Addr-type register length (1,2 or 4 bytes)
				46	* Address absolute address of the register
				47	* value value to be stored in the register
				48	*/
				49	/* IOMUX for RAM only */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	50	DATA 4 0x53fa8554 0x300020
				51	DATA 4 0x53fa8560 0x300020
				52	DATA 4 0x53fa8594 0x300020
				53	DATA 4 0x53fa8584 0x300020
				54	DATA 4 0x53fa8558 0x300040
				55	DATA 4 0x53fa8568 0x300040
				56	DATA 4 0x53fa8590 0x300040
				57	DATA 4 0x53fa857c 0x300040
				58	DATA 4 0x53fa8564 0x300040
				59	DATA 4 0x53fa8580 0x300040
				60	DATA 4 0x53fa8570 0x300220
				61	DATA 4 0x53fa8578 0x300220
				62	DATA 4 0x53fa872c 0x300000
				63	DATA 4 0x53fa8728 0x300000
				64	DATA 4 0x53fa871c 0x300000
				65	DATA 4 0x53fa8718 0x300000
				66	DATA 4 0x53fa8574 0x300020
				67	DATA 4 0x53fa8588 0x300020
				68	DATA 4 0x53fa855c 0x0
				69	DATA 4 0x53fa858c 0x0
				70	DATA 4 0x53fa856c 0x300040
				71	DATA 4 0x53fa86f0 0x300000
				72	DATA 4 0x53fa8720 0x300000
				73	DATA 4 0x53fa86fc 0x0
				74	DATA 4 0x53fa86f4 0x0
				75	DATA 4 0x53fa8714 0x0
				76	DATA 4 0x53fa8724 0x4000000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	77
				78	/* DDR RAM */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	79	DATA 4 0x63fd9088 0x40404040
				80	DATA 4 0x63fd9090 0x40404040
				81	DATA 4 0x63fd907C 0x01420143
				82	DATA 4 0x63fd9080 0x01450146
				83	DATA 4 0x63fd9018 0x00111740
				84	DATA 4 0x63fd9000 0x84190000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	85
				86	/* esdcfgX */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	87	DATA 4 0x63fd900C 0x9f5152e3
				88	DATA 4 0x63fd9010 0xb68e8a63
				89	DATA 4 0x63fd9014 0x01ff00db
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	90
				91	/* Read/Write command delay */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	92	DATA 4 0x63fd902c 0x000026d2
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	93
				94	/* Out of reset delays */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	95	DATA 4 0x63fd9030 0x00ff0e21
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	96
				97	/* ESDCTL ODT timing control */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	98	DATA 4 0x63fd9008 0x12273030
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	99
				100	/* ESDCTL power down control */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	101	DATA 4 0x63fd9004 0x0002002d
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	102
				103	/* Set registers in DDR memory chips */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	104	DATA 4 0x63fd901c 0x00008032
				105	DATA 4 0x63fd901c 0x00008033
				106	DATA 4 0x63fd901c 0x00028031
				107	DATA 4 0x63fd901c 0x052080b0
				108	DATA 4 0x63fd901c 0x04008040
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	109
				110	/* ESDCTL refresh control */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	111	DATA 4 0x63fd9020 0x00005800
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	112
				113	/* PHY ZQ HW control */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	114	DATA 4 0x63fd9040 0x05380003
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	115
				116	/* PHY ODT control */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	117	DATA 4 0x63fd9058 0x00022222
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame^]	118
				119	/* start DDR3 */
Stefano Babic	53b603c	2012-02-22 00:24:40 +0000	[diff] [blame]	120	DATA 4 0x63fd901c 0x00000000