Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __TEGRA2_COMMON_H |
| 25 | #define __TEGRA2_COMMON_H |
| 26 | #include <asm/sizes.h> |
| 27 | |
| 28 | /* |
Simon Glass | ef2fb1a | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 29 | * QUOTE(m) will evaluate to a string version of the value of the macro m |
| 30 | * passed in. The extra level of indirection here is to first evaluate the |
| 31 | * macro m before applying the quoting operator. |
| 32 | */ |
| 33 | #define QUOTE_(m) #m |
| 34 | #define QUOTE(m) QUOTE_(m) |
| 35 | |
| 36 | /* |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 37 | * High Level Configuration Options |
| 38 | */ |
| 39 | #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ |
| 40 | #define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */ |
| 41 | #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ |
Aneesh V | ecee9c8 | 2011-06-16 23:30:48 +0000 | [diff] [blame] | 42 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 43 | |
Anton staaf | 5420cba | 2011-10-03 13:54:58 +0000 | [diff] [blame] | 44 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 45 | |
Simon Glass | 5f3a899 | 2011-11-05 03:56:49 +0000 | [diff] [blame] | 46 | #define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ |
Tom Warren | 112a188 | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 47 | |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 48 | #include <asm/arch/tegra2.h> /* get chip and board defs */ |
| 49 | |
| 50 | /* |
| 51 | * Display CPU and Board information |
| 52 | */ |
| 53 | #define CONFIG_DISPLAY_CPUINFO |
| 54 | #define CONFIG_DISPLAY_BOARDINFO |
| 55 | |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 56 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 57 | |
| 58 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
Grant Likely | 100b849 | 2011-03-28 09:59:07 +0000 | [diff] [blame] | 59 | #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 60 | |
Simon Glass | ef2fb1a | 2012-04-02 13:19:03 +0000 | [diff] [blame] | 61 | #ifdef CONFIG_TEGRA2_LP0 |
| 62 | #define TEGRA_LP0_ADDR 0x1C406000 |
| 63 | #define TEGRA_LP0_SIZE 0x2000 |
| 64 | #define TEGRA_LP0_VEC \ |
| 65 | "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " " |
| 66 | #else |
| 67 | #define TEGRA_LP0_VEC |
| 68 | #endif |
| 69 | |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 70 | /* Environment */ |
Simon Glass | 4e61a34 | 2011-11-05 04:46:48 +0000 | [diff] [blame] | 71 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Size of malloc() pool |
| 75 | */ |
| 76 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ |
| 77 | |
| 78 | /* |
| 79 | * PllX Configuration |
| 80 | */ |
| 81 | #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ |
| 82 | |
| 83 | /* |
| 84 | * NS16550 Configuration |
| 85 | */ |
| 86 | #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ |
| 87 | |
| 88 | #define CONFIG_SYS_NS16550 |
| 89 | #define CONFIG_SYS_NS16550_SERIAL |
| 90 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 91 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| 92 | |
| 93 | /* |
| 94 | * select serial console configuration |
| 95 | */ |
| 96 | #define CONFIG_CONS_INDEX 1 |
| 97 | |
| 98 | /* allow to overwrite serial and ethaddr */ |
| 99 | #define CONFIG_ENV_OVERWRITE |
| 100 | #define CONFIG_BAUDRATE 115200 |
| 101 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 102 | 115200} |
| 103 | |
Simon Glass | 9d58086 | 2012-02-27 10:52:51 +0000 | [diff] [blame] | 104 | /* |
| 105 | * This parameter affects a TXFILLTUNING field that controls how much data is |
| 106 | * sent to the latency fifo before it is sent to the wire. Without this |
| 107 | * parameter, the default (2) causes occasional Data Buffer Errors in OUT |
| 108 | * packets depending on the buffer address and size. |
| 109 | */ |
| 110 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 |
| 111 | #define CONFIG_EHCI_IS_TDI |
| 112 | #define CONFIG_EHCI_DCACHE |
| 113 | |
Simon Glass | aac6088 | 2012-02-03 15:13:59 +0000 | [diff] [blame] | 114 | /* Total I2C ports on Tegra2 */ |
| 115 | #define TEGRA_I2C_NUM_CONTROLLERS 4 |
| 116 | |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 117 | /* include default commands */ |
| 118 | #include <config_cmd_default.h> |
| 119 | |
| 120 | /* remove unused commands */ |
| 121 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
| 122 | #undef CONFIG_CMD_FPGA /* FPGA configuration support */ |
| 123 | #undef CONFIG_CMD_IMI |
| 124 | #undef CONFIG_CMD_IMLS |
| 125 | #undef CONFIG_CMD_NFS /* NFS support */ |
| 126 | #undef CONFIG_CMD_NET /* network support */ |
| 127 | |
| 128 | /* turn on command-line edit/hist/auto */ |
| 129 | #define CONFIG_CMDLINE_EDITING |
| 130 | #define CONFIG_COMMAND_HISTORY |
Mike Frysinger | c1285cb | 2011-10-26 00:19:58 +0000 | [diff] [blame] | 131 | #define CONFIG_AUTO_COMPLETE |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 132 | |
| 133 | #define CONFIG_SYS_NO_FLASH |
| 134 | |
Simon Glass | a32d33d | 2012-04-17 09:01:36 +0000 | [diff] [blame^] | 135 | /* Environment information, boards can override if required */ |
| 136 | #define CONFIG_CONSOLE_MUX |
| 137 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 138 | #define TEGRA2_DEVICE_SETTINGS "stdin=serial\0" \ |
| 139 | "stdout=serial\0" \ |
| 140 | "stderr=serial\0" |
| 141 | |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 142 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 143 | "console=ttyS0,115200n8\0" \ |
| 144 | "mem=" TEGRA2_SYSMEM "\0" \ |
| 145 | "smpflag=smp\0" \ |
Simon Glass | a32d33d | 2012-04-17 09:01:36 +0000 | [diff] [blame^] | 146 | TEGRA2_DEVICE_SETTINGS |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 147 | |
| 148 | #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ |
| 149 | #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ |
| 150 | |
| 151 | /* |
| 152 | * Miscellaneous configurable options |
| 153 | */ |
| 154 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 155 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
| 156 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 157 | #define CONFIG_SYS_PROMPT V_PROMPT |
| 158 | /* |
| 159 | * Increasing the size of the IO buffer as default nfsargs size is more |
| 160 | * than 256 and so it is not possible to edit it |
| 161 | */ |
| 162 | #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ |
| 163 | /* Print Buffer Size */ |
| 164 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 165 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 166 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 167 | /* Boot Argument Buffer Size */ |
| 168 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| 169 | |
| 170 | #define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000) |
| 171 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) |
| 172 | |
| 173 | #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ |
| 174 | #define CONFIG_SYS_HZ 1000 |
| 175 | |
| 176 | /*----------------------------------------------------------------------- |
| 177 | * Stack sizes |
| 178 | * |
| 179 | * The stack sizes are set up in start.S using the settings below |
| 180 | */ |
| 181 | #define CONFIG_STACKBASE 0x2800000 /* 40MB */ |
| 182 | #define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/ |
| 183 | |
| 184 | /*----------------------------------------------------------------------- |
| 185 | * Physical Memory Map |
| 186 | */ |
| 187 | #define CONFIG_NR_DRAM_BANKS 1 |
| 188 | #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 |
| 189 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
| 190 | |
Thierry Reding | 925fae6 | 2011-11-17 00:04:06 +0000 | [diff] [blame] | 191 | #define CONFIG_SYS_TEXT_BASE 0x00108000 |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 192 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 193 | |
| 194 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 195 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
| 196 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 197 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 198 | GENERATED_GBL_DATA_SIZE) |
| 199 | |
Tom Warren | 6e3806b | 2011-06-17 06:27:29 +0000 | [diff] [blame] | 200 | #define CONFIG_TEGRA2_GPIO |
| 201 | #define CONFIG_CMD_GPIO |
Tom Warren | a3e280b | 2011-01-27 10:58:07 +0000 | [diff] [blame] | 202 | #endif /* __TEGRA2_COMMON_H */ |