blob: 66a388d601f5fa046940c564d135fb1c64c3d64c [file] [log] [blame]
Simon Glass509805b2015-01-27 22:13:39 -07001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <errno.h>
9#include <asm/io.h>
Bin Meng07793c082015-10-11 21:37:42 -070010#include <asm/mrccache.h>
Simon Glass509805b2015-01-27 22:13:39 -070011#include <asm/post.h>
12#include <asm/processor.h>
13#include <asm/fsp/fsp_support.h>
14
Simon Glassdaa93d92015-07-31 09:31:31 -060015DECLARE_GLOBAL_DATA_PTR;
16
Simon Glassee7c36f2017-03-28 10:27:30 -060017int checkcpu(void)
18{
19 return 0;
20}
21
Simon Glass509805b2015-01-27 22:13:39 -070022int print_cpuinfo(void)
23{
24 post_code(POST_CPU_INFO);
25 return default_print_cpuinfo();
26}
27
Simon Glassfa912732015-08-10 07:05:07 -060028int fsp_init_phase_pci(void)
Simon Glass509805b2015-01-27 22:13:39 -070029{
30 u32 status;
31
32 /* call into FspNotify */
33 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
34 status = fsp_notify(NULL, INIT_PHASE_PCI);
Simon Glassfa912732015-08-10 07:05:07 -060035 if (status)
Simon Glass509805b2015-01-27 22:13:39 -070036 debug("fail, error code %x\n", status);
37 else
38 debug("OK\n");
39
Simon Glassfa912732015-08-10 07:05:07 -060040 return status ? -EPERM : 0;
41}
42
Simon Glass509805b2015-01-27 22:13:39 -070043void board_final_cleanup(void)
44{
45 u32 status;
46
47 /* call into FspNotify */
48 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
49 status = fsp_notify(NULL, INIT_PHASE_BOOT);
Simon Glass38252292015-08-12 19:33:07 -060050 if (status)
Simon Glass509805b2015-01-27 22:13:39 -070051 debug("fail, error code %x\n", status);
52 else
53 debug("OK\n");
54
55 return;
56}
Bin Mengd560c5c2015-06-07 11:33:14 +080057
Bin Meng07793c082015-10-11 21:37:42 -070058static __maybe_unused void *fsp_prepare_mrc_cache(void)
59{
60 struct mrc_data_container *cache;
61 struct mrc_region entry;
62 int ret;
63
64 ret = mrccache_get_region(NULL, &entry);
65 if (ret)
66 return NULL;
67
68 cache = mrccache_find_current(&entry);
69 if (!cache)
70 return NULL;
71
72 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
73 cache->data, cache->data_size, cache->checksum);
74
75 return cache->data;
76}
77
Simon Glass295c4232017-03-28 10:27:18 -060078int arch_fsp_init(void)
Bin Mengd560c5c2015-06-07 11:33:14 +080079{
Bin Meng07793c082015-10-11 21:37:42 -070080 void *nvs;
81
Bin Meng12440cd2015-08-20 06:40:19 -070082 if (!gd->arch.hob_list) {
Bin Meng07793c082015-10-11 21:37:42 -070083#ifdef CONFIG_ENABLE_MRC_CACHE
84 nvs = fsp_prepare_mrc_cache();
85#else
86 nvs = NULL;
87#endif
Bin Meng12440cd2015-08-20 06:40:19 -070088 /*
89 * The first time we enter here, call fsp_init().
90 * Note the execution does not return to this function,
91 * instead it jumps to fsp_continue().
92 */
Bin Meng07793c082015-10-11 21:37:42 -070093 fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs);
Bin Meng12440cd2015-08-20 06:40:19 -070094 } else {
95 /*
96 * The second time we enter here, adjust the size of malloc()
97 * pool before relocation. Given gd->malloc_base was adjusted
Albert ARIBAUD6cb4c462015-11-25 17:56:32 +010098 * after the call to board_init_f_init_reserve() in arch/x86/
99 * cpu/start.S, we should fix up gd->malloc_limit here.
Bin Meng12440cd2015-08-20 06:40:19 -0700100 */
101 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
102 }
Bin Mengd560c5c2015-06-07 11:33:14 +0800103
104 return 0;
105}