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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#ifndef _ASM_ARCH_SYS_PROTO_H
8#define _ASM_ARCH_SYS_PROTO_H
9
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053010#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
Siva Durga Prasad Paladugub1acb652018-02-28 13:26:53 +053011#define KEY_PTR_LEN 32
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053012
Siva Durga Prasad Paladugu6809e812018-05-31 15:10:23 +053013#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
14#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
15#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
16#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
Siva Durga Prasad Paladugu91c315d2018-03-01 17:44:47 +053017#define ZYNQMP_FPGA_BIT_NS 5
18
Siva Durga Prasad Paladugu6809e812018-05-31 15:10:23 +053019#define ZYNQMP_FPGA_AUTH_DDR 1
20
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053021enum {
22 IDCODE,
23 VERSION,
Michal Simek50d8cef2017-08-22 14:58:53 +020024 IDCODE2,
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053025};
26
27enum {
28 ZYNQMP_SILICON_V1,
29 ZYNQMP_SILICON_V2,
30 ZYNQMP_SILICON_V3,
31 ZYNQMP_SILICON_V4,
32};
33
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053034enum {
35 TCM_LOCK,
36 TCM_SPLIT,
37};
38
Ibai Erkiaga4b1264d2019-09-27 11:36:56 +010039struct zynqmp_ipi_msg {
40 size_t len;
41 u32 *buf;
42};
43
Michal Simek44dd5202017-07-31 10:37:09 +020044int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
Michal Simek04b7e622015-01-15 10:01:51 +010045unsigned int zynqmp_get_silicon_version(void);
46
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053047int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
48int zynqmp_mmio_read(const u32 address, u32 *value);
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053049
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053050void initialize_tcm(bool mode);
Nitin Jain9bcc76f2018-04-20 12:30:40 +053051void mem_map_fill(void);
Siva Durga Prasad Paladugu48eaa0c2018-10-05 15:09:05 +053052#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
53void tcm_init(u8 mode);
54#endif
Siva Durga Prasad Paladugucd35d522017-07-25 11:51:38 +053055
Michal Simek04b7e622015-01-15 10:01:51 +010056#endif /* _ASM_ARCH_SYS_PROTO_H */