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Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _ASM_ARCH_SYS_PROTO_H
9#define _ASM_ARCH_SYS_PROTO_H
10
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053011#define PAYLOAD_ARG_CNT 5
12
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053013#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
Siva Durga Prasad Paladugub1acb652018-02-28 13:26:53 +053014#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
15#define KEY_PTR_LEN 32
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053016
17enum {
18 IDCODE,
19 VERSION,
Michal Simek50d8cef2017-08-22 14:58:53 +020020 IDCODE2,
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053021};
22
23enum {
24 ZYNQMP_SILICON_V1,
25 ZYNQMP_SILICON_V2,
26 ZYNQMP_SILICON_V3,
27 ZYNQMP_SILICON_V4,
28};
29
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053030enum {
31 TCM_LOCK,
32 TCM_SPLIT,
33};
34
Michal Simek44dd5202017-07-31 10:37:09 +020035int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
Michal Simek04b7e622015-01-15 10:01:51 +010036unsigned int zynqmp_get_silicon_version(void);
37
Michal Simek456e4542017-01-09 10:05:16 +010038void handoff_setup(void);
39
Michal Simek8b353302017-02-07 14:32:26 +010040void zynqmp_pmufw_version(void);
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053041int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
42int zynqmp_mmio_read(const u32 address, u32 *value);
43int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
44 u32 *ret_payload);
45
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053046void initialize_tcm(bool mode);
47
Siva Durga Prasad Paladugucd35d522017-07-25 11:51:38 +053048int chip_id(unsigned char id);
49
Michal Simek04b7e622015-01-15 10:01:51 +010050#endif /* _ASM_ARCH_SYS_PROTO_H */