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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sune12abcb2015-03-20 19:28:24 -07002/*
3 * Copyright 2015 Freescale Semiconductor
Gaurav Jain476c6392022-03-24 11:50:35 +05304 * Copyright 2017, 2021 NXP
York Sune12abcb2015-03-20 19:28:24 -07005 */
6#include <common.h>
Tom Rini8c70baa2021-12-14 13:36:40 -05007#include <clock_legacy.h>
Simon Glass1ab16922022-07-31 12:28:48 -06008#include <display_options.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06009#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
York Sune12abcb2015-03-20 19:28:24 -070011#include <malloc.h>
12#include <errno.h>
13#include <netdev.h>
14#include <fsl_ifc.h>
15#include <fsl_ddr.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
York Sune12abcb2015-03-20 19:28:24 -070017#include <asm/io.h>
Yangbo Lucf005552015-05-28 14:53:55 +053018#include <hwconfig.h>
York Sune12abcb2015-03-20 19:28:24 -070019#include <fdt_support.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090020#include <linux/libfdt.h>
York Sune12abcb2015-03-20 19:28:24 -070021#include <fsl-mc/fsl_mc.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060022#include <env_internal.h>
Alexander Graf34f8e972016-11-17 01:02:59 +010023#include <efi_loader.h>
York Sune12abcb2015-03-20 19:28:24 -070024#include <i2c.h>
York Sun729f2d12017-03-06 09:02:34 -080025#include <asm/arch/mmu.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080026#include <asm/arch/soc.h>
Santan Kumarc61c6992017-03-07 11:21:03 +053027#include <asm/arch/ppa.h>
Laurentiu Tudor4adff392019-10-18 09:01:54 +000028#include <asm/arch-fsl-layerscape/fsl_icid.h>
Stephen Carlson4e979ac2021-06-22 16:42:02 -070029#include "../common/i2c_mux.h"
York Sune12abcb2015-03-20 19:28:24 -070030
Priyanka Jain6720d0a2017-04-28 10:41:34 +053031#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -070032#include "../common/qixis.h"
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053033#include "ls2080ardb_qixis.h"
Priyanka Jain6720d0a2017-04-28 10:41:34 +053034#endif
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053035#include "../common/vid.h"
York Sune12abcb2015-03-20 19:28:24 -070036
Kuldeep Singhee510de2021-08-10 11:20:09 +053037#define CORTINA_FW_ADDR_IFCNOR 0x580980000
38#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000
39#define CORTINA_FW_ADDR_QSPI 0x980000
Yangbo Lucf005552015-05-28 14:53:55 +053040#define PIN_MUX_SEL_SDHC 0x00
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +080041#define PIN_MUX_SEL_DSPI 0x0a
Yangbo Lucf005552015-05-28 14:53:55 +053042
43#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
York Sune12abcb2015-03-20 19:28:24 -070044DECLARE_GLOBAL_DATA_PTR;
45
Yangbo Lucf005552015-05-28 14:53:55 +053046enum {
47 MUX_TYPE_SDHC,
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +080048 MUX_TYPE_DSPI,
Yangbo Lucf005552015-05-28 14:53:55 +053049};
50
Stephen Carlsonc3301a22021-02-08 11:11:29 +010051#ifdef CONFIG_VID
52u16 soc_get_fuse_vid(int vid_index)
53{
54 static const u16 vdd[32] = {
55 10500,
56 0, /* reserved */
57 9750,
58 0, /* reserved */
59 9500,
60 0, /* reserved */
61 0, /* reserved */
62 0, /* reserved */
63 9000, /* reserved */
64 0, /* reserved */
65 0, /* reserved */
66 0, /* reserved */
67 0, /* reserved */
68 0, /* reserved */
69 0, /* reserved */
70 0, /* reserved */
71 10000, /* 1.0000V */
72 0, /* reserved */
73 10250,
74 0, /* reserved */
75 10500,
76 0, /* reserved */
77 0, /* reserved */
78 0, /* reserved */
79 0, /* reserved */
80 0, /* reserved */
81 0, /* reserved */
82 0, /* reserved */
83 0, /* reserved */
84 0, /* reserved */
85 0, /* reserved */
86 0, /* reserved */
87 };
88
89 return vdd[vid_index];
90};
91#endif
92
York Sune12abcb2015-03-20 19:28:24 -070093unsigned long long get_qixis_addr(void)
94{
95 unsigned long long addr;
96
97 if (gd->flags & GD_FLG_RELOC)
98 addr = QIXIS_BASE_PHYS;
99 else
100 addr = QIXIS_BASE_PHYS_EARLY;
101
102 /*
103 * IFC address under 256MB is mapped to 0x30000000, any address above
104 * is mapped to 0x5_10000000 up to 4GB.
105 */
106 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
107
108 return addr;
109}
110
111int checkboard(void)
112{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530113#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700114 u8 sw;
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530115#endif
Prabhakar Kushwaha67f2e9c2015-05-28 14:54:07 +0530116 char buf[15];
117
118 cpu_name(buf);
119 printf("Board: %s-RDB, ", buf);
York Sune12abcb2015-03-20 19:28:24 -0700120
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530121#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530122#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700123 sw = QIXIS_READ(arch);
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530124 printf("Board version: %c, ", (sw & 0xf) + 'A');
125
126 sw = QIXIS_READ(brdcfg[0]);
Priyanka Jain75985792018-01-08 12:20:42 +0530127 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530128 switch (sw) {
129 case 0:
130 puts("boot from QSPI DEV#0\n");
131 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
132 break;
133 case 1:
134 puts("boot from QSPI DEV#1\n");
135 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
136 break;
137 case 2:
138 puts("boot from QSPI EMU\n");
139 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
140 break;
141 case 3:
142 puts("boot from QSPI EMU\n");
143 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
144 break;
145 case 4:
146 puts("boot from QSPI DEV#0\n");
147 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
148 break;
149 default:
150 printf("invalid setting of SW%u\n", sw);
151 break;
152 }
Priyanka Jain6e9d2952018-01-08 12:59:31 +0530153 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530154#endif
155 puts("SERDES1 Reference : ");
156 printf("Clock1 = 100MHz ");
157 printf("Clock2 = 161.13MHz");
158#else
159#ifdef CONFIG_FSL_QIXIS
160 sw = QIXIS_READ(arch);
161 printf("Board Arch: V%d, ", sw >> 4);
Prabhakar Kushwaha8368a592015-05-28 14:54:04 +0530162 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
York Sune12abcb2015-03-20 19:28:24 -0700163
164 sw = QIXIS_READ(brdcfg[0]);
165 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
166
167 if (sw < 0x8)
168 printf("vBank: %d\n", sw);
169 else if (sw == 0x9)
170 puts("NAND\n");
171 else
172 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
173
174 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530175#endif
York Sune12abcb2015-03-20 19:28:24 -0700176 puts("SERDES1 Reference : ");
177 printf("Clock1 = 156.25MHz ");
178 printf("Clock2 = 156.25MHz");
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530179#endif
York Sune12abcb2015-03-20 19:28:24 -0700180
181 puts("\nSERDES2 Reference : ");
182 printf("Clock1 = 100MHz ");
183 printf("Clock2 = 100MHz\n");
184
185 return 0;
186}
187
188unsigned long get_board_sys_clk(void)
189{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530190#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700191 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
192
193 switch (sysclk_conf & 0x0F) {
194 case QIXIS_SYSCLK_83:
195 return 83333333;
196 case QIXIS_SYSCLK_100:
197 return 100000000;
198 case QIXIS_SYSCLK_125:
199 return 125000000;
200 case QIXIS_SYSCLK_133:
201 return 133333333;
202 case QIXIS_SYSCLK_150:
203 return 150000000;
204 case QIXIS_SYSCLK_160:
205 return 160000000;
206 case QIXIS_SYSCLK_166:
207 return 166666666;
208 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530209#endif
210 return 100000000;
York Sune12abcb2015-03-20 19:28:24 -0700211}
212
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530213int i2c_multiplexer_select_vid_channel(u8 channel)
214{
Stephen Carlson4e979ac2021-06-22 16:42:02 -0700215 return select_i2c_ch_pca9547(channel, 0);
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530216}
217
Yangbo Lucf005552015-05-28 14:53:55 +0530218int config_board_mux(int ctrl_type)
219{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530220#ifdef CONFIG_FSL_QIXIS
Yangbo Lucf005552015-05-28 14:53:55 +0530221 u8 reg5;
222
223 reg5 = QIXIS_READ(brdcfg[5]);
224
225 switch (ctrl_type) {
226 case MUX_TYPE_SDHC:
227 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
228 break;
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800229 case MUX_TYPE_DSPI:
230 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
231 break;
Yangbo Lucf005552015-05-28 14:53:55 +0530232 default:
233 printf("Wrong mux interface type\n");
234 return -1;
235 }
236
237 QIXIS_WRITE(brdcfg[5], reg5);
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530238#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800239 return 0;
240}
241
Kuldeep Singhee510de2021-08-10 11:20:09 +0530242ulong *cs4340_get_fw_addr(void)
243{
244#ifdef CONFIG_TFABOOT
Tom Rini376b88a2022-10-28 20:27:13 -0400245 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
Kuldeep Singhee510de2021-08-10 11:20:09 +0530246 u32 svr = gur_in32(&gur->svr);
247#endif
248 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
249
250#ifdef CONFIG_TFABOOT
251 /* LS2088A TFA boot */
252 if (SVR_SOC_VER(svr) == SVR_LS2088A) {
253 enum boot_src src = get_boot_src();
254 u8 sw;
255
256 switch (src) {
257 case BOOT_SOURCE_IFC_NOR:
258 sw = QIXIS_READ(brdcfg[0]);
259 sw = (sw & 0x0f);
260 if (sw == 0)
261 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
262 else if (sw == 4)
263 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
264 break;
265 case BOOT_SOURCE_QSPI_NOR:
266 /* Only one bank in QSPI */
267 cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
268 break;
269 default:
270 printf("WARNING: Boot source not found\n");
271 }
272 }
273#endif
274 return (ulong *)cortina_fw_addr;
275}
276
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800277int board_init(void)
278{
York Sun8cbc1952016-05-26 13:59:03 -0700279#ifdef CONFIG_FSL_MC_ENET
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800280 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
York Sun8cbc1952016-05-26 13:59:03 -0700281#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800282
283 init_final_memctl_regs();
284
Stephen Carlson4e979ac2021-06-22 16:42:02 -0700285 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800286
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530287#ifdef CONFIG_FSL_QIXIS
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800288 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530289#endif
Udit Agarwalc83ea8a2017-08-16 07:13:29 -0400290
Santan Kumarc61c6992017-03-07 11:21:03 +0530291#ifdef CONFIG_FSL_LS_PPA
292 ppa_init();
293#endif
294
York Sun8cbc1952016-05-26 13:59:03 -0700295#ifdef CONFIG_FSL_MC_ENET
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800296 /* invert AQR405 IRQ pins polarity */
297 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
York Sun8cbc1952016-05-26 13:59:03 -0700298#endif
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800299
Ioana Ciorneicfa114a2020-03-18 16:47:40 +0200300#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
301 pci_init();
302#endif
303
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800304 return 0;
305}
306
307int board_early_init_f(void)
308{
Tom Rini714482a2021-08-18 23:12:25 -0400309#if defined(CONFIG_SYS_I2C_EARLY_INIT)
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530310 i2c_early_init_f();
311#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800312 fsl_lsch3_early_init_f();
Yangbo Lucf005552015-05-28 14:53:55 +0530313 return 0;
314}
315
316int misc_init_r(void)
317{
Santan Kumar0ce3f402017-06-15 17:07:01 +0530318 char *env_hwconfig;
319 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
320 u32 val;
Tom Rini376b88a2022-10-28 20:27:13 -0400321 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
Priyanka Jain0915dda2017-09-15 10:19:48 +0530322 u32 svr = gur_in32(&gur->svr);
Santan Kumar0ce3f402017-06-15 17:07:01 +0530323
324 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
325
Simon Glass64b723f2017-08-03 12:22:12 -0600326 env_hwconfig = env_get("hwconfig");
Santan Kumar0ce3f402017-06-15 17:07:01 +0530327
328 if (hwconfig_f("dspi", env_hwconfig) &&
329 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
330 config_board_mux(MUX_TYPE_DSPI);
331 else
332 config_board_mux(MUX_TYPE_SDHC);
333
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530334 /*
Santan Kumar20e7f5a2017-06-09 11:48:05 +0530335 * LS2081ARDB RevF board has smart voltage translator
Priyanka Jaind1587182017-04-25 10:12:31 +0530336 * which needs to be programmed to enable high speed SD interface
337 * by setting GPIO4_10 output to zero
338 */
Santan Kumar20e7f5a2017-06-09 11:48:05 +0530339#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jaind1587182017-04-25 10:12:31 +0530340 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
341 in_le32(GPIO4_GPDIR_ADDR)));
342 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
343 in_le32(GPIO4_GPDAT_ADDR)));
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530344#endif
Yangbo Lucf005552015-05-28 14:53:55 +0530345 if (hwconfig("sdhc"))
346 config_board_mux(MUX_TYPE_SDHC);
347
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530348 if (adjust_vdd(0))
349 printf("Warning: Adjusting core voltage failed.\n");
Priyanka Jain0915dda2017-09-15 10:19:48 +0530350 /*
351 * Default value of board env is based on filename which is
352 * ls2080ardb. Modify board env for other supported SoCs
353 */
354 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
355 (SVR_SOC_VER(svr) == SVR_LS2048A))
356 env_set("board", "ls2088ardb");
357 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
358 (SVR_SOC_VER(svr) == SVR_LS2041A))
359 env_set("board", "ls2081ardb");
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530360
Yangbo Lucf005552015-05-28 14:53:55 +0530361 return 0;
362}
363
York Sune12abcb2015-03-20 19:28:24 -0700364void detail_board_ddr_info(void)
365{
366 puts("\nDDR ");
367 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
368 print_ddr_info(0);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530369#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -0700370 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sune12abcb2015-03-20 19:28:24 -0700371 puts("\nDP-DDR ");
372 print_size(gd->bd->bi_dram[2].size, "");
373 print_ddr_info(CONFIG_DP_DDR_CTRL);
374 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530375#endif
York Sune12abcb2015-03-20 19:28:24 -0700376}
377
York Sune12abcb2015-03-20 19:28:24 -0700378#ifdef CONFIG_FSL_MC_ENET
379void fdt_fixup_board_enet(void *fdt)
380{
381 int offset;
382
Stuart Yodera3466152016-03-02 16:37:13 -0600383 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
York Sune12abcb2015-03-20 19:28:24 -0700384
385 if (offset < 0)
Stuart Yodera3466152016-03-02 16:37:13 -0600386 offset = fdt_path_offset(fdt, "/fsl-mc");
York Sune12abcb2015-03-20 19:28:24 -0700387
388 if (offset < 0) {
389 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
390 __func__, offset);
391 return;
392 }
393
Mian Yousaf Kaukab97124652018-12-18 14:01:17 +0100394 if (get_mc_boot_status() == 0 &&
395 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
York Sune12abcb2015-03-20 19:28:24 -0700396 fdt_status_okay(fdt, offset);
397 else
398 fdt_status_fail(fdt, offset);
399}
Alexander Graf2ebeb442016-11-17 01:02:57 +0100400
401void board_quiesce_devices(void)
402{
403 fsl_mc_ldpaa_exit(gd->bd);
404}
York Sune12abcb2015-03-20 19:28:24 -0700405#endif
406
407#ifdef CONFIG_OF_BOARD_SETUP
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530408void fsl_fdt_fixup_flash(void *fdt)
409{
410 int offset;
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000411#ifdef CONFIG_TFABOOT
412 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
413 u32 val;
414#endif
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530415
416/*
417 * IFC and QSPI are muxed on board.
418 * So disable IFC node in dts if QSPI is enabled or
419 * disable QSPI node in dts in case QSPI is not enabled.
420 */
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000421#ifdef CONFIG_TFABOOT
422 enum boot_src src = get_boot_src();
423 bool disable_ifc = false;
424
425 switch (src) {
426 case BOOT_SOURCE_IFC_NOR:
427 disable_ifc = false;
428 break;
429 case BOOT_SOURCE_QSPI_NOR:
430 disable_ifc = true;
431 break;
432 default:
433 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
434 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
435 disable_ifc = true;
436 break;
437 }
438
439 if (disable_ifc) {
440 offset = fdt_path_offset(fdt, "/soc/ifc");
441
442 if (offset < 0)
443 offset = fdt_path_offset(fdt, "/ifc");
444 } else {
445 offset = fdt_path_offset(fdt, "/soc/quadspi");
446
447 if (offset < 0)
448 offset = fdt_path_offset(fdt, "/quadspi");
449 }
450
451#else
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530452#ifdef CONFIG_FSL_QSPI
453 offset = fdt_path_offset(fdt, "/soc/ifc");
454
455 if (offset < 0)
456 offset = fdt_path_offset(fdt, "/ifc");
457#else
458 offset = fdt_path_offset(fdt, "/soc/quadspi");
459
460 if (offset < 0)
461 offset = fdt_path_offset(fdt, "/quadspi");
462#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000463#endif
464
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530465 if (offset < 0)
466 return;
467
468 fdt_status_disabled(fdt, offset);
469}
470
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900471int ft_board_setup(void *blob, struct bd_info *bd)
York Sune12abcb2015-03-20 19:28:24 -0700472{
Meenakshi Aggarwald67ae482019-05-23 15:13:43 +0530473 int i;
474 u16 mc_memory_bank = 0;
475
476 u64 *base;
477 u64 *size;
478 u64 mc_memory_base = 0;
479 u64 mc_memory_size = 0;
480 u16 total_memory_banks;
York Sune12abcb2015-03-20 19:28:24 -0700481
482 ft_cpu_setup(blob, bd);
483
Meenakshi Aggarwald67ae482019-05-23 15:13:43 +0530484 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
485
486 if (mc_memory_base != 0)
487 mc_memory_bank++;
488
489 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
490
491 base = calloc(total_memory_banks, sizeof(u64));
492 size = calloc(total_memory_banks, sizeof(u64));
493
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530494 /* fixup DT for the two GPP DDR banks */
495 base[0] = gd->bd->bi_dram[0].start;
496 size[0] = gd->bd->bi_dram[0].size;
497 base[1] = gd->bd->bi_dram[1].start;
498 size[1] = gd->bd->bi_dram[1].size;
499
York Sun4de24ef2017-03-06 09:02:28 -0800500#ifdef CONFIG_RESV_RAM
501 /* reduce size if reserved memory is within this bank */
502 if (gd->arch.resv_ram >= base[0] &&
503 gd->arch.resv_ram < base[0] + size[0])
504 size[0] = gd->arch.resv_ram - base[0];
505 else if (gd->arch.resv_ram >= base[1] &&
506 gd->arch.resv_ram < base[1] + size[1])
507 size[1] = gd->arch.resv_ram - base[1];
508#endif
509
Meenakshi Aggarwald67ae482019-05-23 15:13:43 +0530510 if (mc_memory_base != 0) {
511 for (i = 0; i <= total_memory_banks; i++) {
512 if (base[i] == 0 && size[i] == 0) {
513 base[i] = mc_memory_base;
514 size[i] = mc_memory_size;
515 break;
516 }
517 }
518 }
519
520 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
York Sune12abcb2015-03-20 19:28:24 -0700521
Nipun Guptad6912642018-08-20 16:01:14 +0530522 fdt_fsl_mc_fixup_iommu_map_entry(blob);
523
Sriram Dash9fd465c2016-09-16 17:12:15 +0530524 fsl_fdt_fixup_dr_usb(blob, bd);
Sriram Dash01820952016-06-13 09:58:36 +0530525
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530526 fsl_fdt_fixup_flash(blob);
527
York Sune12abcb2015-03-20 19:28:24 -0700528#ifdef CONFIG_FSL_MC_ENET
529 fdt_fixup_board_enet(blob);
York Sune12abcb2015-03-20 19:28:24 -0700530#endif
531
Laurentiu Tudor4adff392019-10-18 09:01:54 +0000532 fdt_fixup_icid(blob);
533
York Sune12abcb2015-03-20 19:28:24 -0700534 return 0;
535}
536#endif
537
538void qixis_dump_switch(void)
539{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530540#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700541 int i, nr_of_cfgsw;
542
543 QIXIS_WRITE(cms[0], 0x00);
544 nr_of_cfgsw = QIXIS_READ(cms[1]);
545
546 puts("DIP switch settings dump:\n");
547 for (i = 1; i <= nr_of_cfgsw; i++) {
548 QIXIS_WRITE(cms[0], i);
549 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
550 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530551#endif
York Sune12abcb2015-03-20 19:28:24 -0700552}
York Sunac192a92015-05-28 14:54:09 +0530553
554/*
555 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
556 * Both slots has 0x54, resulting 2nd slot unusable.
557 */
558void update_spd_address(unsigned int ctrl_num,
559 unsigned int slot,
560 unsigned int *addr)
561{
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530562#ifndef CONFIG_TARGET_LS2081ARDB
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530563#ifdef CONFIG_FSL_QIXIS
York Sunac192a92015-05-28 14:54:09 +0530564 u8 sw;
565
566 sw = QIXIS_READ(arch);
567 if ((sw & 0xf) < 0x3) {
568 if (ctrl_num == 1 && slot == 0)
569 *addr = SPD_EEPROM_ADDRESS4;
570 else if (ctrl_num == 1 && slot == 1)
571 *addr = SPD_EEPROM_ADDRESS3;
572 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530573#endif
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530574#endif
York Sunac192a92015-05-28 14:54:09 +0530575}