Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2015 Freescale Semiconductor |
Alison Wang | 160a435 | 2018-06-18 20:25:05 +0800 | [diff] [blame] | 4 | * Copyright 2017 NXP |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 5 | */ |
| 6 | #include <common.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 7 | #include <env.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 9 | #include <malloc.h> |
| 10 | #include <errno.h> |
| 11 | #include <netdev.h> |
| 12 | #include <fsl_ifc.h> |
| 13 | #include <fsl_ddr.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 15 | #include <asm/io.h> |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 16 | #include <hwconfig.h> |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 17 | #include <fdt_support.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 18 | #include <linux/libfdt.h> |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 19 | #include <fsl-mc/fsl_mc.h> |
Simon Glass | 9d1f619 | 2019-08-02 09:44:25 -0600 | [diff] [blame] | 20 | #include <env_internal.h> |
Alexander Graf | 34f8e97 | 2016-11-17 01:02:59 +0100 | [diff] [blame] | 21 | #include <efi_loader.h> |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 22 | #include <i2c.h> |
York Sun | 729f2d1 | 2017-03-06 09:02:34 -0800 | [diff] [blame] | 23 | #include <asm/arch/mmu.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 24 | #include <asm/arch/soc.h> |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame] | 25 | #include <asm/arch/ppa.h> |
Saksham Jain | c0c38d2 | 2016-03-23 16:24:35 +0530 | [diff] [blame] | 26 | #include <fsl_sec.h> |
Laurentiu Tudor | 4adff39 | 2019-10-18 09:01:54 +0000 | [diff] [blame] | 27 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
Stephen Carlson | 4e979ac | 2021-06-22 16:42:02 -0700 | [diff] [blame] | 28 | #include "../common/i2c_mux.h" |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 29 | |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 30 | #ifdef CONFIG_FSL_QIXIS |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 31 | #include "../common/qixis.h" |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 32 | #include "ls2080ardb_qixis.h" |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 33 | #endif |
Rai Harninder | 6aa1f3b | 2016-03-23 17:04:38 +0530 | [diff] [blame] | 34 | #include "../common/vid.h" |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 35 | |
Kuldeep Singh | ee510de | 2021-08-10 11:20:09 +0530 | [diff] [blame] | 36 | #define CORTINA_FW_ADDR_IFCNOR 0x580980000 |
| 37 | #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000 |
| 38 | #define CORTINA_FW_ADDR_QSPI 0x980000 |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 39 | #define PIN_MUX_SEL_SDHC 0x00 |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 40 | #define PIN_MUX_SEL_DSPI 0x0a |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 41 | |
| 42 | #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 43 | DECLARE_GLOBAL_DATA_PTR; |
| 44 | |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 45 | enum { |
| 46 | MUX_TYPE_SDHC, |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 47 | MUX_TYPE_DSPI, |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 48 | }; |
| 49 | |
Stephen Carlson | c3301a2 | 2021-02-08 11:11:29 +0100 | [diff] [blame] | 50 | #ifdef CONFIG_VID |
| 51 | u16 soc_get_fuse_vid(int vid_index) |
| 52 | { |
| 53 | static const u16 vdd[32] = { |
| 54 | 10500, |
| 55 | 0, /* reserved */ |
| 56 | 9750, |
| 57 | 0, /* reserved */ |
| 58 | 9500, |
| 59 | 0, /* reserved */ |
| 60 | 0, /* reserved */ |
| 61 | 0, /* reserved */ |
| 62 | 9000, /* reserved */ |
| 63 | 0, /* reserved */ |
| 64 | 0, /* reserved */ |
| 65 | 0, /* reserved */ |
| 66 | 0, /* reserved */ |
| 67 | 0, /* reserved */ |
| 68 | 0, /* reserved */ |
| 69 | 0, /* reserved */ |
| 70 | 10000, /* 1.0000V */ |
| 71 | 0, /* reserved */ |
| 72 | 10250, |
| 73 | 0, /* reserved */ |
| 74 | 10500, |
| 75 | 0, /* reserved */ |
| 76 | 0, /* reserved */ |
| 77 | 0, /* reserved */ |
| 78 | 0, /* reserved */ |
| 79 | 0, /* reserved */ |
| 80 | 0, /* reserved */ |
| 81 | 0, /* reserved */ |
| 82 | 0, /* reserved */ |
| 83 | 0, /* reserved */ |
| 84 | 0, /* reserved */ |
| 85 | 0, /* reserved */ |
| 86 | }; |
| 87 | |
| 88 | return vdd[vid_index]; |
| 89 | }; |
| 90 | #endif |
| 91 | |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 92 | unsigned long long get_qixis_addr(void) |
| 93 | { |
| 94 | unsigned long long addr; |
| 95 | |
| 96 | if (gd->flags & GD_FLG_RELOC) |
| 97 | addr = QIXIS_BASE_PHYS; |
| 98 | else |
| 99 | addr = QIXIS_BASE_PHYS_EARLY; |
| 100 | |
| 101 | /* |
| 102 | * IFC address under 256MB is mapped to 0x30000000, any address above |
| 103 | * is mapped to 0x5_10000000 up to 4GB. |
| 104 | */ |
| 105 | addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; |
| 106 | |
| 107 | return addr; |
| 108 | } |
| 109 | |
| 110 | int checkboard(void) |
| 111 | { |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 112 | #ifdef CONFIG_FSL_QIXIS |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 113 | u8 sw; |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 114 | #endif |
Prabhakar Kushwaha | 67f2e9c | 2015-05-28 14:54:07 +0530 | [diff] [blame] | 115 | char buf[15]; |
| 116 | |
| 117 | cpu_name(buf); |
| 118 | printf("Board: %s-RDB, ", buf); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 119 | |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 120 | #ifdef CONFIG_TARGET_LS2081ARDB |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 121 | #ifdef CONFIG_FSL_QIXIS |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 122 | sw = QIXIS_READ(arch); |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 123 | printf("Board version: %c, ", (sw & 0xf) + 'A'); |
| 124 | |
| 125 | sw = QIXIS_READ(brdcfg[0]); |
Priyanka Jain | 7598579 | 2018-01-08 12:20:42 +0530 | [diff] [blame] | 126 | sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK; |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 127 | switch (sw) { |
| 128 | case 0: |
| 129 | puts("boot from QSPI DEV#0\n"); |
| 130 | puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); |
| 131 | break; |
| 132 | case 1: |
| 133 | puts("boot from QSPI DEV#1\n"); |
| 134 | puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); |
| 135 | break; |
| 136 | case 2: |
| 137 | puts("boot from QSPI EMU\n"); |
| 138 | puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); |
| 139 | break; |
| 140 | case 3: |
| 141 | puts("boot from QSPI EMU\n"); |
| 142 | puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); |
| 143 | break; |
| 144 | case 4: |
| 145 | puts("boot from QSPI DEV#0\n"); |
| 146 | puts("QSPI_CSA_1 mapped to QSPI EMU\n"); |
| 147 | break; |
| 148 | default: |
| 149 | printf("invalid setting of SW%u\n", sw); |
| 150 | break; |
| 151 | } |
Priyanka Jain | 6e9d295 | 2018-01-08 12:59:31 +0530 | [diff] [blame] | 152 | printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 153 | #endif |
| 154 | puts("SERDES1 Reference : "); |
| 155 | printf("Clock1 = 100MHz "); |
| 156 | printf("Clock2 = 161.13MHz"); |
| 157 | #else |
| 158 | #ifdef CONFIG_FSL_QIXIS |
| 159 | sw = QIXIS_READ(arch); |
| 160 | printf("Board Arch: V%d, ", sw >> 4); |
Prabhakar Kushwaha | 8368a59 | 2015-05-28 14:54:04 +0530 | [diff] [blame] | 161 | printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 162 | |
| 163 | sw = QIXIS_READ(brdcfg[0]); |
| 164 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 165 | |
| 166 | if (sw < 0x8) |
| 167 | printf("vBank: %d\n", sw); |
| 168 | else if (sw == 0x9) |
| 169 | puts("NAND\n"); |
| 170 | else |
| 171 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
| 172 | |
| 173 | printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 174 | #endif |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 175 | puts("SERDES1 Reference : "); |
| 176 | printf("Clock1 = 156.25MHz "); |
| 177 | printf("Clock2 = 156.25MHz"); |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 178 | #endif |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 179 | |
| 180 | puts("\nSERDES2 Reference : "); |
| 181 | printf("Clock1 = 100MHz "); |
| 182 | printf("Clock2 = 100MHz\n"); |
| 183 | |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | unsigned long get_board_sys_clk(void) |
| 188 | { |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 189 | #ifdef CONFIG_FSL_QIXIS |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 190 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 191 | |
| 192 | switch (sysclk_conf & 0x0F) { |
| 193 | case QIXIS_SYSCLK_83: |
| 194 | return 83333333; |
| 195 | case QIXIS_SYSCLK_100: |
| 196 | return 100000000; |
| 197 | case QIXIS_SYSCLK_125: |
| 198 | return 125000000; |
| 199 | case QIXIS_SYSCLK_133: |
| 200 | return 133333333; |
| 201 | case QIXIS_SYSCLK_150: |
| 202 | return 150000000; |
| 203 | case QIXIS_SYSCLK_160: |
| 204 | return 160000000; |
| 205 | case QIXIS_SYSCLK_166: |
| 206 | return 166666666; |
| 207 | } |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 208 | #endif |
| 209 | return 100000000; |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 210 | } |
| 211 | |
Rai Harninder | 6aa1f3b | 2016-03-23 17:04:38 +0530 | [diff] [blame] | 212 | int i2c_multiplexer_select_vid_channel(u8 channel) |
| 213 | { |
Stephen Carlson | 4e979ac | 2021-06-22 16:42:02 -0700 | [diff] [blame] | 214 | return select_i2c_ch_pca9547(channel, 0); |
Rai Harninder | 6aa1f3b | 2016-03-23 17:04:38 +0530 | [diff] [blame] | 215 | } |
| 216 | |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 217 | int config_board_mux(int ctrl_type) |
| 218 | { |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 219 | #ifdef CONFIG_FSL_QIXIS |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 220 | u8 reg5; |
| 221 | |
| 222 | reg5 = QIXIS_READ(brdcfg[5]); |
| 223 | |
| 224 | switch (ctrl_type) { |
| 225 | case MUX_TYPE_SDHC: |
| 226 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); |
| 227 | break; |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 228 | case MUX_TYPE_DSPI: |
| 229 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); |
| 230 | break; |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 231 | default: |
| 232 | printf("Wrong mux interface type\n"); |
| 233 | return -1; |
| 234 | } |
| 235 | |
| 236 | QIXIS_WRITE(brdcfg[5], reg5); |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 237 | #endif |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 238 | return 0; |
| 239 | } |
| 240 | |
Kuldeep Singh | ee510de | 2021-08-10 11:20:09 +0530 | [diff] [blame] | 241 | ulong *cs4340_get_fw_addr(void) |
| 242 | { |
| 243 | #ifdef CONFIG_TFABOOT |
| 244 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 245 | u32 svr = gur_in32(&gur->svr); |
| 246 | #endif |
| 247 | ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; |
| 248 | |
| 249 | #ifdef CONFIG_TFABOOT |
| 250 | /* LS2088A TFA boot */ |
| 251 | if (SVR_SOC_VER(svr) == SVR_LS2088A) { |
| 252 | enum boot_src src = get_boot_src(); |
| 253 | u8 sw; |
| 254 | |
| 255 | switch (src) { |
| 256 | case BOOT_SOURCE_IFC_NOR: |
| 257 | sw = QIXIS_READ(brdcfg[0]); |
| 258 | sw = (sw & 0x0f); |
| 259 | if (sw == 0) |
| 260 | cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; |
| 261 | else if (sw == 4) |
| 262 | cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; |
| 263 | break; |
| 264 | case BOOT_SOURCE_QSPI_NOR: |
| 265 | /* Only one bank in QSPI */ |
| 266 | cortina_fw_addr = CORTINA_FW_ADDR_QSPI; |
| 267 | break; |
| 268 | default: |
| 269 | printf("WARNING: Boot source not found\n"); |
| 270 | } |
| 271 | } |
| 272 | #endif |
| 273 | return (ulong *)cortina_fw_addr; |
| 274 | } |
| 275 | |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 276 | int board_init(void) |
| 277 | { |
York Sun | 8cbc195 | 2016-05-26 13:59:03 -0700 | [diff] [blame] | 278 | #ifdef CONFIG_FSL_MC_ENET |
Shaohui Xie | 8c7ce82 | 2016-01-28 15:38:15 +0800 | [diff] [blame] | 279 | u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; |
York Sun | 8cbc195 | 2016-05-26 13:59:03 -0700 | [diff] [blame] | 280 | #endif |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 281 | |
| 282 | init_final_memctl_regs(); |
| 283 | |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 284 | #ifdef CONFIG_ENV_IS_NOWHERE |
| 285 | gd->env_addr = (ulong)&default_environment[0]; |
| 286 | #endif |
Stephen Carlson | 4e979ac | 2021-06-22 16:42:02 -0700 | [diff] [blame] | 287 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 288 | |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 289 | #ifdef CONFIG_FSL_QIXIS |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 290 | QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 291 | #endif |
Udit Agarwal | c83ea8a | 2017-08-16 07:13:29 -0400 | [diff] [blame] | 292 | |
| 293 | #ifdef CONFIG_FSL_CAAM |
| 294 | sec_init(); |
| 295 | #endif |
Santan Kumar | c61c699 | 2017-03-07 11:21:03 +0530 | [diff] [blame] | 296 | #ifdef CONFIG_FSL_LS_PPA |
| 297 | ppa_init(); |
| 298 | #endif |
| 299 | |
York Sun | 8cbc195 | 2016-05-26 13:59:03 -0700 | [diff] [blame] | 300 | #ifdef CONFIG_FSL_MC_ENET |
Shaohui Xie | 8c7ce82 | 2016-01-28 15:38:15 +0800 | [diff] [blame] | 301 | /* invert AQR405 IRQ pins polarity */ |
| 302 | out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); |
York Sun | 8cbc195 | 2016-05-26 13:59:03 -0700 | [diff] [blame] | 303 | #endif |
Udit Agarwal | 62ed9a8 | 2017-02-03 22:53:38 +0530 | [diff] [blame] | 304 | #ifdef CONFIG_FSL_CAAM |
| 305 | sec_init(); |
| 306 | #endif |
Shaohui Xie | 8c7ce82 | 2016-01-28 15:38:15 +0800 | [diff] [blame] | 307 | |
Ioana Ciornei | cfa114a | 2020-03-18 16:47:40 +0200 | [diff] [blame] | 308 | #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) |
| 309 | pci_init(); |
| 310 | #endif |
| 311 | |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | int board_early_init_f(void) |
| 316 | { |
Tom Rini | 714482a | 2021-08-18 23:12:25 -0400 | [diff] [blame^] | 317 | #if defined(CONFIG_SYS_I2C_EARLY_INIT) |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 318 | i2c_early_init_f(); |
| 319 | #endif |
Haikun.Wang@freescale.com | b8a258c | 2015-06-26 19:58:24 +0800 | [diff] [blame] | 320 | fsl_lsch3_early_init_f(); |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | int misc_init_r(void) |
| 325 | { |
Santan Kumar | 0ce3f40 | 2017-06-15 17:07:01 +0530 | [diff] [blame] | 326 | char *env_hwconfig; |
| 327 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| 328 | u32 val; |
Priyanka Jain | 0915dda | 2017-09-15 10:19:48 +0530 | [diff] [blame] | 329 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 330 | u32 svr = gur_in32(&gur->svr); |
Santan Kumar | 0ce3f40 | 2017-06-15 17:07:01 +0530 | [diff] [blame] | 331 | |
| 332 | val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); |
| 333 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 334 | env_hwconfig = env_get("hwconfig"); |
Santan Kumar | 0ce3f40 | 2017-06-15 17:07:01 +0530 | [diff] [blame] | 335 | |
| 336 | if (hwconfig_f("dspi", env_hwconfig) && |
| 337 | DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) |
| 338 | config_board_mux(MUX_TYPE_DSPI); |
| 339 | else |
| 340 | config_board_mux(MUX_TYPE_SDHC); |
| 341 | |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 342 | /* |
Santan Kumar | 20e7f5a | 2017-06-09 11:48:05 +0530 | [diff] [blame] | 343 | * LS2081ARDB RevF board has smart voltage translator |
Priyanka Jain | d158718 | 2017-04-25 10:12:31 +0530 | [diff] [blame] | 344 | * which needs to be programmed to enable high speed SD interface |
| 345 | * by setting GPIO4_10 output to zero |
| 346 | */ |
Santan Kumar | 20e7f5a | 2017-06-09 11:48:05 +0530 | [diff] [blame] | 347 | #ifdef CONFIG_TARGET_LS2081ARDB |
Priyanka Jain | d158718 | 2017-04-25 10:12:31 +0530 | [diff] [blame] | 348 | out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | |
| 349 | in_le32(GPIO4_GPDIR_ADDR))); |
| 350 | out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & |
| 351 | in_le32(GPIO4_GPDAT_ADDR))); |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 352 | #endif |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 353 | if (hwconfig("sdhc")) |
| 354 | config_board_mux(MUX_TYPE_SDHC); |
| 355 | |
Rai Harninder | 6aa1f3b | 2016-03-23 17:04:38 +0530 | [diff] [blame] | 356 | if (adjust_vdd(0)) |
| 357 | printf("Warning: Adjusting core voltage failed.\n"); |
Priyanka Jain | 0915dda | 2017-09-15 10:19:48 +0530 | [diff] [blame] | 358 | /* |
| 359 | * Default value of board env is based on filename which is |
| 360 | * ls2080ardb. Modify board env for other supported SoCs |
| 361 | */ |
| 362 | if ((SVR_SOC_VER(svr) == SVR_LS2088A) || |
| 363 | (SVR_SOC_VER(svr) == SVR_LS2048A)) |
| 364 | env_set("board", "ls2088ardb"); |
| 365 | else if ((SVR_SOC_VER(svr) == SVR_LS2081A) || |
| 366 | (SVR_SOC_VER(svr) == SVR_LS2041A)) |
| 367 | env_set("board", "ls2081ardb"); |
Rai Harninder | 6aa1f3b | 2016-03-23 17:04:38 +0530 | [diff] [blame] | 368 | |
Yangbo Lu | cf00555 | 2015-05-28 14:53:55 +0530 | [diff] [blame] | 369 | return 0; |
| 370 | } |
| 371 | |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 372 | void detail_board_ddr_info(void) |
| 373 | { |
| 374 | puts("\nDDR "); |
| 375 | print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); |
| 376 | print_ddr_info(0); |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 377 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 378 | if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 379 | puts("\nDP-DDR "); |
| 380 | print_size(gd->bd->bi_dram[2].size, ""); |
| 381 | print_ddr_info(CONFIG_DP_DDR_CTRL); |
| 382 | } |
Prabhakar Kushwaha | 122bcfd | 2015-11-09 16:42:07 +0530 | [diff] [blame] | 383 | #endif |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 384 | } |
| 385 | |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 386 | #ifdef CONFIG_FSL_MC_ENET |
| 387 | void fdt_fixup_board_enet(void *fdt) |
| 388 | { |
| 389 | int offset; |
| 390 | |
Stuart Yoder | a346615 | 2016-03-02 16:37:13 -0600 | [diff] [blame] | 391 | offset = fdt_path_offset(fdt, "/soc/fsl-mc"); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 392 | |
| 393 | if (offset < 0) |
Stuart Yoder | a346615 | 2016-03-02 16:37:13 -0600 | [diff] [blame] | 394 | offset = fdt_path_offset(fdt, "/fsl-mc"); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 395 | |
| 396 | if (offset < 0) { |
| 397 | printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", |
| 398 | __func__, offset); |
| 399 | return; |
| 400 | } |
| 401 | |
Mian Yousaf Kaukab | 9712465 | 2018-12-18 14:01:17 +0100 | [diff] [blame] | 402 | if (get_mc_boot_status() == 0 && |
| 403 | (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 404 | fdt_status_okay(fdt, offset); |
| 405 | else |
| 406 | fdt_status_fail(fdt, offset); |
| 407 | } |
Alexander Graf | 2ebeb44 | 2016-11-17 01:02:57 +0100 | [diff] [blame] | 408 | |
| 409 | void board_quiesce_devices(void) |
| 410 | { |
| 411 | fsl_mc_ldpaa_exit(gd->bd); |
| 412 | } |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 413 | #endif |
| 414 | |
| 415 | #ifdef CONFIG_OF_BOARD_SETUP |
Santan Kumar | 39ea8bf | 2017-07-05 18:05:08 +0530 | [diff] [blame] | 416 | void fsl_fdt_fixup_flash(void *fdt) |
| 417 | { |
| 418 | int offset; |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 419 | #ifdef CONFIG_TFABOOT |
| 420 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| 421 | u32 val; |
| 422 | #endif |
Santan Kumar | 39ea8bf | 2017-07-05 18:05:08 +0530 | [diff] [blame] | 423 | |
| 424 | /* |
| 425 | * IFC and QSPI are muxed on board. |
| 426 | * So disable IFC node in dts if QSPI is enabled or |
| 427 | * disable QSPI node in dts in case QSPI is not enabled. |
| 428 | */ |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 429 | #ifdef CONFIG_TFABOOT |
| 430 | enum boot_src src = get_boot_src(); |
| 431 | bool disable_ifc = false; |
| 432 | |
| 433 | switch (src) { |
| 434 | case BOOT_SOURCE_IFC_NOR: |
| 435 | disable_ifc = false; |
| 436 | break; |
| 437 | case BOOT_SOURCE_QSPI_NOR: |
| 438 | disable_ifc = true; |
| 439 | break; |
| 440 | default: |
| 441 | val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); |
| 442 | if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) |
| 443 | disable_ifc = true; |
| 444 | break; |
| 445 | } |
| 446 | |
| 447 | if (disable_ifc) { |
| 448 | offset = fdt_path_offset(fdt, "/soc/ifc"); |
| 449 | |
| 450 | if (offset < 0) |
| 451 | offset = fdt_path_offset(fdt, "/ifc"); |
| 452 | } else { |
| 453 | offset = fdt_path_offset(fdt, "/soc/quadspi"); |
| 454 | |
| 455 | if (offset < 0) |
| 456 | offset = fdt_path_offset(fdt, "/quadspi"); |
| 457 | } |
| 458 | |
| 459 | #else |
Santan Kumar | 39ea8bf | 2017-07-05 18:05:08 +0530 | [diff] [blame] | 460 | #ifdef CONFIG_FSL_QSPI |
| 461 | offset = fdt_path_offset(fdt, "/soc/ifc"); |
| 462 | |
| 463 | if (offset < 0) |
| 464 | offset = fdt_path_offset(fdt, "/ifc"); |
| 465 | #else |
| 466 | offset = fdt_path_offset(fdt, "/soc/quadspi"); |
| 467 | |
| 468 | if (offset < 0) |
| 469 | offset = fdt_path_offset(fdt, "/quadspi"); |
| 470 | #endif |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 471 | #endif |
| 472 | |
Santan Kumar | 39ea8bf | 2017-07-05 18:05:08 +0530 | [diff] [blame] | 473 | if (offset < 0) |
| 474 | return; |
| 475 | |
| 476 | fdt_status_disabled(fdt, offset); |
| 477 | } |
| 478 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 479 | int ft_board_setup(void *blob, struct bd_info *bd) |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 480 | { |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 481 | int i; |
| 482 | u16 mc_memory_bank = 0; |
| 483 | |
| 484 | u64 *base; |
| 485 | u64 *size; |
| 486 | u64 mc_memory_base = 0; |
| 487 | u64 mc_memory_size = 0; |
| 488 | u16 total_memory_banks; |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 489 | |
| 490 | ft_cpu_setup(blob, bd); |
| 491 | |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 492 | fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); |
| 493 | |
| 494 | if (mc_memory_base != 0) |
| 495 | mc_memory_bank++; |
| 496 | |
| 497 | total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; |
| 498 | |
| 499 | base = calloc(total_memory_banks, sizeof(u64)); |
| 500 | size = calloc(total_memory_banks, sizeof(u64)); |
| 501 | |
Bhupesh Sharma | 0b10a1a | 2015-05-28 14:54:10 +0530 | [diff] [blame] | 502 | /* fixup DT for the two GPP DDR banks */ |
| 503 | base[0] = gd->bd->bi_dram[0].start; |
| 504 | size[0] = gd->bd->bi_dram[0].size; |
| 505 | base[1] = gd->bd->bi_dram[1].start; |
| 506 | size[1] = gd->bd->bi_dram[1].size; |
| 507 | |
York Sun | 4de24ef | 2017-03-06 09:02:28 -0800 | [diff] [blame] | 508 | #ifdef CONFIG_RESV_RAM |
| 509 | /* reduce size if reserved memory is within this bank */ |
| 510 | if (gd->arch.resv_ram >= base[0] && |
| 511 | gd->arch.resv_ram < base[0] + size[0]) |
| 512 | size[0] = gd->arch.resv_ram - base[0]; |
| 513 | else if (gd->arch.resv_ram >= base[1] && |
| 514 | gd->arch.resv_ram < base[1] + size[1]) |
| 515 | size[1] = gd->arch.resv_ram - base[1]; |
| 516 | #endif |
| 517 | |
Meenakshi Aggarwal | d67ae48 | 2019-05-23 15:13:43 +0530 | [diff] [blame] | 518 | if (mc_memory_base != 0) { |
| 519 | for (i = 0; i <= total_memory_banks; i++) { |
| 520 | if (base[i] == 0 && size[i] == 0) { |
| 521 | base[i] = mc_memory_base; |
| 522 | size[i] = mc_memory_size; |
| 523 | break; |
| 524 | } |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | fdt_fixup_memory_banks(blob, base, size, total_memory_banks); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 529 | |
Nipun Gupta | d691264 | 2018-08-20 16:01:14 +0530 | [diff] [blame] | 530 | fdt_fsl_mc_fixup_iommu_map_entry(blob); |
| 531 | |
Sriram Dash | 9fd465c | 2016-09-16 17:12:15 +0530 | [diff] [blame] | 532 | fsl_fdt_fixup_dr_usb(blob, bd); |
Sriram Dash | 0182095 | 2016-06-13 09:58:36 +0530 | [diff] [blame] | 533 | |
Santan Kumar | 39ea8bf | 2017-07-05 18:05:08 +0530 | [diff] [blame] | 534 | fsl_fdt_fixup_flash(blob); |
| 535 | |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 536 | #ifdef CONFIG_FSL_MC_ENET |
| 537 | fdt_fixup_board_enet(blob); |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 538 | #endif |
| 539 | |
Laurentiu Tudor | 4adff39 | 2019-10-18 09:01:54 +0000 | [diff] [blame] | 540 | fdt_fixup_icid(blob); |
| 541 | |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 542 | return 0; |
| 543 | } |
| 544 | #endif |
| 545 | |
| 546 | void qixis_dump_switch(void) |
| 547 | { |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 548 | #ifdef CONFIG_FSL_QIXIS |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 549 | int i, nr_of_cfgsw; |
| 550 | |
| 551 | QIXIS_WRITE(cms[0], 0x00); |
| 552 | nr_of_cfgsw = QIXIS_READ(cms[1]); |
| 553 | |
| 554 | puts("DIP switch settings dump:\n"); |
| 555 | for (i = 1; i <= nr_of_cfgsw; i++) { |
| 556 | QIXIS_WRITE(cms[0], i); |
| 557 | printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
| 558 | } |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 559 | #endif |
York Sun | e12abcb | 2015-03-20 19:28:24 -0700 | [diff] [blame] | 560 | } |
York Sun | ac192a9 | 2015-05-28 14:54:09 +0530 | [diff] [blame] | 561 | |
| 562 | /* |
| 563 | * Board rev C and earlier has duplicated I2C addresses for 2nd controller. |
| 564 | * Both slots has 0x54, resulting 2nd slot unusable. |
| 565 | */ |
| 566 | void update_spd_address(unsigned int ctrl_num, |
| 567 | unsigned int slot, |
| 568 | unsigned int *addr) |
| 569 | { |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 570 | #ifndef CONFIG_TARGET_LS2081ARDB |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 571 | #ifdef CONFIG_FSL_QIXIS |
York Sun | ac192a9 | 2015-05-28 14:54:09 +0530 | [diff] [blame] | 572 | u8 sw; |
| 573 | |
| 574 | sw = QIXIS_READ(arch); |
| 575 | if ((sw & 0xf) < 0x3) { |
| 576 | if (ctrl_num == 1 && slot == 0) |
| 577 | *addr = SPD_EEPROM_ADDRESS4; |
| 578 | else if (ctrl_num == 1 && slot == 1) |
| 579 | *addr = SPD_EEPROM_ADDRESS3; |
| 580 | } |
Priyanka Jain | 6720d0a | 2017-04-28 10:41:34 +0530 | [diff] [blame] | 581 | #endif |
Priyanka Jain | 75cd67f | 2017-04-27 15:08:07 +0530 | [diff] [blame] | 582 | #endif |
York Sun | ac192a9 | 2015-05-28 14:54:09 +0530 | [diff] [blame] | 583 | } |