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Chen-Yu Tsai3a045422014-10-03 20:16:25 +08001/*
2 * sun6i specific clock code
3 *
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
14#include <asm/io.h>
15#include <asm/arch/clock.h>
Chen-Yu Tsai6ee63882014-10-22 16:47:47 +080016#include <asm/arch/prcm.h>
Chen-Yu Tsai3a045422014-10-03 20:16:25 +080017#include <asm/arch/sys_proto.h>
18
Hans de Goedec27d68d2014-10-25 20:16:33 +020019#ifdef CONFIG_SPL_BUILD
20void clock_init_safe(void)
21{
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24 struct sunxi_prcm_reg * const prcm =
25 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
26
27 /* Set PLL ldo voltage without this PLL6 does not work properly */
28 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
29 PRCM_PLL_CTRL_LDO_KEY);
30 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
31 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
32 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
33 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
34
35 clock_set_pll1(408000000);
36
Hans de Goedec27d68d2014-10-25 20:16:33 +020037 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
Siarhei Siamashka2b8bd912015-11-20 07:07:48 +020038 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
39 ;
40
41 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
Hans de Goedec27d68d2014-10-25 20:16:33 +020042
43 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
44 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
45}
46#endif
47
Chen-Yu Tsai6daddfe2016-01-06 15:13:07 +080048void clock_init_sec(void)
49{
50#ifdef CONFIG_MACH_SUN8I_H3
51 struct sunxi_ccm_reg * const ccm =
52 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
53
54 setbits_le32(&ccm->ccu_sec_switch,
55 CCM_SEC_SWITCH_MBUS_NONSEC |
56 CCM_SEC_SWITCH_BUS_NONSEC |
57 CCM_SEC_SWITCH_PLL_NONSEC);
58#endif
59}
60
Chen-Yu Tsai3a045422014-10-03 20:16:25 +080061void clock_init_uart(void)
62{
Hans de Goede627bc692015-01-14 19:28:38 +010063#if CONFIG_CONS_INDEX < 5
Chen-Yu Tsai3a045422014-10-03 20:16:25 +080064 struct sunxi_ccm_reg *const ccm =
65 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
66
67 /* uart clock source is apb2 */
68 writel(APB2_CLK_SRC_OSC24M|
69 APB2_CLK_RATE_N_1|
70 APB2_CLK_RATE_M(1),
71 &ccm->apb2_div);
72
73 /* open the clock for uart */
74 setbits_le32(&ccm->apb2_gate,
75 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
76 CONFIG_CONS_INDEX - 1));
77
78 /* deassert uart reset */
79 setbits_le32(&ccm->apb2_reset_cfg,
80 1 << (APB2_RESET_UART_SHIFT +
81 CONFIG_CONS_INDEX - 1));
Chen-Yu Tsai6ee63882014-10-22 16:47:47 +080082#else
83 /* enable R_PIO and R_UART clocks, and de-assert resets */
84 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
85#endif
Chen-Yu Tsai3a045422014-10-03 20:16:25 +080086}
87
88int clock_twi_onoff(int port, int state)
89{
90 struct sunxi_ccm_reg *const ccm =
91 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
92
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +010093 if (port == 5) {
94 if (state)
95 prcm_apb0_enable(
96 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
97 else
98 prcm_apb0_disable(
99 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
100 return 0;
101 }
102
Chen-Yu Tsai3a045422014-10-03 20:16:25 +0800103 /* set the apb clock gate for twi */
104 if (state)
105 setbits_le32(&ccm->apb2_gate,
106 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
107 else
108 clrbits_le32(&ccm->apb2_gate,
109 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
110
111 return 0;
112}
113
Hans de Goedec27d68d2014-10-25 20:16:33 +0200114#ifdef CONFIG_SPL_BUILD
115void clock_set_pll1(unsigned int clk)
116{
117 struct sunxi_ccm_reg * const ccm =
118 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goede645d4d52014-12-27 17:56:59 +0100119 const int p = 0;
Hans de Goedec27d68d2014-10-25 20:16:33 +0200120 int k = 1;
121 int m = 1;
122
123 if (clk > 1152000000) {
124 k = 2;
125 } else if (clk > 768000000) {
126 k = 3;
127 m = 2;
128 }
129
130 /* Switch to 24MHz clock while changing PLL1 */
131 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
132 ATB_DIV_2 << ATB_DIV_SHIFT |
133 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
134 &ccm->cpu_axi_cfg);
135
Hans de Goede645d4d52014-12-27 17:56:59 +0100136 /*
137 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
138 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
139 */
140 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
Hans de Goedec27d68d2014-10-25 20:16:33 +0200141 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
142 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
143 sdelay(200);
144
145 /* Switch CPU to PLL1 */
146 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
147 ATB_DIV_2 << ATB_DIV_SHIFT |
148 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
149 &ccm->cpu_axi_cfg);
150}
151#endif
152
Hans de Goede70d7ab52014-11-08 14:07:27 +0100153void clock_set_pll3(unsigned int clk)
154{
155 struct sunxi_ccm_reg * const ccm =
156 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
157 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
158
159 if (clk == 0) {
160 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
161 return;
162 }
163
164 /* PLL3 rate = 24000000 * n / m */
165 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
166 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
167 &ccm->pll3_cfg);
168}
169
Hans de Goede0cbc4cb2014-11-30 11:58:17 +0100170void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
Hans de Goedec27d68d2014-10-25 20:16:33 +0200171{
172 struct sunxi_ccm_reg * const ccm =
173 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goede0bfa7742014-12-07 21:09:31 +0100174 const int max_n = 32;
175 int k = 1, m = 2;
Hans de Goedec27d68d2014-10-25 20:16:33 +0200176
Hans de Goede0cbc4cb2014-11-30 11:58:17 +0100177 if (sigma_delta_enable)
178 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
179
Hans de Goedec27d68d2014-10-25 20:16:33 +0200180 /* PLL5 rate = 24000000 * n * k / m */
Hans de Goede0bfa7742014-12-07 21:09:31 +0100181 if (clk > 24000000 * k * max_n / m) {
182 m = 1;
183 if (clk > 24000000 * k * max_n / m)
184 k = 2;
185 }
Hans de Goede0cbc4cb2014-11-30 11:58:17 +0100186 writel(CCM_PLL5_CTRL_EN |
187 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
188 CCM_PLL5_CTRL_UPD |
Hans de Goedec27d68d2014-10-25 20:16:33 +0200189 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
190 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
191
192 udelay(5500);
193}
194
Hans de Goeded6eaadc2015-08-08 14:05:35 +0200195#ifdef CONFIG_MACH_SUN6I
196void clock_set_mipi_pll(unsigned int clk)
197{
198 struct sunxi_ccm_reg * const ccm =
199 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
200 unsigned int k, m, n, value, diff;
201 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
202 unsigned int src = clock_get_pll3();
203
204 /* All calculations are in KHz to avoid overflows */
205 clk /= 1000;
206 src /= 1000;
207
208 /* Pick the closest lower clock */
209 for (k = 1; k <= 4; k++) {
210 for (m = 1; m <= 16; m++) {
211 for (n = 1; n <= 16; n++) {
212 value = src * n * k / m;
213 if (value > clk)
214 continue;
215
216 diff = clk - value;
217 if (diff < best_diff) {
218 best_diff = diff;
219 best_k = k;
220 best_m = m;
221 best_n = n;
222 }
223 if (diff == 0)
224 goto done;
225 }
226 }
227 }
228
229done:
230 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
231 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
232 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
233}
234#endif
235
Hans de Goede0fdbe202015-04-12 11:46:41 +0200236#ifdef CONFIG_MACH_SUN8I_A33
237void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
238{
239 struct sunxi_ccm_reg * const ccm =
240 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
241
242 if (sigma_delta_enable)
243 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
244
245 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
246 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
247 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
248
249 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
250 ;
251}
252#endif
253
Hans de Goede957a727292015-08-08 12:36:44 +0200254unsigned int clock_get_pll3(void)
255{
256 struct sunxi_ccm_reg *const ccm =
257 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
258 uint32_t rval = readl(&ccm->pll3_cfg);
259 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
260 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
261
262 /* Multiply by 1000 after dividing by m to avoid integer overflows */
263 return (24000 * n / m) * 1000;
264}
265
Chen-Yu Tsai3a045422014-10-03 20:16:25 +0800266unsigned int clock_get_pll6(void)
267{
268 struct sunxi_ccm_reg *const ccm =
269 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
270 uint32_t rval = readl(&ccm->pll6_cfg);
271 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
272 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
273 return 24000000 * n * k / 2;
274}
Hans de Goede70d7ab52014-11-08 14:07:27 +0100275
Hans de Goeded6eaadc2015-08-08 14:05:35 +0200276unsigned int clock_get_mipi_pll(void)
277{
278 struct sunxi_ccm_reg *const ccm =
279 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
280 uint32_t rval = readl(&ccm->mipi_pll_cfg);
281 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
282 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
283 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
284 unsigned int src = clock_get_pll3();
285
286 /* Multiply by 1000 after dividing by m to avoid integer overflows */
287 return ((src / 1000) * n * k / m) * 1000;
288}
289
Hans de Goede70d7ab52014-11-08 14:07:27 +0100290void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
291{
292 int pll = clock_get_pll6() * 2;
293 int div = 1;
294
295 while ((pll / div) > hz)
296 div++;
297
298 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
299 clk_cfg);
300}