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git01.mediatek.com / filogic / uboot / 9d1f6196dda01b9cc76d3a3ff3beb26f62e0a5d7 / . / arch / arm / mach-uniphier / clk / clk-pro4.c
blob: 2b364dca4100f197b159189a9cdbb1261a01eb7a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]2/*
Masahiro Yamadab4eda202016-10-17 22:18:03 +0900[diff] [blame]3 * Copyright (C) 2011-2015 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]6 */
7
Masahiro Yamada663a23f2015-05-29 17:30:00 +0900[diff] [blame]8#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]9
10#include "../init.h"
11#include "../sc-regs.h"
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]12
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]13void uniphier_pro4_clk_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]14{
15 u32 tmp;
16
17 /* deassert reset */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]18 tmp = readl(sc_base + SC_RSTCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]19#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada046d8fd2015-02-27 02:26:58 +0900[diff] [blame]20 tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
21 SC_RSTCTRL_NRST_GIO;
22#endif
Masahiro Yamadac04368f2015-02-27 02:26:51 +0900[diff] [blame]23#ifdef CONFIG_NAND_DENALI
24 tmp |= SC_RSTCTRL_NRST_NAND;
25#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]26 writel(tmp, sc_base + SC_RSTCTRL);
27 readl(sc_base + SC_RSTCTRL); /* dummy read */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]28
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]29#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]30 tmp = readl(sc_base + SC_RSTCTRL2);
Masahiro Yamada046d8fd2015-02-27 02:26:58 +0900[diff] [blame]31 tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]32 writel(tmp, sc_base + SC_RSTCTRL2);
33 readl(sc_base + SC_RSTCTRL2); /* dummy read */
Masahiro Yamada046d8fd2015-02-27 02:26:58 +0900[diff] [blame]34#endif
35
Masahiro Yamada1c6a5e42016-03-30 20:17:42 +0900[diff] [blame]36 /* provide clocks */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]37 tmp = readl(sc_base + SC_CLKCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]38#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada046d8fd2015-02-27 02:26:58 +0900[diff] [blame]39 tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
40 SC_CLKCTRL_CEN_GIO;
41#endif
Masahiro Yamadac04368f2015-02-27 02:26:51 +0900[diff] [blame]42#ifdef CONFIG_NAND_DENALI
43 tmp |= SC_CLKCTRL_CEN_NAND;
44#endif
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]45 writel(tmp, sc_base + SC_CLKCTRL);
46 readl(sc_base + SC_CLKCTRL); /* dummy read */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]47}