blob: 6226d55658eada14d9768468bff0de0a551958a1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass421358c2015-08-30 16:55:31 -06002/*
3 * (C) Copyright 2015 Google, Inc
Simon Glass421358c2015-08-30 16:55:31 -06004 */
5
6#include <common.h>
David Wu3c248b22017-09-20 14:28:19 +08007#include <bitfield.h>
Stephen Warrena9622432016-06-17 09:44:00 -06008#include <clk-uclass.h>
Simon Glasscf6741b2018-12-27 20:15:20 -07009#include <div64.h>
Simon Glass421358c2015-08-30 16:55:31 -060010#include <dm.h>
Simon Glass00c5fd42016-07-04 11:58:29 -060011#include <dt-structs.h>
Simon Glass421358c2015-08-30 16:55:31 -060012#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <malloc.h>
Simon Glass00c5fd42016-07-04 11:58:29 -060015#include <mapmem.h>
Simon Glass421358c2015-08-30 16:55:31 -060016#include <syscon.h>
17#include <asm/io.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080018#include <asm/arch-rockchip/clock.h>
Jagan Teki783acfd2020-01-09 14:22:17 +053019#include <asm/arch-rockchip/cru.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080020#include <asm/arch-rockchip/grf_rk3288.h>
21#include <asm/arch-rockchip/hardware.h>
Simon Glass8d32f4b2016-01-21 19:43:38 -070022#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass344f3662016-01-21 19:43:41 -070023#include <dm/device-internal.h>
Simon Glass421358c2015-08-30 16:55:31 -060024#include <dm/lists.h>
Simon Glass344f3662016-01-21 19:43:41 -070025#include <dm/uclass-internal.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060026#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060027#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070028#include <linux/err.h>
Heiko Stübner1b7dcc32016-07-22 23:51:06 +020029#include <linux/log2.h>
Simon Glassfb64e362020-05-10 11:40:09 -060030#include <linux/stringify.h>
Simon Glass421358c2015-08-30 16:55:31 -060031
32DECLARE_GLOBAL_DATA_PTR;
33
Simon Glass00c5fd42016-07-04 11:58:29 -060034struct rk3288_clk_plat {
35#if CONFIG_IS_ENABLED(OF_PLATDATA)
36 struct dtd_rockchip_rk3288_cru dtd;
37#endif
38};
39
Simon Glass421358c2015-08-30 16:55:31 -060040struct pll_div {
41 u32 nr;
42 u32 nf;
43 u32 no;
44};
45
46enum {
47 VCO_MAX_HZ = 2200U * 1000000,
48 VCO_MIN_HZ = 440 * 1000000,
49 OUTPUT_MAX_HZ = 2200U * 1000000,
50 OUTPUT_MIN_HZ = 27500000,
51 FREF_MAX_HZ = 2200U * 1000000,
Heiko Stübner7f78c242016-07-16 00:17:17 +020052 FREF_MIN_HZ = 269 * 1000,
Simon Glass421358c2015-08-30 16:55:31 -060053};
54
55enum {
56 /* PLL CON0 */
57 PLL_OD_MASK = 0x0f,
58
59 /* PLL CON1 */
60 PLL_NF_MASK = 0x1fff,
61
62 /* PLL CON2 */
63 PLL_BWADJ_MASK = 0x0fff,
64
65 /* PLL CON3 */
66 PLL_RESET_SHIFT = 5,
67
Simon Glass94906e42016-01-21 19:45:17 -070068 /* CLKSEL0 */
Simon Glass94906e42016-01-21 19:45:17 -070069 CORE_SEL_PLL_SHIFT = 15,
Simon Glass303384f2017-05-31 17:57:31 -060070 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
Simon Glass94906e42016-01-21 19:45:17 -070071 A17_DIV_SHIFT = 8,
Simon Glass303384f2017-05-31 17:57:31 -060072 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
Simon Glass94906e42016-01-21 19:45:17 -070073 MP_DIV_SHIFT = 4,
Simon Glass303384f2017-05-31 17:57:31 -060074 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
Simon Glass94906e42016-01-21 19:45:17 -070075 M0_DIV_SHIFT = 0,
Simon Glass303384f2017-05-31 17:57:31 -060076 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
Simon Glass94906e42016-01-21 19:45:17 -070077
Simon Glass421358c2015-08-30 16:55:31 -060078 /* CLKSEL1: pd bus clk pll sel: codec or general */
79 PD_BUS_SEL_PLL_MASK = 15,
80 PD_BUS_SEL_CPLL = 0,
81 PD_BUS_SEL_GPLL,
82
83 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
84 PD_BUS_PCLK_DIV_SHIFT = 12,
Simon Glass303384f2017-05-31 17:57:31 -060085 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -060086
87 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
88 PD_BUS_HCLK_DIV_SHIFT = 8,
Simon Glass303384f2017-05-31 17:57:31 -060089 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -060090
91 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
92 PD_BUS_ACLK_DIV0_SHIFT = 3,
Simon Glass303384f2017-05-31 17:57:31 -060093 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -060094 PD_BUS_ACLK_DIV1_SHIFT = 0,
Simon Glass303384f2017-05-31 17:57:31 -060095 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -060096
97 /*
98 * CLKSEL10
99 * peripheral bus pclk div:
100 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
101 */
Simon Glasse6a682b2016-01-21 19:45:15 -0700102 PERI_SEL_PLL_SHIFT = 15,
Simon Glass303384f2017-05-31 17:57:31 -0600103 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
Simon Glasse6a682b2016-01-21 19:45:15 -0700104 PERI_SEL_CPLL = 0,
105 PERI_SEL_GPLL,
106
Simon Glass421358c2015-08-30 16:55:31 -0600107 PERI_PCLK_DIV_SHIFT = 12,
Simon Glass303384f2017-05-31 17:57:31 -0600108 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -0600109
110 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
111 PERI_HCLK_DIV_SHIFT = 8,
Simon Glass303384f2017-05-31 17:57:31 -0600112 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -0600113
114 /*
115 * peripheral bus aclk div:
116 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
117 */
118 PERI_ACLK_DIV_SHIFT = 0,
Simon Glass303384f2017-05-31 17:57:31 -0600119 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
Simon Glass421358c2015-08-30 16:55:31 -0600120
David Wu3c248b22017-09-20 14:28:19 +0800121 /*
122 * CLKSEL24
123 * saradc_div_con:
124 * clk_saradc=24MHz/(saradc_div_con+1)
125 */
126 CLK_SARADC_DIV_CON_SHIFT = 8,
127 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
128 CLK_SARADC_DIV_CON_WIDTH = 8,
129
Simon Glass421358c2015-08-30 16:55:31 -0600130 SOCSTS_DPLL_LOCK = 1 << 5,
131 SOCSTS_APLL_LOCK = 1 << 6,
132 SOCSTS_CPLL_LOCK = 1 << 7,
133 SOCSTS_GPLL_LOCK = 1 << 8,
134 SOCSTS_NPLL_LOCK = 1 << 9,
135};
136
Simon Glass421358c2015-08-30 16:55:31 -0600137#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
138
139#define PLL_DIVISORS(hz, _nr, _no) {\
140 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
141 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
142 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
143 "divisors on line " __stringify(__LINE__));
144
145/* Keep divisors as low as possible to reduce jitter and power usage */
146static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
147static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
148static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
149
Jagan Teki783acfd2020-01-09 14:22:17 +0530150static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
Simon Glass421358c2015-08-30 16:55:31 -0600151 const struct pll_div *div)
152{
153 int pll_id = rk_pll_id(clk_id);
154 struct rk3288_pll *pll = &cru->pll[pll_id];
155 /* All PLLs have same VCO and output frequency range restrictions. */
156 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
157 uint output_hz = vco_hz / div->no;
158
Simon Glasse6a682b2016-01-21 19:45:15 -0700159 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
160 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
Simon Glass421358c2015-08-30 16:55:31 -0600161 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
162 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
163 (div->no == 1 || !(div->no % 2)));
164
Simon Glasse6a682b2016-01-21 19:45:15 -0700165 /* enter reset */
Simon Glass421358c2015-08-30 16:55:31 -0600166 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
167
Simon Glass303384f2017-05-31 17:57:31 -0600168 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600169 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
170 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
171 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
172
173 udelay(10);
174
Simon Glasse6a682b2016-01-21 19:45:15 -0700175 /* return from reset */
Simon Glass421358c2015-08-30 16:55:31 -0600176 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
177
178 return 0;
179}
180
Jagan Teki783acfd2020-01-09 14:22:17 +0530181static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
Simon Glass421358c2015-08-30 16:55:31 -0600182 unsigned int hz)
183{
184 static const struct pll_div dpll_cfg[] = {
185 {.nf = 25, .nr = 2, .no = 1},
186 {.nf = 400, .nr = 9, .no = 2},
187 {.nf = 500, .nr = 9, .no = 2},
188 {.nf = 100, .nr = 3, .no = 1},
189 };
190 int cfg;
191
Simon Glass421358c2015-08-30 16:55:31 -0600192 switch (hz) {
193 case 300000000:
194 cfg = 0;
195 break;
196 case 533000000: /* actually 533.3P MHz */
197 cfg = 1;
198 break;
199 case 666000000: /* actually 666.6P MHz */
200 cfg = 2;
201 break;
202 case 800000000:
203 cfg = 3;
204 break;
205 default:
Simon Glasse6a682b2016-01-21 19:45:15 -0700206 debug("Unsupported SDRAM frequency");
Simon Glass421358c2015-08-30 16:55:31 -0600207 return -EINVAL;
208 }
209
210 /* pll enter slow-mode */
Simon Glass303384f2017-05-31 17:57:31 -0600211 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600212 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
213
214 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
215
216 /* wait for pll lock */
217 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
218 udelay(1);
219
220 /* PLL enter normal-mode */
Simon Glass303384f2017-05-31 17:57:31 -0600221 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
Simon Glass5562bf12016-01-21 19:45:01 -0700222 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
Simon Glass421358c2015-08-30 16:55:31 -0600223
224 return 0;
225}
226
Simon Glass273afb22016-01-21 19:45:02 -0700227#ifndef CONFIG_SPL_BUILD
228#define VCO_MAX_KHZ 2200000
229#define VCO_MIN_KHZ 440000
230#define FREF_MAX_KHZ 2200000
231#define FREF_MIN_KHZ 269
232
233static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
234{
235 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
236 uint fref_khz;
237 uint diff_khz, best_diff_khz;
238 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
239 uint vco_khz;
240 uint no = 1;
241 uint freq_khz = freq_hz / 1000;
242
243 if (!freq_hz) {
244 printf("%s: the frequency can not be 0 Hz\n", __func__);
245 return -EINVAL;
246 }
247
248 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
249 if (ext_div) {
250 *ext_div = DIV_ROUND_UP(no, max_no);
251 no = DIV_ROUND_UP(no, *ext_div);
252 }
253
254 /* only even divisors (and 1) are supported */
255 if (no > 1)
256 no = DIV_ROUND_UP(no, 2) * 2;
257
258 vco_khz = freq_khz * no;
259 if (ext_div)
260 vco_khz *= *ext_div;
261
262 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
263 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
264 __func__, freq_hz);
265 return -1;
266 }
267
268 div->no = no;
269
270 best_diff_khz = vco_khz;
271 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
272 fref_khz = ref_khz / nr;
273 if (fref_khz < FREF_MIN_KHZ)
274 break;
275 if (fref_khz > FREF_MAX_KHZ)
276 continue;
277
278 nf = vco_khz / fref_khz;
279 if (nf >= max_nf)
280 continue;
281 diff_khz = vco_khz - nf * fref_khz;
282 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
283 nf++;
284 diff_khz = fref_khz - diff_khz;
285 }
286
287 if (diff_khz >= best_diff_khz)
288 continue;
289
290 best_diff_khz = diff_khz;
291 div->nr = nr;
292 div->nf = nf;
293 }
294
295 if (best_diff_khz > 4 * 1000) {
296 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
297 __func__, freq_hz, best_diff_khz * 1000);
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
Jagan Teki783acfd2020-01-09 14:22:17 +0530304static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
Sjoerd Simons3ce69bf2016-02-28 22:24:59 +0100305{
David Wu879d2fb2018-01-13 14:06:33 +0800306 ulong ret;
307
308 /*
309 * The gmac clock can be derived either from an external clock
310 * or can be generated from internally by a divider from SCLK_MAC.
311 */
312 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
313 /* An external clock will always generate the right rate... */
314 ret = freq;
315 } else {
316 u32 con = readl(&cru->cru_clksel_con[21]);
317 ulong pll_rate;
318 u8 div;
319
320 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
321 EMAC_PLL_SELECT_GENERAL)
322 pll_rate = GPLL_HZ;
323 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
324 EMAC_PLL_SELECT_CODEC)
325 pll_rate = CPLL_HZ;
326 else
327 pll_rate = NPLL_HZ;
328
329 div = DIV_ROUND_UP(pll_rate, freq) - 1;
330 if (div <= 0x1f)
331 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
332 div << MAC_DIV_CON_SHIFT);
333 else
334 debug("Unsupported div for gmac:%d\n", div);
335
336 return DIV_TO_RATE(pll_rate, div);
337 }
Sjoerd Simons3ce69bf2016-02-28 22:24:59 +0100338
David Wu879d2fb2018-01-13 14:06:33 +0800339 return ret;
Sjoerd Simons3ce69bf2016-02-28 22:24:59 +0100340}
341
Jagan Teki783acfd2020-01-09 14:22:17 +0530342static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
Simon Glass273afb22016-01-21 19:45:02 -0700343 int periph, unsigned int rate_hz)
344{
345 struct pll_div npll_config = {0};
346 u32 lcdc_div;
347 int ret;
348
349 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
350 if (ret)
351 return ret;
352
Simon Glass303384f2017-05-31 17:57:31 -0600353 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
Simon Glass273afb22016-01-21 19:45:02 -0700354 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
355 rkclk_set_pll(cru, CLK_NEW, &npll_config);
356
357 /* waiting for pll lock */
358 while (1) {
359 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
360 break;
361 udelay(1);
362 }
363
Simon Glass303384f2017-05-31 17:57:31 -0600364 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
Simon Glass273afb22016-01-21 19:45:02 -0700365 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
366
367 /* vop dclk source clk: npll,dclk_div: 1 */
368 switch (periph) {
369 case DCLK_VOP0:
370 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
371 (lcdc_div - 1) << 8 | 2 << 0);
372 break;
373 case DCLK_VOP1:
374 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
375 (lcdc_div - 1) << 8 | 2 << 6);
376 break;
377 }
378
379 return 0;
380}
Simon Glasscf6741b2018-12-27 20:15:20 -0700381
382static u32 rockchip_clk_gcd(u32 a, u32 b)
383{
384 while (b != 0) {
385 int r = b;
386
387 b = a % b;
388 a = r;
389 }
390 return a;
391}
392
Jagan Teki783acfd2020-01-09 14:22:17 +0530393static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
Simon Glasscf6741b2018-12-27 20:15:20 -0700394{
395 unsigned long long rate;
396 uint val;
397 int n, d;
398
399 val = readl(&cru->cru_clksel_con[8]);
400 n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
401 d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
402
403 rate = (unsigned long long)gclk_rate * n;
404 do_div(rate, d);
405
406 return (ulong)rate;
407}
408
Jagan Teki783acfd2020-01-09 14:22:17 +0530409static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
Simon Glasscf6741b2018-12-27 20:15:20 -0700410 uint freq)
411{
412 int n, d;
413 int v;
414
415 /* set frac divider */
416 v = rockchip_clk_gcd(gclk_rate, freq);
417 n = gclk_rate / v;
418 d = freq / v;
419 assert(freq == gclk_rate / n * d);
420 writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
421 &cru->cru_clksel_con[8]);
422
423 return rockchip_i2s_get_clk(cru, gclk_rate);
424}
Simon Glass30ca6a42017-05-31 17:57:32 -0600425#endif /* CONFIG_SPL_BUILD */
Simon Glass273afb22016-01-21 19:45:02 -0700426
Jagan Teki783acfd2020-01-09 14:22:17 +0530427static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
Simon Glass421358c2015-08-30 16:55:31 -0600428{
429 u32 aclk_div;
430 u32 hclk_div;
431 u32 pclk_div;
432
433 /* pll enter slow-mode */
434 rk_clrsetreg(&cru->cru_mode_con,
Simon Glass303384f2017-05-31 17:57:31 -0600435 GPLL_MODE_MASK | CPLL_MODE_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600436 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
437 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
438
439 /* init pll */
440 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
441 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
442
443 /* waiting for pll lock */
444 while ((readl(&grf->soc_status[1]) &
445 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
446 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
447 udelay(1);
448
449 /*
450 * pd_bus clock pll source selection and
451 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
452 */
453 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
454 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
455 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
456 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
457 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
458
459 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
460 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
461 PD_BUS_ACLK_HZ && pclk_div < 0x7);
462
463 rk_clrsetreg(&cru->cru_clksel_con[1],
Simon Glass303384f2017-05-31 17:57:31 -0600464 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
465 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600466 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
467 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
468 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
469 0 << 0);
470
471 /*
472 * peri clock pll source selection and
473 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
474 */
475 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
476 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
477
Heiko Stübner1b7dcc32016-07-22 23:51:06 +0200478 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
Simon Glass421358c2015-08-30 16:55:31 -0600479 assert((1 << hclk_div) * PERI_HCLK_HZ ==
480 PERI_ACLK_HZ && (hclk_div < 0x4));
481
Heiko Stübner1b7dcc32016-07-22 23:51:06 +0200482 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
Simon Glass421358c2015-08-30 16:55:31 -0600483 assert((1 << pclk_div) * PERI_PCLK_HZ ==
484 PERI_ACLK_HZ && (pclk_div < 0x4));
485
486 rk_clrsetreg(&cru->cru_clksel_con[10],
Simon Glass303384f2017-05-31 17:57:31 -0600487 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
488 PERI_ACLK_DIV_MASK,
Simon Glasse6a682b2016-01-21 19:45:15 -0700489 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
Simon Glass421358c2015-08-30 16:55:31 -0600490 pclk_div << PERI_PCLK_DIV_SHIFT |
491 hclk_div << PERI_HCLK_DIV_SHIFT |
492 aclk_div << PERI_ACLK_DIV_SHIFT);
493
494 /* PLL enter normal-mode */
495 rk_clrsetreg(&cru->cru_mode_con,
Simon Glass303384f2017-05-31 17:57:31 -0600496 GPLL_MODE_MASK | CPLL_MODE_MASK,
Simon Glass5562bf12016-01-21 19:45:01 -0700497 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
498 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
Simon Glass421358c2015-08-30 16:55:31 -0600499}
Simon Glass421358c2015-08-30 16:55:31 -0600500
Jagan Teki783acfd2020-01-09 14:22:17 +0530501void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
Simon Glass94906e42016-01-21 19:45:17 -0700502{
503 /* pll enter slow-mode */
Simon Glass303384f2017-05-31 17:57:31 -0600504 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
Simon Glass94906e42016-01-21 19:45:17 -0700505 APLL_MODE_SLOW << APLL_MODE_SHIFT);
506
507 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
508
509 /* waiting for pll lock */
510 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
511 udelay(1);
512
513 /*
514 * core clock pll source selection and
515 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
516 * core clock select apll, apll clk = 1800MHz
517 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
518 */
519 rk_clrsetreg(&cru->cru_clksel_con[0],
Simon Glass303384f2017-05-31 17:57:31 -0600520 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
521 M0_DIV_MASK,
Simon Glass94906e42016-01-21 19:45:17 -0700522 0 << A17_DIV_SHIFT |
523 3 << MP_DIV_SHIFT |
524 1 << M0_DIV_SHIFT);
525
526 /*
527 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
528 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
529 */
530 rk_clrsetreg(&cru->cru_clksel_con[37],
Simon Glass303384f2017-05-31 17:57:31 -0600531 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
532 PCLK_CORE_DBG_DIV_MASK,
Simon Glass94906e42016-01-21 19:45:17 -0700533 1 << CLK_L2RAM_DIV_SHIFT |
534 3 << ATCLK_CORE_DIV_CON_SHIFT |
535 3 << PCLK_CORE_DBG_DIV_SHIFT);
536
537 /* PLL enter normal-mode */
Simon Glass303384f2017-05-31 17:57:31 -0600538 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
Simon Glass94906e42016-01-21 19:45:17 -0700539 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
540}
541
Simon Glass421358c2015-08-30 16:55:31 -0600542/* Get pll rate by id */
Jagan Teki783acfd2020-01-09 14:22:17 +0530543static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
Simon Glass421358c2015-08-30 16:55:31 -0600544 enum rk_clk_id clk_id)
545{
546 uint32_t nr, no, nf;
547 uint32_t con;
548 int pll_id = rk_pll_id(clk_id);
549 struct rk3288_pll *pll = &cru->pll[pll_id];
550 static u8 clk_shift[CLK_COUNT] = {
Simon Glass5562bf12016-01-21 19:45:01 -0700551 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
552 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
Simon Glass421358c2015-08-30 16:55:31 -0600553 };
554 uint shift;
555
556 con = readl(&cru->cru_mode_con);
557 shift = clk_shift[clk_id];
Simon Glass303384f2017-05-31 17:57:31 -0600558 switch ((con >> shift) & CRU_MODE_MASK) {
Simon Glass5562bf12016-01-21 19:45:01 -0700559 case APLL_MODE_SLOW:
Simon Glass421358c2015-08-30 16:55:31 -0600560 return OSC_HZ;
Simon Glass5562bf12016-01-21 19:45:01 -0700561 case APLL_MODE_NORMAL:
Simon Glass421358c2015-08-30 16:55:31 -0600562 /* normal mode */
563 con = readl(&pll->con0);
Simon Glass303384f2017-05-31 17:57:31 -0600564 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
565 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
Simon Glass421358c2015-08-30 16:55:31 -0600566 con = readl(&pll->con1);
Simon Glass303384f2017-05-31 17:57:31 -0600567 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
Simon Glass421358c2015-08-30 16:55:31 -0600568
569 return (24 * nf / (nr * no)) * 1000000;
Simon Glass5562bf12016-01-21 19:45:01 -0700570 case APLL_MODE_DEEP:
Simon Glass421358c2015-08-30 16:55:31 -0600571 default:
572 return 32768;
573 }
574}
575
Jagan Teki783acfd2020-01-09 14:22:17 +0530576static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
Simon Glass8d32f4b2016-01-21 19:43:38 -0700577 int periph)
Simon Glass421358c2015-08-30 16:55:31 -0600578{
579 uint src_rate;
580 uint div, mux;
581 u32 con;
582
583 switch (periph) {
Simon Glass8d32f4b2016-01-21 19:43:38 -0700584 case HCLK_EMMC:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800585 case SCLK_EMMC:
Simon Glass421358c2015-08-30 16:55:31 -0600586 con = readl(&cru->cru_clksel_con[12]);
Simon Glass303384f2017-05-31 17:57:31 -0600587 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
588 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600589 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700590 case HCLK_SDMMC:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800591 case SCLK_SDMMC:
Simon Glass8d32f4b2016-01-21 19:43:38 -0700592 con = readl(&cru->cru_clksel_con[11]);
Simon Glass303384f2017-05-31 17:57:31 -0600593 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
594 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600595 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700596 case HCLK_SDIO0:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800597 case SCLK_SDIO0:
Simon Glass421358c2015-08-30 16:55:31 -0600598 con = readl(&cru->cru_clksel_con[12]);
Simon Glass303384f2017-05-31 17:57:31 -0600599 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
600 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600601 break;
602 default:
603 return -EINVAL;
604 }
605
Simon Glassafe0cb02016-01-21 19:43:39 -0700606 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
Simon Glass421358c2015-08-30 16:55:31 -0600607 return DIV_TO_RATE(src_rate, div);
608}
609
Jagan Teki783acfd2020-01-09 14:22:17 +0530610static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
Simon Glass8d32f4b2016-01-21 19:43:38 -0700611 int periph, uint freq)
Simon Glass421358c2015-08-30 16:55:31 -0600612{
613 int src_clk_div;
614 int mux;
615
Simon Glassafe0cb02016-01-21 19:43:39 -0700616 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
Kever Yang99b546d2017-07-27 12:54:01 +0800617 /* mmc clock default div 2 internal, need provide double in cru */
618 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
Simon Glass421358c2015-08-30 16:55:31 -0600619
620 if (src_clk_div > 0x3f) {
Kever Yang99b546d2017-07-27 12:54:01 +0800621 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
Kever Yangf20995b2017-07-27 12:54:02 +0800622 assert(src_clk_div < 0x40);
Simon Glass421358c2015-08-30 16:55:31 -0600623 mux = EMMC_PLL_SELECT_24MHZ;
624 assert((int)EMMC_PLL_SELECT_24MHZ ==
625 (int)MMC0_PLL_SELECT_24MHZ);
626 } else {
627 mux = EMMC_PLL_SELECT_GENERAL;
628 assert((int)EMMC_PLL_SELECT_GENERAL ==
629 (int)MMC0_PLL_SELECT_GENERAL);
630 }
631 switch (periph) {
Simon Glass8d32f4b2016-01-21 19:43:38 -0700632 case HCLK_EMMC:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800633 case SCLK_EMMC:
Simon Glass421358c2015-08-30 16:55:31 -0600634 rk_clrsetreg(&cru->cru_clksel_con[12],
Simon Glass303384f2017-05-31 17:57:31 -0600635 EMMC_PLL_MASK | EMMC_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600636 mux << EMMC_PLL_SHIFT |
637 (src_clk_div - 1) << EMMC_DIV_SHIFT);
638 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700639 case HCLK_SDMMC:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800640 case SCLK_SDMMC:
Simon Glass421358c2015-08-30 16:55:31 -0600641 rk_clrsetreg(&cru->cru_clksel_con[11],
Simon Glass303384f2017-05-31 17:57:31 -0600642 MMC0_PLL_MASK | MMC0_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600643 mux << MMC0_PLL_SHIFT |
644 (src_clk_div - 1) << MMC0_DIV_SHIFT);
645 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700646 case HCLK_SDIO0:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800647 case SCLK_SDIO0:
Simon Glass421358c2015-08-30 16:55:31 -0600648 rk_clrsetreg(&cru->cru_clksel_con[12],
Simon Glass303384f2017-05-31 17:57:31 -0600649 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600650 mux << SDIO0_PLL_SHIFT |
651 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
652 break;
653 default:
654 return -EINVAL;
655 }
656
Simon Glassafe0cb02016-01-21 19:43:39 -0700657 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
Simon Glass421358c2015-08-30 16:55:31 -0600658}
659
Jagan Teki783acfd2020-01-09 14:22:17 +0530660static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
Simon Glass8d32f4b2016-01-21 19:43:38 -0700661 int periph)
Simon Glass421358c2015-08-30 16:55:31 -0600662{
663 uint div, mux;
664 u32 con;
665
666 switch (periph) {
Simon Glass8d32f4b2016-01-21 19:43:38 -0700667 case SCLK_SPI0:
Simon Glass421358c2015-08-30 16:55:31 -0600668 con = readl(&cru->cru_clksel_con[25]);
Simon Glass303384f2017-05-31 17:57:31 -0600669 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
670 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600671 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700672 case SCLK_SPI1:
Simon Glass421358c2015-08-30 16:55:31 -0600673 con = readl(&cru->cru_clksel_con[25]);
Simon Glass303384f2017-05-31 17:57:31 -0600674 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
675 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600676 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700677 case SCLK_SPI2:
Simon Glass421358c2015-08-30 16:55:31 -0600678 con = readl(&cru->cru_clksel_con[39]);
Simon Glass303384f2017-05-31 17:57:31 -0600679 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
680 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
Simon Glass421358c2015-08-30 16:55:31 -0600681 break;
682 default:
683 return -EINVAL;
684 }
685 assert(mux == SPI0_PLL_SELECT_GENERAL);
686
Simon Glassafe0cb02016-01-21 19:43:39 -0700687 return DIV_TO_RATE(gclk_rate, div);
Simon Glass421358c2015-08-30 16:55:31 -0600688}
689
Jagan Teki783acfd2020-01-09 14:22:17 +0530690static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
Simon Glass8d32f4b2016-01-21 19:43:38 -0700691 int periph, uint freq)
Simon Glass421358c2015-08-30 16:55:31 -0600692{
693 int src_clk_div;
694
Simon Glassafe0cb02016-01-21 19:43:39 -0700695 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
Kever Yangf20995b2017-07-27 12:54:02 +0800696 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
697 assert(src_clk_div < 128);
Simon Glass421358c2015-08-30 16:55:31 -0600698 switch (periph) {
Simon Glass8d32f4b2016-01-21 19:43:38 -0700699 case SCLK_SPI0:
Simon Glass421358c2015-08-30 16:55:31 -0600700 rk_clrsetreg(&cru->cru_clksel_con[25],
Simon Glass303384f2017-05-31 17:57:31 -0600701 SPI0_PLL_MASK | SPI0_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600702 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
703 src_clk_div << SPI0_DIV_SHIFT);
704 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700705 case SCLK_SPI1:
Simon Glass421358c2015-08-30 16:55:31 -0600706 rk_clrsetreg(&cru->cru_clksel_con[25],
Simon Glass303384f2017-05-31 17:57:31 -0600707 SPI1_PLL_MASK | SPI1_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600708 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
709 src_clk_div << SPI1_DIV_SHIFT);
710 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700711 case SCLK_SPI2:
Simon Glass421358c2015-08-30 16:55:31 -0600712 rk_clrsetreg(&cru->cru_clksel_con[39],
Simon Glass303384f2017-05-31 17:57:31 -0600713 SPI2_PLL_MASK | SPI2_DIV_MASK,
Simon Glass421358c2015-08-30 16:55:31 -0600714 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
715 src_clk_div << SPI2_DIV_SHIFT);
716 break;
717 default:
718 return -EINVAL;
719 }
720
Simon Glassafe0cb02016-01-21 19:43:39 -0700721 return rockchip_spi_get_clk(cru, gclk_rate, periph);
Simon Glass421358c2015-08-30 16:55:31 -0600722}
723
Jagan Teki783acfd2020-01-09 14:22:17 +0530724static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
David Wu3c248b22017-09-20 14:28:19 +0800725{
726 u32 div, val;
727
728 val = readl(&cru->cru_clksel_con[24]);
729 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
730 CLK_SARADC_DIV_CON_WIDTH);
731
732 return DIV_TO_RATE(OSC_HZ, div);
733}
734
Jagan Teki783acfd2020-01-09 14:22:17 +0530735static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
David Wu3c248b22017-09-20 14:28:19 +0800736{
737 int src_clk_div;
738
739 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
740 assert(src_clk_div < 128);
741
742 rk_clrsetreg(&cru->cru_clksel_con[24],
743 CLK_SARADC_DIV_CON_MASK,
744 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
745
746 return rockchip_saradc_get_clk(cru);
747}
748
Stephen Warrena9622432016-06-17 09:44:00 -0600749static ulong rk3288_clk_get_rate(struct clk *clk)
Simon Glass398ced12016-01-21 19:43:40 -0700750{
Stephen Warrena9622432016-06-17 09:44:00 -0600751 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
Simon Glass398ced12016-01-21 19:43:40 -0700752 ulong new_rate, gclk_rate;
Simon Glass398ced12016-01-21 19:43:40 -0700753
Stephen Warrena9622432016-06-17 09:44:00 -0600754 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
755 switch (clk->id) {
756 case 0 ... 63:
757 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
758 break;
Simon Glass398ced12016-01-21 19:43:40 -0700759 case HCLK_EMMC:
Simon Glassd4a8a682016-01-21 19:43:45 -0700760 case HCLK_SDMMC:
Simon Glass398ced12016-01-21 19:43:40 -0700761 case HCLK_SDIO0:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800762 case SCLK_EMMC:
763 case SCLK_SDMMC:
764 case SCLK_SDIO0:
Stephen Warrena9622432016-06-17 09:44:00 -0600765 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
Simon Glass398ced12016-01-21 19:43:40 -0700766 break;
767 case SCLK_SPI0:
768 case SCLK_SPI1:
769 case SCLK_SPI2:
Stephen Warrena9622432016-06-17 09:44:00 -0600770 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
Simon Glass398ced12016-01-21 19:43:40 -0700771 break;
772 case PCLK_I2C0:
773 case PCLK_I2C1:
774 case PCLK_I2C2:
775 case PCLK_I2C3:
776 case PCLK_I2C4:
777 case PCLK_I2C5:
778 return gclk_rate;
Kever Yang40514622016-08-12 17:57:05 +0800779 case PCLK_PWM:
780 return PD_BUS_PCLK_HZ;
David Wu3c248b22017-09-20 14:28:19 +0800781 case SCLK_SARADC:
782 new_rate = rockchip_saradc_get_clk(priv->cru);
783 break;
Simon Glass398ced12016-01-21 19:43:40 -0700784 default:
785 return -ENOENT;
786 }
787
788 return new_rate;
789}
790
Stephen Warrena9622432016-06-17 09:44:00 -0600791static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
Simon Glass421358c2015-08-30 16:55:31 -0600792{
Stephen Warrena9622432016-06-17 09:44:00 -0600793 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
Jagan Teki783acfd2020-01-09 14:22:17 +0530794 struct rockchip_cru *cru = priv->cru;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700795 ulong new_rate, gclk_rate;
Simon Glass421358c2015-08-30 16:55:31 -0600796
Stephen Warrena9622432016-06-17 09:44:00 -0600797 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
798 switch (clk->id) {
Simon Glasscb1c7af2016-11-13 14:22:13 -0700799 case PLL_APLL:
800 /* We only support a fixed rate here */
801 if (rate != 1800000000)
802 return -EINVAL;
803 rk3288_clk_configure_cpu(priv->cru, priv->grf);
804 new_rate = rate;
805 break;
Stephen Warrena9622432016-06-17 09:44:00 -0600806 case CLK_DDR:
807 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
808 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700809 case HCLK_EMMC:
810 case HCLK_SDMMC:
811 case HCLK_SDIO0:
Xu Ziyuan42118e42017-04-16 17:44:45 +0800812 case SCLK_EMMC:
813 case SCLK_SDMMC:
814 case SCLK_SDIO0:
Stephen Warrena9622432016-06-17 09:44:00 -0600815 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
Simon Glass421358c2015-08-30 16:55:31 -0600816 break;
Simon Glass8d32f4b2016-01-21 19:43:38 -0700817 case SCLK_SPI0:
818 case SCLK_SPI1:
819 case SCLK_SPI2:
Stephen Warrena9622432016-06-17 09:44:00 -0600820 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
Simon Glass273afb22016-01-21 19:45:02 -0700821 break;
822#ifndef CONFIG_SPL_BUILD
Simon Glasscf6741b2018-12-27 20:15:20 -0700823 case SCLK_I2S0:
824 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
825 break;
Sjoerd Simons3ce69bf2016-02-28 22:24:59 +0100826 case SCLK_MAC:
David Wu879d2fb2018-01-13 14:06:33 +0800827 new_rate = rockchip_mac_set_clk(priv->cru, rate);
Sjoerd Simons3ce69bf2016-02-28 22:24:59 +0100828 break;
Simon Glass273afb22016-01-21 19:45:02 -0700829 case DCLK_VOP0:
830 case DCLK_VOP1:
Stephen Warrena9622432016-06-17 09:44:00 -0600831 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
Simon Glass273afb22016-01-21 19:45:02 -0700832 break;
833 case SCLK_EDP_24M:
834 /* clk_edp_24M source: 24M */
835 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
836
837 /* rst edp */
838 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
839 udelay(1);
840 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
841 new_rate = rate;
842 break;
843 case ACLK_VOP0:
844 case ACLK_VOP1: {
845 u32 div;
846
847 /* vop aclk source clk: cpll */
848 div = CPLL_HZ / rate;
849 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
850
Stephen Warrena9622432016-06-17 09:44:00 -0600851 switch (clk->id) {
Simon Glass273afb22016-01-21 19:45:02 -0700852 case ACLK_VOP0:
853 rk_clrsetreg(&cru->cru_clksel_con[31],
854 3 << 6 | 0x1f << 0,
855 0 << 6 | (div - 1) << 0);
856 break;
857 case ACLK_VOP1:
858 rk_clrsetreg(&cru->cru_clksel_con[31],
859 3 << 14 | 0x1f << 8,
860 0 << 14 | (div - 1) << 8);
861 break;
862 }
863 new_rate = rate;
Simon Glass421358c2015-08-30 16:55:31 -0600864 break;
Simon Glass273afb22016-01-21 19:45:02 -0700865 }
866 case PCLK_HDMI_CTRL:
867 /* enable pclk hdmi ctrl */
868 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
869
870 /* software reset hdmi */
871 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
872 udelay(1);
873 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
874 new_rate = rate;
875 break;
876#endif
David Wu3c248b22017-09-20 14:28:19 +0800877 case SCLK_SARADC:
878 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
879 break;
David Wu879d2fb2018-01-13 14:06:33 +0800880 case PLL_GPLL:
881 case PLL_CPLL:
882 case PLL_NPLL:
883 case ACLK_CPU:
884 case HCLK_CPU:
885 case PCLK_CPU:
886 case ACLK_PERI:
887 case HCLK_PERI:
888 case PCLK_PERI:
889 case SCLK_UART0:
890 return 0;
Simon Glass421358c2015-08-30 16:55:31 -0600891 default:
892 return -ENOENT;
893 }
894
895 return new_rate;
896}
897
Philipp Tomsich6dd2fb42018-01-25 15:27:10 +0100898static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
David Wu879d2fb2018-01-13 14:06:33 +0800899{
900 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
Jagan Teki783acfd2020-01-09 14:22:17 +0530901 struct rockchip_cru *cru = priv->cru;
David Wu879d2fb2018-01-13 14:06:33 +0800902 const char *clock_output_name;
903 int ret;
904
905 /*
906 * If the requested parent is in the same clock-controller and
907 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
908 * clock.
909 */
910 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
911 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
912 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
913 return 0;
914 }
915
916 /*
917 * Otherwise, we need to check the clock-output-names of the
918 * requested parent to see if the requested id is "ext_gmac".
919 */
920 ret = dev_read_string_index(parent->dev, "clock-output-names",
921 parent->id, &clock_output_name);
922 if (ret < 0)
923 return -ENODATA;
924
925 /* If this is "ext_gmac", switch to the external clock input */
926 if (!strcmp(clock_output_name, "ext_gmac")) {
927 debug("%s: switching GMAC to external clock\n", __func__);
928 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
929 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
930 return 0;
931 }
932
933 return -EINVAL;
934}
935
Philipp Tomsich6dd2fb42018-01-25 15:27:10 +0100936static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
David Wu879d2fb2018-01-13 14:06:33 +0800937{
938 switch (clk->id) {
939 case SCLK_MAC:
940 return rk3288_gmac_set_parent(clk, parent);
941 case SCLK_USBPHY480M_SRC:
942 return 0;
943 }
944
945 debug("%s: unsupported clk %ld\n", __func__, clk->id);
946 return -ENOENT;
947}
948
Simon Glass421358c2015-08-30 16:55:31 -0600949static struct clk_ops rk3288_clk_ops = {
950 .get_rate = rk3288_clk_get_rate,
951 .set_rate = rk3288_clk_set_rate,
Philipp Tomsich6dd2fb42018-01-25 15:27:10 +0100952#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
David Wu879d2fb2018-01-13 14:06:33 +0800953 .set_parent = rk3288_clk_set_parent,
Philipp Tomsich6dd2fb42018-01-25 15:27:10 +0100954#endif
Simon Glass421358c2015-08-30 16:55:31 -0600955};
956
Simon Glassaad29ae2020-12-03 16:55:21 -0700957static int rk3288_clk_of_to_plat(struct udevice *dev)
Simon Glass421358c2015-08-30 16:55:31 -0600958{
Simon Glass00c5fd42016-07-04 11:58:29 -0600959#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass421358c2015-08-30 16:55:31 -0600960 struct rk3288_clk_priv *priv = dev_get_priv(dev);
961
Kever Yang08ffa442018-02-11 11:53:08 +0800962 priv->cru = dev_read_addr_ptr(dev);
Simon Glass00c5fd42016-07-04 11:58:29 -0600963#endif
Simon Glass994c29d2016-07-04 11:58:28 -0600964
965 return 0;
966}
967
968static int rk3288_clk_probe(struct udevice *dev)
969{
970 struct rk3288_clk_priv *priv = dev_get_priv(dev);
Simon Glass30ca6a42017-05-31 17:57:32 -0600971 bool init_clocks = false;
Simon Glass994c29d2016-07-04 11:58:28 -0600972
Simon Glass421358c2015-08-30 16:55:31 -0600973 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Simon Glass994c29d2016-07-04 11:58:28 -0600974 if (IS_ERR(priv->grf))
975 return PTR_ERR(priv->grf);
Simon Glass421358c2015-08-30 16:55:31 -0600976#ifdef CONFIG_SPL_BUILD
Simon Glass00c5fd42016-07-04 11:58:29 -0600977#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassfa20e932020-12-03 16:55:20 -0700978 struct rk3288_clk_plat *plat = dev_get_plat(dev);
Simon Glass00c5fd42016-07-04 11:58:29 -0600979
980 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
981#endif
Simon Glass30ca6a42017-05-31 17:57:32 -0600982 init_clocks = true;
Simon Glass421358c2015-08-30 16:55:31 -0600983#endif
Simon Glass30ca6a42017-05-31 17:57:32 -0600984 if (!(gd->flags & GD_FLG_RELOC)) {
985 u32 reg;
986
987 /*
988 * Init clocks in U-Boot proper if the NPLL is runnning. This
989 * indicates that a previous boot loader set up the clocks, so
990 * we need to redo it. U-Boot's SPL does not set this clock.
991 */
992 reg = readl(&priv->cru->cru_mode_con);
993 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
994 NPLL_MODE_NORMAL)
995 init_clocks = true;
996 }
997
998 if (init_clocks)
999 rkclk_init(priv->cru, priv->grf);
Simon Glass421358c2015-08-30 16:55:31 -06001000
1001 return 0;
1002}
1003
Simon Glass421358c2015-08-30 16:55:31 -06001004static int rk3288_clk_bind(struct udevice *dev)
1005{
Stephen Warrena9622432016-06-17 09:44:00 -06001006 int ret;
Kever Yang4fbb6c22017-11-03 15:16:13 +08001007 struct udevice *sys_child;
1008 struct sysreset_reg *priv;
Simon Glass421358c2015-08-30 16:55:31 -06001009
1010 /* The reset driver does not have a device node, so bind it here */
Kever Yang4fbb6c22017-11-03 15:16:13 +08001011 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1012 &sys_child);
1013 if (ret) {
1014 debug("Warning: No sysreset driver: ret=%d\n", ret);
1015 } else {
1016 priv = malloc(sizeof(struct sysreset_reg));
Jagan Teki783acfd2020-01-09 14:22:17 +05301017 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
Kever Yang4fbb6c22017-11-03 15:16:13 +08001018 cru_glb_srst_fst_value);
Jagan Teki783acfd2020-01-09 14:22:17 +05301019 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
Kever Yang4fbb6c22017-11-03 15:16:13 +08001020 cru_glb_srst_snd_value);
Simon Glass95588622020-12-22 19:30:28 -07001021 dev_set_priv(sys_child, priv);
Kever Yang4fbb6c22017-11-03 15:16:13 +08001022 }
Simon Glass421358c2015-08-30 16:55:31 -06001023
Heiko Stuebner416f8d32019-11-09 00:06:30 +01001024#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
Jagan Teki783acfd2020-01-09 14:22:17 +05301025 ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
Elaine Zhang432976f2017-12-19 18:22:38 +08001026 ret = rockchip_reset_bind(dev, ret, 12);
1027 if (ret)
1028 debug("Warning: software reset driver bind faile\n");
1029#endif
1030
Simon Glass421358c2015-08-30 16:55:31 -06001031 return 0;
1032}
1033
1034static const struct udevice_id rk3288_clk_ids[] = {
1035 { .compatible = "rockchip,rk3288-cru" },
1036 { }
1037};
1038
Simon Glass00c5fd42016-07-04 11:58:29 -06001039U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1040 .name = "rockchip_rk3288_cru",
Simon Glass421358c2015-08-30 16:55:31 -06001041 .id = UCLASS_CLK,
1042 .of_match = rk3288_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001043 .priv_auto = sizeof(struct rk3288_clk_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -07001044 .plat_auto = sizeof(struct rk3288_clk_plat),
Simon Glass421358c2015-08-30 16:55:31 -06001045 .ops = &rk3288_clk_ops,
1046 .bind = rk3288_clk_bind,
Simon Glassaad29ae2020-12-03 16:55:21 -07001047 .of_to_plat = rk3288_clk_of_to_plat,
Simon Glass421358c2015-08-30 16:55:31 -06001048 .probe = rk3288_clk_probe,
1049};