99b546da5d81bf03882b0f0e04a2c862ad3236b8 - filogic/uboot

commit	99b546da5d81bf03882b0f0e04a2c862ad3236b8	[log] [tgz]
author	Kever Yang <kever.yang@rock-chips.com>	Thu Jul 27 12:54:01 2017 +0800
committer	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>	Sun Aug 13 17:15:09 2017 +0200
tree	97eceee91df5dd3414f899062ec64041bf7257ed
parent	086a871bc5dadb7bd8748d7b425d8c3883fcb06c [diff]

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

drivers/clk/rockchip/clk_rk3036.c[diff]
drivers/clk/rockchip/clk_rk3188.c[diff]
drivers/clk/rockchip/clk_rk322x.c[diff]
drivers/clk/rockchip/clk_rk3288.c[diff]
drivers/clk/rockchip/clk_rk3328.c[diff]
drivers/clk/rockchip/clk_rk3399.c[diff]

6 files changed

tree: 97eceee91df5dd3414f899062ec64041bf7257ed