tree 97eceee91df5dd3414f899062ec64041bf7257ed
parent 086a871bc5dadb7bd8748d7b425d8c3883fcb06c
author Kever Yang <kever.yang@rock-chips.com> 1501131241 +0800
committer Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1502637309 +0200

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>