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git01.mediatek.com / filogic / uboot / 9ae65bd5444f1d6ef6201b02b94874fd407946a4 / . / drivers / ddr / fsl / Kconfig
blob: 277167060432cf5421296990c3e81e9bfca04ee7 [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]13if SYS_FSL_DDR || SYS_FSL_MMDC
14
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]15config SYS_FSL_DDR_BE
16 bool
17 help
18 Access DDR registers in big-endian
19
20config SYS_FSL_DDR_LE
21 bool
22 help
23 Access DDR registers in little-endian
24
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]25config FSL_DDR_BIST
26 bool
27
28config FSL_DDR_INTERACTIVE
29 bool
30
31config FSL_DDR_SYNC_REFRESH
32 bool
33
34config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
35 bool
36
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]37menu "Freescale DDR controllers"
38 depends on SYS_FSL_DDR
39
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]40config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]41 int "Maximum DDR controllers"
42 default 3 if ARCH_LS2080A || \
43 ARCH_T4240
44 default 2 if ARCH_B4860 || \
45 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]46 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]47 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]48 ARCH_LX2160A || \
Tom Rinia7ffa3d2021-05-23 10:58:05 -0400[diff] [blame]49 ARCH_LX2162A
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]50 default 1
51
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]52config CHIP_SELECTS_PER_CTRL
53 int "Number of chip selects per controller"
54 default 4
55
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]56config SYS_FSL_DDR_VER
57 int
58 default 50 if SYS_FSL_DDR_VER_50
59 default 47 if SYS_FSL_DDR_VER_47
60 default 46 if SYS_FSL_DDR_VER_46
61 default 44 if SYS_FSL_DDR_VER_44
62
63config SYS_FSL_DDR_VER_50
64 bool
65
66config SYS_FSL_DDR_VER_47
67 bool
68
69config SYS_FSL_DDR_VER_46
70 bool
71
72config SYS_FSL_DDR_VER_44
73 bool
74
75config SYS_FSL_DDRC_GEN1
76 bool
77 help
78 Enable Freescale DDR controller.
79
80config SYS_FSL_DDRC_GEN2
81 bool
82 depends on !MPC86xx
83 help
84 Enable Freescale DDR2 controller.
85
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]86config SYS_FSL_DDRC_GEN3
87 bool
88 depends on PPC
89 help
90 Enable Freescale DDR3 controller for PowerPC SoCs.
91
92config SYS_FSL_DDRC_ARM_GEN3
93 bool
94 depends on ARM
95 help
96 Enable Freescale DDR3 controller for ARM SoCs.
97
98config SYS_FSL_DDRC_GEN4
99 bool
100 help
101 Enable Freescale DDR4 controller.
102
103config SYS_FSL_HAS_DDR4
104 bool
105
106config SYS_FSL_HAS_DDR3
107 bool
108
109config SYS_FSL_HAS_DDR2
110 bool
111
112config SYS_FSL_HAS_DDR1
113 bool
114
115choice
116 prompt "DDR technology"
117 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
118 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
119 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
120 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
121
122config SYS_FSL_DDR4
123 bool "Freescale DDR4 controller"
124 depends on SYS_FSL_HAS_DDR4
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]125 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]126 select SYS_FSL_DDRC_GEN4
127
128config SYS_FSL_DDR3
129 bool "Freescale DDR3 controller"
130 depends on SYS_FSL_HAS_DDR3
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]131 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]132 select SYS_FSL_DDRC_GEN3 if PPC
133 select SYS_FSL_DDRC_ARM_GEN3 if ARM
134
135config SYS_FSL_DDR2
136 bool "Freescale DDR2 controller"
137 depends on SYS_FSL_HAS_DDR2
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]138 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]139 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]140
141config SYS_FSL_DDR1
142 bool "Freescale DDR1 controller"
143 depends on SYS_FSL_HAS_DDR1
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]144 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]145 select SYS_FSL_DDRC_GEN1
146
147endchoice
148
149endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]150
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]151config FSL_DMA
152 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
153
154config DDR_ECC
155 bool "ECC DDR memory support"
156
157config DDR_ECC_CMD
158 bool "Access the ECC features of the memory controller"
159 depends on DDR_ECC && MPC83xx
160 default y
161
162config ECC_INIT_VIA_DDRCONTROLLER
163 bool "DDR Memory controller initializes memory."
164 help
165 Use the DDR controller to auto initialize memory. If not enabled,
166 the DMA controller is responsible for doing this.
167
168endif
169
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]170menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
171 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
172
173config SYS_BR0_PRELIM_BOOL
174 bool "Define Bank 0"
175
176config SYS_BR0_PRELIM
177 hex "Preliminary value for BR0"
178 depends on SYS_BR0_PRELIM_BOOL
179
180config SYS_OR0_PRELIM
181 hex "Preliminary value for OR0"
182 depends on SYS_BR0_PRELIM_BOOL
183
184config SYS_BR1_PRELIM_BOOL
185 bool "Define Bank 1"
186
187config SYS_BR1_PRELIM
188 hex "Preliminary value for BR1"
189 depends on SYS_BR1_PRELIM_BOOL
190
191config SYS_OR1_PRELIM
192 hex "Preliminary value for OR1"
193 depends on SYS_BR1_PRELIM_BOOL
194
195config SYS_BR2_PRELIM_BOOL
196 bool "Define Bank 2"
197
198config SYS_BR2_PRELIM
199 hex "Preliminary value for BR2"
200 depends on SYS_BR2_PRELIM_BOOL
201
202config SYS_OR2_PRELIM
203 hex "Preliminary value for OR2"
204 depends on SYS_BR2_PRELIM_BOOL
205
206config SYS_BR3_PRELIM_BOOL
207 bool "Define Bank 3"
208
209config SYS_BR3_PRELIM
210 hex "Preliminary value for BR3"
211 depends on SYS_BR3_PRELIM_BOOL
212
213config SYS_OR3_PRELIM
214 hex "Preliminary value for OR3"
215 depends on SYS_BR3_PRELIM_BOOL
216
217config SYS_BR4_PRELIM_BOOL
218 bool "Define Bank 4"
219
220config SYS_BR4_PRELIM
221 hex "Preliminary value for BR4"
222 depends on SYS_BR4_PRELIM_BOOL
223
224config SYS_OR4_PRELIM
225 hex "Preliminary value for OR4"
226 depends on SYS_BR4_PRELIM_BOOL
227
228config SYS_BR5_PRELIM_BOOL
229 bool "Define Bank 5"
230
231config SYS_BR5_PRELIM
232 hex "Preliminary value for BR5"
233 depends on SYS_BR5_PRELIM_BOOL
234
235config SYS_OR5_PRELIM
236 hex "Preliminary value for OR5"
237 depends on SYS_BR5_PRELIM_BOOL
238
239config SYS_BR6_PRELIM_BOOL
240 bool "Define Bank 6"
241
242config SYS_BR6_PRELIM
243 hex "Preliminary value for BR6"
244 depends on SYS_BR6_PRELIM_BOOL
245
246config SYS_OR6_PRELIM
247 hex "Preliminary value for OR6"
248 depends on SYS_BR6_PRELIM_BOOL
249
250config SYS_BR7_PRELIM_BOOL
251 bool "Define Bank 7"
252
253config SYS_BR7_PRELIM
254 hex "Preliminary value for BR7"
255 depends on SYS_BR7_PRELIM_BOOL
256
257config SYS_OR7_PRELIM
258 hex "Preliminary value for OR7"
259 depends on SYS_BR7_PRELIM_BOOL
260endmenu
261
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]262config SYS_FSL_ERRATUM_A008378
263 bool
264
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]265config SYS_FSL_ERRATUM_A008109
266 bool
267
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]268config SYS_FSL_ERRATUM_A008511
269 bool
270
271config SYS_FSL_ERRATUM_A009663
272 bool
273
274config SYS_FSL_ERRATUM_A009801
275 bool
276
277config SYS_FSL_ERRATUM_A009803
278 bool
279
280config SYS_FSL_ERRATUM_A009942
281 bool
282
283config SYS_FSL_ERRATUM_A010165
284 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]285
286config SYS_FSL_ERRATUM_NMG_DDR120
287 bool
288
289config SYS_FSL_ERRATUM_DDR_115
290 bool
291
292config SYS_FSL_ERRATUM_DDR111_DDR134
293 bool
294
295config SYS_FSL_ERRATUM_DDR_A003
296 bool
297
298config SYS_FSL_ERRATUM_DDR_A003474
299 bool