blob: 9231cca9e95d6200f9f9dd3b6ccc38ee5e8b993e [file] [log] [blame]
Shaohui Xie085ac1c2016-09-07 17:56:14 +08001/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1046AQDS_H__
8#define __LS1046AQDS_H__
9
10#include "ls1046a_common.h"
11
Shaohui Xie085ac1c2016-09-07 17:56:14 +080012#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13#define CONFIG_SYS_TEXT_BASE 0x82000000
14#elif defined(CONFIG_QSPI_BOOT)
Alison Wang42f37802017-05-16 10:45:59 +080015#define CONFIG_SYS_TEXT_BASE 0x40100000
Shaohui Xie085ac1c2016-09-07 17:56:14 +080016#else
17#define CONFIG_SYS_TEXT_BASE 0x60100000
18#endif
19
20#ifndef __ASSEMBLY__
21unsigned long get_board_sys_clk(void);
22unsigned long get_board_ddr_clk(void);
23#endif
24
25#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
27
28#define CONFIG_SKIP_LOWLEVEL_INIT
29
30#define CONFIG_LAYERSCAPE_NS_ACCESS
31
32#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33/* Physical Memory Map */
34#define CONFIG_CHIP_SELECTS_PER_CTRL 4
35#define CONFIG_NR_DRAM_BANKS 2
36
37#define CONFIG_DDR_SPD
38#define SPD_EEPROM_ADDRESS 0x51
39#define CONFIG_SYS_SPD_BUS_NUM 0
40
Hou Zhiqianga43c3ac2017-02-06 11:29:00 +080041#ifndef CONFIG_SPL
Shaohui Xie085ac1c2016-09-07 17:56:14 +080042#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Hou Zhiqianga43c3ac2017-02-06 11:29:00 +080043#endif
Shaohui Xie085ac1c2016-09-07 17:56:14 +080044
45#define CONFIG_DDR_ECC
46#ifdef CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#endif
50
Shaohui Xie085ac1c2016-09-07 17:56:14 +080051/* DSPI */
52#ifdef CONFIG_FSL_DSPI
53#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
54#define CONFIG_SPI_FLASH_SST /* cs1 */
55#define CONFIG_SPI_FLASH_EON /* cs2 */
56#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
57#define CONFIG_SF_DEFAULT_BUS 1
58#define CONFIG_SF_DEFAULT_CS 0
59#endif
60#endif
61
62/* QSPI */
63#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
64#ifdef CONFIG_FSL_QSPI
65#define CONFIG_SPI_FLASH_SPANSION
66#define FSL_QSPI_FLASH_SIZE (1 << 24)
67#define FSL_QSPI_FLASH_NUM 2
68#endif
69#endif
70
71#ifdef CONFIG_SYS_DPAA_FMAN
72#define CONFIG_FMAN_ENET
Shaohui Xie085ac1c2016-09-07 17:56:14 +080073#define CONFIG_PHY_VITESSE
74#define CONFIG_PHY_REALTEK
75#define CONFIG_PHYLIB_10G
76#define RGMII_PHY1_ADDR 0x1
77#define RGMII_PHY2_ADDR 0x2
78#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
79#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
80#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
81#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
82/* PHY address on QSGMII riser card on slot 2 */
83#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
84#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
85#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
86#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
87#endif
88
89#ifdef CONFIG_RAMBOOT_PBL
90#define CONFIG_SYS_FSL_PBL_PBI \
91 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
92#endif
93
94#ifdef CONFIG_NAND_BOOT
95#define CONFIG_SYS_FSL_PBL_RCW \
96 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
97#endif
98
99#ifdef CONFIG_SD_BOOT
100#ifdef CONFIG_SD_BOOT_QSPI
101#define CONFIG_SYS_FSL_PBL_RCW \
102 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
103#else
104#define CONFIG_SYS_FSL_PBL_RCW \
105 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
106#endif
107#endif
108
109/* IFC */
110#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
111#define CONFIG_FSL_IFC
112/*
113 * CONFIG_SYS_FLASH_BASE has the final address (core view)
114 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
115 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
116 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
117 */
118#define CONFIG_SYS_FLASH_BASE 0x60000000
119#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
120#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
121
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900122#ifdef CONFIG_MTD_NOR_FLASH
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800123#define CONFIG_FLASH_CFI_DRIVER
124#define CONFIG_SYS_FLASH_CFI
125#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
126#define CONFIG_SYS_FLASH_QUIET_TEST
127#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
128#endif
129#endif
130
Shaohui Xie56007a02016-10-28 14:24:02 +0800131/* LPUART */
132#ifdef CONFIG_LPUART
133#define CONFIG_LPUART_32B_REG
134#define CFG_UART_MUX_MASK 0x6
135#define CFG_UART_MUX_SHIFT 1
136#define CFG_LPUART_EN 0x2
137#endif
138
Tang Yuantianbe1d2f32017-01-20 17:12:14 +0800139/* USB */
140#define CONFIG_HAS_FSL_XHCI_USB
141#ifdef CONFIG_HAS_FSL_XHCI_USB
Tang Yuantianbe1d2f32017-01-20 17:12:14 +0800142#define CONFIG_USB_XHCI_FSL
Tang Yuantianbe1d2f32017-01-20 17:12:14 +0800143#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Tang Yuantianbe1d2f32017-01-20 17:12:14 +0800144#endif
145
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800146/* SATA */
147#define CONFIG_LIBATA
148#define CONFIG_SCSI_AHCI
149#define CONFIG_SCSI_AHCI_PLAT
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800150
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800151/* EEPROM */
152#define CONFIG_ID_EEPROM
153#define CONFIG_SYS_I2C_EEPROM_NXID
154#define CONFIG_SYS_EEPROM_BUS_NUM 0
155#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
156#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
157#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
158#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
159
160#define CONFIG_SYS_SATA AHCI_BASE_ADDR
161
162#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
163#define CONFIG_SYS_SCSI_MAX_LUN 1
164#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
165 CONFIG_SYS_SCSI_MAX_LUN)
166
167/*
168 * IFC Definitions
169 */
170#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
171#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
172#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
173 CSPR_PORT_SIZE_16 | \
174 CSPR_MSEL_NOR | \
175 CSPR_V)
176#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
177#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
178 + 0x8000000) | \
179 CSPR_PORT_SIZE_16 | \
180 CSPR_MSEL_NOR | \
181 CSPR_V)
182#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
183
184#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
185 CSOR_NOR_TRHZ_80)
186#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
187 FTIM0_NOR_TEADC(0x5) | \
188 FTIM0_NOR_TEAHC(0x5))
189#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
190 FTIM1_NOR_TRAD_NOR(0x1a) | \
191 FTIM1_NOR_TSEQRAD_NOR(0x13))
192#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
193 FTIM2_NOR_TCH(0x4) | \
194 FTIM2_NOR_TWPH(0xe) | \
195 FTIM2_NOR_TWP(0x1c))
196#define CONFIG_SYS_NOR_FTIM3 0
197
198#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
199#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
200#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
201#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
202
203#define CONFIG_SYS_FLASH_EMPTY_INFO
204#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
205 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
206
207#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
208#define CONFIG_SYS_WRITE_SWAPPED_DATA
209
210/*
211 * NAND Flash Definitions
212 */
213#define CONFIG_NAND_FSL_IFC
214
215#define CONFIG_SYS_NAND_BASE 0x7e800000
216#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
217
218#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
219
220#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
221 | CSPR_PORT_SIZE_8 \
222 | CSPR_MSEL_NAND \
223 | CSPR_V)
224#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
225#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
226 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
227 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
228 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
229 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
230 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
231 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
232
233#define CONFIG_SYS_NAND_ONFI_DETECTION
234
235#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
236 FTIM0_NAND_TWP(0x18) | \
237 FTIM0_NAND_TWCHT(0x7) | \
238 FTIM0_NAND_TWH(0xa))
239#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
240 FTIM1_NAND_TWBE(0x39) | \
241 FTIM1_NAND_TRR(0xe) | \
242 FTIM1_NAND_TRP(0x18))
243#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
244 FTIM2_NAND_TREH(0xa) | \
245 FTIM2_NAND_TWHRE(0x1e))
246#define CONFIG_SYS_NAND_FTIM3 0x0
247
248#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
249#define CONFIG_SYS_MAX_NAND_DEVICE 1
250#define CONFIG_MTD_NAND_VERIFY_WRITE
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800251
252#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
253#endif
254
255#ifdef CONFIG_NAND_BOOT
256#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
257#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
258#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
259#endif
260
261#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
262#define CONFIG_QIXIS_I2C_ACCESS
263#define CONFIG_SYS_I2C_EARLY_INIT
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800264#endif
265
266/*
267 * QIXIS Definitions
268 */
269#define CONFIG_FSL_QIXIS
270
271#ifdef CONFIG_FSL_QIXIS
272#define QIXIS_BASE 0x7fb00000
273#define QIXIS_BASE_PHYS QIXIS_BASE
274#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
275#define QIXIS_LBMAP_SWITCH 6
276#define QIXIS_LBMAP_MASK 0x0f
277#define QIXIS_LBMAP_SHIFT 0
278#define QIXIS_LBMAP_DFLTBANK 0x00
279#define QIXIS_LBMAP_ALTBANK 0x04
280#define QIXIS_LBMAP_NAND 0x09
281#define QIXIS_LBMAP_SD 0x00
282#define QIXIS_LBMAP_SD_QSPI 0xff
283#define QIXIS_LBMAP_QSPI 0xff
284#define QIXIS_RCW_SRC_NAND 0x110
285#define QIXIS_RCW_SRC_SD 0x040
286#define QIXIS_RCW_SRC_QSPI 0x045
287#define QIXIS_RST_CTL_RESET 0x41
288#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
289#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
290#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
291
292#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
293#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
294 CSPR_PORT_SIZE_8 | \
295 CSPR_MSEL_GPCM | \
296 CSPR_V)
297#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
298#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
299 CSOR_NOR_NOR_MODE_AVD_NOR | \
300 CSOR_NOR_TRHZ_80)
301
302/*
303 * QIXIS Timing parameters for IFC GPCM
304 */
305#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
306 FTIM0_GPCM_TEADC(0x20) | \
307 FTIM0_GPCM_TEAHC(0x10))
308#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
309 FTIM1_GPCM_TRAD(0x1f))
310#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
311 FTIM2_GPCM_TCH(0x8) | \
312 FTIM2_GPCM_TWP(0xf0))
313#define CONFIG_SYS_FPGA_FTIM3 0x0
314#endif
315
316#ifdef CONFIG_NAND_BOOT
317#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
318#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
319#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
320#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
321#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
322#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
323#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
324#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
325#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
326#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
327#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
328#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
329#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
330#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
331#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
332#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
333#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
334#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
335#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
336#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
337#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
338#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
339#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
340#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
341#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
342#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
343#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
344#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
345#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
346#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
347#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
348#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
349#else
350#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
351#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
352#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
353#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
354#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
355#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
356#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
357#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
358#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
359#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
360#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
361#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
362#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
363#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
364#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
365#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
366#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
367#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
368#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
369#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
370#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
371#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
372#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
373#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
374#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
375#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
376#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
377#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
378#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
379#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
380#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
381#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
382#endif
383
384/*
385 * I2C bus multiplexer
386 */
387#define I2C_MUX_PCA_ADDR_PRI 0x77
388#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
389#define I2C_RETIMER_ADDR 0x18
390#define I2C_MUX_CH_DEFAULT 0x8
391#define I2C_MUX_CH_CH7301 0xC
392#define I2C_MUX_CH5 0xD
393#define I2C_MUX_CH6 0xE
394#define I2C_MUX_CH7 0xF
395
396#define I2C_MUX_CH_VOL_MONITOR 0xa
397
398/* Voltage monitor on channel 2*/
399#define I2C_VOL_MONITOR_ADDR 0x40
400#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
401#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
402#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
403
404#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
405#ifndef CONFIG_SPL_BUILD
406#define CONFIG_VID
407#endif
408#define CONFIG_VOL_MONITOR_IR36021_SET
409#define CONFIG_VOL_MONITOR_INA220
410/* The lowest and highest voltage allowed for LS1046AQDS */
411#define VDD_MV_MIN 819
412#define VDD_MV_MAX 1212
413
414/*
415 * Miscellaneous configurable options
416 */
417#define CONFIG_MISC_INIT_R
418#define CONFIG_SYS_LONGHELP /* undef to save memory */
419#define CONFIG_AUTO_COMPLETE
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800420
421#define CONFIG_SYS_MEMTEST_START 0x80000000
422#define CONFIG_SYS_MEMTEST_END 0x9fffffff
423
424#define CONFIG_SYS_HZ 1000
425
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800426#define CONFIG_SYS_INIT_SP_OFFSET \
427 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
428
429#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
430
431/*
432 * Environment
433 */
434#define CONFIG_ENV_OVERWRITE
435
436#ifdef CONFIG_NAND_BOOT
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800437#define CONFIG_ENV_SIZE 0x2000
Alison Wang42f37802017-05-16 10:45:59 +0800438#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800439#elif defined(CONFIG_SD_BOOT)
Alison Wang42f37802017-05-16 10:45:59 +0800440#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800441#define CONFIG_SYS_MMC_ENV_DEV 0
442#define CONFIG_ENV_SIZE 0x2000
443#elif defined(CONFIG_QSPI_BOOT)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800444#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
Alison Wang42f37802017-05-16 10:45:59 +0800445#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800446#define CONFIG_ENV_SECT_SIZE 0x10000
447#else
Alison Wang42f37802017-05-16 10:45:59 +0800448#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800449#define CONFIG_ENV_SECT_SIZE 0x20000
450#define CONFIG_ENV_SIZE 0x20000
451#endif
452
453#define CONFIG_CMDLINE_TAG
454
Qianyu Gong6264ab62017-06-15 11:10:09 +0800455#undef CONFIG_BOOTCOMMAND
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800456#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
457#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
458 "e0000 f00000 && bootm $kernel_load"
459#else
460#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
461 "$kernel_size && bootm $kernel_load"
462#endif
463
464#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
465#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
466 "14m(free)"
467#else
Wenbin Song94ac15f2017-03-24 18:05:48 +0800468#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
469 "2m@0x100000(nor_bank0_uboot),"\
470 "40m@0x1100000(nor_bank0_fit)," \
471 "7m(nor_bank0_user)," \
472 "2m@0x4100000(nor_bank4_uboot)," \
473 "40m@0x5100000(nor_bank4_fit),"\
474 "-(nor_bank4_user);" \
475 "7e800000.flash:" \
Shaohui Xie085ac1c2016-09-07 17:56:14 +0800476 "4m(nand_uboot),36m(nand_kernel)," \
477 "472m(nand_free);spi0.0:2m(uboot)," \
478 "14m(free)"
479#endif
480
481#include <asm/fsl_secure_boot.h>
482
483#endif /* __LS1046AQDS_H__ */